rockchip-vop.txt 1.7 KB

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  1. device-tree bindings for rockchip soc display controller (vop)
  2. VOP (Visual Output Processor) is the Display Controller for the Rockchip
  3. series of SoCs which transfers the image data from a video memory
  4. buffer to an external LCD interface.
  5. Required properties:
  6. - compatible: value should be one of the following
  7. "rockchip,rk3288-vop";
  8. - interrupts: should contain a list of all VOP IP block interrupts in the
  9. order: VSYNC, LCD_SYSTEM. The interrupt specifier
  10. format depends on the interrupt controller used.
  11. - clocks: must include clock specifiers corresponding to entries in the
  12. clock-names property.
  13. - clock-names: Must contain
  14. aclk_vop: for ddr buffer transfer.
  15. hclk_vop: for ahb bus to R/W the phy regs.
  16. dclk_vop: pixel clock.
  17. - resets: Must contain an entry for each entry in reset-names.
  18. See ../reset/reset.txt for details.
  19. - reset-names: Must include the following entries:
  20. - axi
  21. - ahb
  22. - dclk
  23. - iommus: required a iommu node
  24. - port: A port node with endpoint definitions as defined in
  25. Documentation/devicetree/bindings/media/video-interfaces.txt.
  26. Example:
  27. SoC specific DT entry:
  28. vopb: vopb@ff930000 {
  29. compatible = "rockchip,rk3288-vop";
  30. reg = <0xff930000 0x19c>;
  31. interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
  32. clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
  33. clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
  34. resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
  35. reset-names = "axi", "ahb", "dclk";
  36. iommus = <&vopb_mmu>;
  37. vopb_out: port {
  38. #address-cells = <1>;
  39. #size-cells = <0>;
  40. vopb_out_edp: endpoint@0 {
  41. reg = <0>;
  42. remote-endpoint=<&edp_in_vopb>;
  43. };
  44. vopb_out_hdmi: endpoint@1 {
  45. reg = <1>;
  46. remote-endpoint=<&hdmi_in_vopb>;
  47. };
  48. };
  49. };