fw-dma.txt 3.6 KB

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  1. This page describes the structures and procedures used by the cx2341x DMA
  2. engine.
  3. Introduction
  4. ============
  5. The cx2341x PCI interface is busmaster capable. This means it has a DMA
  6. engine to efficiently transfer large volumes of data between the card and main
  7. memory without requiring help from a CPU. Like most hardware, it must operate
  8. on contiguous physical memory. This is difficult to come by in large quantities
  9. on virtual memory machines.
  10. Therefore, it also supports a technique called "scatter-gather". The card can
  11. transfer multiple buffers in one operation. Instead of allocating one large
  12. contiguous buffer, the driver can allocate several smaller buffers.
  13. In practice, I've seen the average transfer to be roughly 80K, but transfers
  14. above 128K were not uncommon, particularly at startup. The 128K figure is
  15. important, because that is the largest block that the kernel can normally
  16. allocate. Even still, 128K blocks are hard to come by, so the driver writer is
  17. urged to choose a smaller block size and learn the scatter-gather technique.
  18. Mailbox #10 is reserved for DMA transfer information.
  19. Note: the hardware expects little-endian data ('intel format').
  20. Flow
  21. ====
  22. This section describes, in general, the order of events when handling DMA
  23. transfers. Detailed information follows this section.
  24. - The card raises the Encoder interrupt.
  25. - The driver reads the transfer type, offset and size from Mailbox #10.
  26. - The driver constructs the scatter-gather array from enough free dma buffers
  27. to cover the size.
  28. - The driver schedules the DMA transfer via the ScheduleDMAtoHost API call.
  29. - The card raises the DMA Complete interrupt.
  30. - The driver checks the DMA status register for any errors.
  31. - The driver post-processes the newly transferred buffers.
  32. NOTE! It is possible that the Encoder and DMA Complete interrupts get raised
  33. simultaneously. (End of the last, start of the next, etc.)
  34. Mailbox #10
  35. ===========
  36. The Flags, Command, Return Value and Timeout fields are ignored.
  37. Name: Mailbox #10
  38. Results[0]: Type: 0: MPEG.
  39. Results[1]: Offset: The position relative to the card's memory space.
  40. Results[2]: Size: The exact number of bytes to transfer.
  41. My speculation is that since the StartCapture API has a capture type of "RAW"
  42. available, that the type field will have other values that correspond to YUV
  43. and PCM data.
  44. Scatter-Gather Array
  45. ====================
  46. The scatter-gather array is a contiguously allocated block of memory that
  47. tells the card the source and destination of each data-block to transfer.
  48. Card "addresses" are derived from the offset supplied by Mailbox #10. Host
  49. addresses are the physical memory location of the target DMA buffer.
  50. Each S-G array element is a struct of three 32-bit words. The first word is
  51. the source address, the second is the destination address. Both take up the
  52. entire 32 bits. The lowest 18 bits of the third word is the transfer byte
  53. count. The high-bit of the third word is the "last" flag. The last-flag tells
  54. the card to raise the DMA_DONE interrupt. From hard personal experience, if
  55. you forget to set this bit, the card will still "work" but the stream will
  56. most likely get corrupted.
  57. The transfer count must be a multiple of 256. Therefore, the driver will need
  58. to track how much data in the target buffer is valid and deal with it
  59. accordingly.
  60. Array Element:
  61. - 32-bit Source Address
  62. - 32-bit Destination Address
  63. - 14-bit reserved (high bit is the last flag)
  64. - 18-bit byte count
  65. DMA Transfer Status
  66. ===================
  67. Register 0x0004 holds the DMA Transfer Status:
  68. Bit
  69. 0 read completed
  70. 1 write completed
  71. 2 DMA read error
  72. 3 DMA write error
  73. 4 Scatter-Gather array error