fpu.c 1.8 KB

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  1. /*
  2. * fpu.c - save/restore of Floating Point Unit Registers on task switch
  3. *
  4. * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/sched.h>
  11. #include <asm/switch_to.h>
  12. /*
  13. * To save/restore FPU regs, simplest scheme would use LR/SR insns.
  14. * However since SR serializes the pipeline, an alternate "hack" can be used
  15. * which uses the FPU Exchange insn (DEXCL) to r/w FPU regs.
  16. *
  17. * Store to 64bit dpfp1 reg from a pair of core regs:
  18. * dexcl1 0, r1, r0 ; where r1:r0 is the 64 bit val
  19. *
  20. * Read from dpfp1 into pair of core regs (w/o clobbering dpfp1)
  21. * mov_s r3, 0
  22. * daddh11 r1, r3, r3 ; get "hi" into r1 (dpfp1 unchanged)
  23. * dexcl1 r0, r1, r3 ; get "low" into r0 (dpfp1 low clobbered)
  24. * dexcl1 0, r1, r0 ; restore dpfp1 to orig value
  25. *
  26. * However we can tweak the read, so that read-out of outgoing task's FPU regs
  27. * and write of incoming task's regs happen in one shot. So all the work is
  28. * done before context switch
  29. */
  30. void fpu_save_restore(struct task_struct *prev, struct task_struct *next)
  31. {
  32. unsigned int *saveto = &prev->thread.fpu.aux_dpfp[0].l;
  33. unsigned int *readfrom = &next->thread.fpu.aux_dpfp[0].l;
  34. const unsigned int zero = 0;
  35. __asm__ __volatile__(
  36. "daddh11 %0, %2, %2\n"
  37. "dexcl1 %1, %3, %4\n"
  38. : "=&r" (*(saveto + 1)), /* early clobber must here */
  39. "=&r" (*(saveto))
  40. : "r" (zero), "r" (*(readfrom + 1)), "r" (*(readfrom))
  41. );
  42. __asm__ __volatile__(
  43. "daddh22 %0, %2, %2\n"
  44. "dexcl2 %1, %3, %4\n"
  45. : "=&r"(*(saveto + 3)), /* early clobber must here */
  46. "=&r"(*(saveto + 2))
  47. : "r" (zero), "r" (*(readfrom + 3)), "r" (*(readfrom + 2))
  48. );
  49. }