emif.c 2.0 KB

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  1. /*
  2. * External Memory Interface
  3. *
  4. * Copyright (C) 2011 Texas Instruments Incorporated
  5. * Author: Mark Salter <msalter@redhat.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/of.h>
  12. #include <linux/of_address.h>
  13. #include <linux/io.h>
  14. #include <asm/soc.h>
  15. #include <asm/dscr.h>
  16. #define NUM_EMIFA_CHIP_ENABLES 4
  17. struct emifa_regs {
  18. u32 midr;
  19. u32 stat;
  20. u32 reserved1[6];
  21. u32 bprio;
  22. u32 reserved2[23];
  23. u32 cecfg[NUM_EMIFA_CHIP_ENABLES];
  24. u32 reserved3[4];
  25. u32 awcc;
  26. u32 reserved4[7];
  27. u32 intraw;
  28. u32 intmsk;
  29. u32 intmskset;
  30. u32 intmskclr;
  31. };
  32. static struct of_device_id emifa_match[] __initdata = {
  33. { .compatible = "ti,c64x+emifa" },
  34. {}
  35. };
  36. /*
  37. * Parse device tree for existence of an EMIF (External Memory Interface)
  38. * and initialize it if found.
  39. */
  40. static int __init c6x_emifa_init(void)
  41. {
  42. struct emifa_regs __iomem *regs;
  43. struct device_node *node;
  44. const __be32 *p;
  45. u32 val;
  46. int i, len, err;
  47. node = of_find_matching_node(NULL, emifa_match);
  48. if (!node)
  49. return 0;
  50. regs = of_iomap(node, 0);
  51. if (!regs)
  52. return 0;
  53. /* look for a dscr-based enable for emifa pin buffers */
  54. err = of_property_read_u32_array(node, "ti,dscr-dev-enable", &val, 1);
  55. if (!err)
  56. dscr_set_devstate(val, DSCR_DEVSTATE_ENABLED);
  57. /* set up the chip enables */
  58. p = of_get_property(node, "ti,emifa-ce-config", &len);
  59. if (p) {
  60. len /= sizeof(u32);
  61. if (len > NUM_EMIFA_CHIP_ENABLES)
  62. len = NUM_EMIFA_CHIP_ENABLES;
  63. for (i = 0; i <= len; i++)
  64. soc_writel(be32_to_cpup(&p[i]), &regs->cecfg[i]);
  65. }
  66. err = of_property_read_u32_array(node, "ti,emifa-burst-priority", &val, 1);
  67. if (!err)
  68. soc_writel(val, &regs->bprio);
  69. err = of_property_read_u32_array(node, "ti,emifa-async-wait-control", &val, 1);
  70. if (!err)
  71. soc_writel(val, &regs->awcc);
  72. iounmap(regs);
  73. of_node_put(node);
  74. return 0;
  75. }
  76. pure_initcall(c6x_emifa_init);