setup.c 32 KB

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  1. /* setup.c: FRV specific setup
  2. *
  3. * Copyright (C) 2003-5 Red Hat, Inc. All Rights Reserved.
  4. * Written by David Howells (dhowells@redhat.com)
  5. * - Derived from arch/m68k/kernel/setup.c
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. */
  12. #include <generated/utsrelease.h>
  13. #include <linux/kernel.h>
  14. #include <linux/sched.h>
  15. #include <linux/delay.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/fs.h>
  18. #include <linux/mm.h>
  19. #include <linux/fb.h>
  20. #include <linux/console.h>
  21. #include <linux/genhd.h>
  22. #include <linux/errno.h>
  23. #include <linux/string.h>
  24. #include <linux/major.h>
  25. #include <linux/bootmem.h>
  26. #include <linux/highmem.h>
  27. #include <linux/seq_file.h>
  28. #include <linux/serial.h>
  29. #include <linux/serial_core.h>
  30. #include <linux/serial_reg.h>
  31. #include <linux/serial_8250.h>
  32. #include <asm/setup.h>
  33. #include <asm/irq.h>
  34. #include <asm/sections.h>
  35. #include <asm/pgalloc.h>
  36. #include <asm/busctl-regs.h>
  37. #include <asm/serial-regs.h>
  38. #include <asm/timer-regs.h>
  39. #include <asm/irc-regs.h>
  40. #include <asm/spr-regs.h>
  41. #include <asm/mb-regs.h>
  42. #include <asm/mb93493-regs.h>
  43. #include <asm/gdb-stub.h>
  44. #include <asm/io.h>
  45. #ifdef CONFIG_BLK_DEV_INITRD
  46. #include <asm/pgtable.h>
  47. #endif
  48. #include "local.h"
  49. #ifdef CONFIG_MB93090_MB00
  50. static void __init mb93090_display(void);
  51. #endif
  52. #ifdef CONFIG_MMU
  53. static void __init setup_linux_memory(void);
  54. #else
  55. static void __init setup_uclinux_memory(void);
  56. #endif
  57. #ifdef CONFIG_MB93090_MB00
  58. static char __initdata mb93090_banner[] = "FJ/RH FR-V Linux";
  59. static char __initdata mb93090_version[] = UTS_RELEASE;
  60. int __nongprelbss mb93090_mb00_detected;
  61. #endif
  62. const char __frv_unknown_system[] = "unknown";
  63. const char __frv_mb93091_cb10[] = "mb93091-cb10";
  64. const char __frv_mb93091_cb11[] = "mb93091-cb11";
  65. const char __frv_mb93091_cb30[] = "mb93091-cb30";
  66. const char __frv_mb93091_cb41[] = "mb93091-cb41";
  67. const char __frv_mb93091_cb60[] = "mb93091-cb60";
  68. const char __frv_mb93091_cb70[] = "mb93091-cb70";
  69. const char __frv_mb93091_cb451[] = "mb93091-cb451";
  70. const char __frv_mb93090_mb00[] = "mb93090-mb00";
  71. const char __frv_mb93493[] = "mb93493";
  72. const char __frv_mb93093[] = "mb93093";
  73. static const char *__nongprelbss cpu_series;
  74. static const char *__nongprelbss cpu_core;
  75. static const char *__nongprelbss cpu_silicon;
  76. static const char *__nongprelbss cpu_mmu;
  77. static const char *__nongprelbss cpu_system;
  78. static const char *__nongprelbss cpu_board1;
  79. static const char *__nongprelbss cpu_board2;
  80. static unsigned long __nongprelbss cpu_psr_all;
  81. static unsigned long __nongprelbss cpu_hsr0_all;
  82. unsigned long __nongprelbss pdm_suspend_mode;
  83. unsigned long __nongprelbss rom_length;
  84. unsigned long __nongprelbss memory_start;
  85. unsigned long __nongprelbss memory_end;
  86. unsigned long __nongprelbss dma_coherent_mem_start;
  87. unsigned long __nongprelbss dma_coherent_mem_end;
  88. unsigned long __initdata __sdram_old_base;
  89. unsigned long __initdata num_mappedpages;
  90. char __initdata command_line[COMMAND_LINE_SIZE];
  91. char __initdata redboot_command_line[COMMAND_LINE_SIZE];
  92. #ifdef CONFIG_PM
  93. #define __pminit
  94. #define __pminitdata
  95. #define __pminitconst
  96. #else
  97. #define __pminit __init
  98. #define __pminitdata __initdata
  99. #define __pminitconst __initconst
  100. #endif
  101. struct clock_cmode {
  102. uint8_t xbus, sdram, corebus, core, dsu;
  103. };
  104. #define _frac(N,D) ((N)<<4 | (D))
  105. #define _x0_16 _frac(1,6)
  106. #define _x0_25 _frac(1,4)
  107. #define _x0_33 _frac(1,3)
  108. #define _x0_375 _frac(3,8)
  109. #define _x0_5 _frac(1,2)
  110. #define _x0_66 _frac(2,3)
  111. #define _x0_75 _frac(3,4)
  112. #define _x1 _frac(1,1)
  113. #define _x1_5 _frac(3,2)
  114. #define _x2 _frac(2,1)
  115. #define _x3 _frac(3,1)
  116. #define _x4 _frac(4,1)
  117. #define _x4_5 _frac(9,2)
  118. #define _x6 _frac(6,1)
  119. #define _x8 _frac(8,1)
  120. #define _x9 _frac(9,1)
  121. int __nongprelbss clock_p0_current;
  122. int __nongprelbss clock_cm_current;
  123. int __nongprelbss clock_cmode_current;
  124. #ifdef CONFIG_PM
  125. int __nongprelbss clock_cmodes_permitted;
  126. unsigned long __nongprelbss clock_bits_settable;
  127. #endif
  128. static struct clock_cmode __pminitdata undef_clock_cmode = { _x1, _x1, _x1, _x1, _x1 };
  129. static struct clock_cmode __pminitdata clock_cmodes_fr401_fr403[16] = {
  130. [4] = { _x1, _x1, _x2, _x2, _x0_25 },
  131. [5] = { _x1, _x2, _x4, _x4, _x0_5 },
  132. [8] = { _x1, _x1, _x1, _x2, _x0_25 },
  133. [9] = { _x1, _x2, _x2, _x4, _x0_5 },
  134. [11] = { _x1, _x4, _x4, _x8, _x1 },
  135. [12] = { _x1, _x1, _x2, _x4, _x0_5 },
  136. [13] = { _x1, _x2, _x4, _x8, _x1 },
  137. };
  138. static struct clock_cmode __pminitdata clock_cmodes_fr405[16] = {
  139. [0] = { _x1, _x1, _x1, _x1, _x0_5 },
  140. [1] = { _x1, _x1, _x1, _x3, _x0_25 },
  141. [2] = { _x1, _x1, _x2, _x6, _x0_5 },
  142. [3] = { _x1, _x2, _x2, _x6, _x0_5 },
  143. [4] = { _x1, _x1, _x2, _x2, _x0_16 },
  144. [8] = { _x1, _x1, _x1, _x2, _x0_16 },
  145. [9] = { _x1, _x2, _x2, _x4, _x0_33 },
  146. [12] = { _x1, _x1, _x2, _x4, _x0_33 },
  147. [14] = { _x1, _x3, _x3, _x9, _x0_75 },
  148. [15] = { _x1, _x1_5, _x1_5, _x4_5, _x0_375 },
  149. #define CLOCK_CMODES_PERMITTED_FR405 0xd31f
  150. };
  151. static struct clock_cmode __pminitdata clock_cmodes_fr555[16] = {
  152. [0] = { _x1, _x2, _x2, _x4, _x0_33 },
  153. [1] = { _x1, _x3, _x3, _x6, _x0_5 },
  154. [2] = { _x1, _x2, _x4, _x8, _x0_66 },
  155. [3] = { _x1, _x1_5, _x3, _x6, _x0_5 },
  156. [4] = { _x1, _x3, _x3, _x9, _x0_75 },
  157. [5] = { _x1, _x2, _x2, _x6, _x0_5 },
  158. [6] = { _x1, _x1_5, _x1_5, _x4_5, _x0_375 },
  159. };
  160. static const struct clock_cmode __pminitconst *clock_cmodes;
  161. static int __pminitdata clock_doubled;
  162. static struct uart_port __pminitdata __frv_uart0 = {
  163. .uartclk = 0,
  164. .membase = (char *) UART0_BASE,
  165. .irq = IRQ_CPU_UART0,
  166. .regshift = 3,
  167. .iotype = UPIO_MEM,
  168. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
  169. };
  170. static struct uart_port __pminitdata __frv_uart1 = {
  171. .uartclk = 0,
  172. .membase = (char *) UART1_BASE,
  173. .irq = IRQ_CPU_UART1,
  174. .regshift = 3,
  175. .iotype = UPIO_MEM,
  176. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
  177. };
  178. #if 0
  179. static void __init printk_xampr(unsigned long ampr, unsigned long amlr, char i_d, int n)
  180. {
  181. unsigned long phys, virt, cxn, size;
  182. #ifdef CONFIG_MMU
  183. virt = amlr & 0xffffc000;
  184. cxn = amlr & 0x3fff;
  185. #else
  186. virt = ampr & 0xffffc000;
  187. cxn = 0;
  188. #endif
  189. phys = ampr & xAMPRx_PPFN;
  190. size = 1 << (((ampr & xAMPRx_SS) >> 4) + 17);
  191. printk("%cAMPR%d: va %08lx-%08lx [pa %08lx] %c%c%c%c [cxn:%04lx]\n",
  192. i_d, n,
  193. virt, virt + size - 1,
  194. phys,
  195. ampr & xAMPRx_S ? 'S' : '-',
  196. ampr & xAMPRx_C ? 'C' : '-',
  197. ampr & DAMPRx_WP ? 'W' : '-',
  198. ampr & xAMPRx_V ? 'V' : '-',
  199. cxn
  200. );
  201. }
  202. #endif
  203. /*****************************************************************************/
  204. /*
  205. * dump the memory map
  206. */
  207. static void __init dump_memory_map(void)
  208. {
  209. #if 0
  210. /* dump the protection map */
  211. printk_xampr(__get_IAMPR(0), __get_IAMLR(0), 'I', 0);
  212. printk_xampr(__get_IAMPR(1), __get_IAMLR(1), 'I', 1);
  213. printk_xampr(__get_IAMPR(2), __get_IAMLR(2), 'I', 2);
  214. printk_xampr(__get_IAMPR(3), __get_IAMLR(3), 'I', 3);
  215. printk_xampr(__get_IAMPR(4), __get_IAMLR(4), 'I', 4);
  216. printk_xampr(__get_IAMPR(5), __get_IAMLR(5), 'I', 5);
  217. printk_xampr(__get_IAMPR(6), __get_IAMLR(6), 'I', 6);
  218. printk_xampr(__get_IAMPR(7), __get_IAMLR(7), 'I', 7);
  219. printk_xampr(__get_IAMPR(8), __get_IAMLR(8), 'I', 8);
  220. printk_xampr(__get_IAMPR(9), __get_IAMLR(9), 'i', 9);
  221. printk_xampr(__get_IAMPR(10), __get_IAMLR(10), 'I', 10);
  222. printk_xampr(__get_IAMPR(11), __get_IAMLR(11), 'I', 11);
  223. printk_xampr(__get_IAMPR(12), __get_IAMLR(12), 'I', 12);
  224. printk_xampr(__get_IAMPR(13), __get_IAMLR(13), 'I', 13);
  225. printk_xampr(__get_IAMPR(14), __get_IAMLR(14), 'I', 14);
  226. printk_xampr(__get_IAMPR(15), __get_IAMLR(15), 'I', 15);
  227. printk_xampr(__get_DAMPR(0), __get_DAMLR(0), 'D', 0);
  228. printk_xampr(__get_DAMPR(1), __get_DAMLR(1), 'D', 1);
  229. printk_xampr(__get_DAMPR(2), __get_DAMLR(2), 'D', 2);
  230. printk_xampr(__get_DAMPR(3), __get_DAMLR(3), 'D', 3);
  231. printk_xampr(__get_DAMPR(4), __get_DAMLR(4), 'D', 4);
  232. printk_xampr(__get_DAMPR(5), __get_DAMLR(5), 'D', 5);
  233. printk_xampr(__get_DAMPR(6), __get_DAMLR(6), 'D', 6);
  234. printk_xampr(__get_DAMPR(7), __get_DAMLR(7), 'D', 7);
  235. printk_xampr(__get_DAMPR(8), __get_DAMLR(8), 'D', 8);
  236. printk_xampr(__get_DAMPR(9), __get_DAMLR(9), 'D', 9);
  237. printk_xampr(__get_DAMPR(10), __get_DAMLR(10), 'D', 10);
  238. printk_xampr(__get_DAMPR(11), __get_DAMLR(11), 'D', 11);
  239. printk_xampr(__get_DAMPR(12), __get_DAMLR(12), 'D', 12);
  240. printk_xampr(__get_DAMPR(13), __get_DAMLR(13), 'D', 13);
  241. printk_xampr(__get_DAMPR(14), __get_DAMLR(14), 'D', 14);
  242. printk_xampr(__get_DAMPR(15), __get_DAMLR(15), 'D', 15);
  243. #endif
  244. #if 0
  245. /* dump the bus controller registers */
  246. printk("LGCR: %08lx\n", __get_LGCR());
  247. printk("Master: %08lx-%08lx CR=%08lx\n",
  248. __get_LEMBR(), __get_LEMBR() + __get_LEMAM(),
  249. __get_LMAICR());
  250. int loop;
  251. for (loop = 1; loop <= 7; loop++) {
  252. unsigned long lcr = __get_LCR(loop), lsbr = __get_LSBR(loop);
  253. printk("CS#%d: %08lx-%08lx %c%c%c%c%c%c%c%c%c\n",
  254. loop,
  255. lsbr, lsbr + __get_LSAM(loop),
  256. lcr & 0x80000000 ? 'r' : '-',
  257. lcr & 0x40000000 ? 'w' : '-',
  258. lcr & 0x08000000 ? 'b' : '-',
  259. lcr & 0x04000000 ? 'B' : '-',
  260. lcr & 0x02000000 ? 'C' : '-',
  261. lcr & 0x01000000 ? 'D' : '-',
  262. lcr & 0x00800000 ? 'W' : '-',
  263. lcr & 0x00400000 ? 'R' : '-',
  264. (lcr & 0x00030000) == 0x00000000 ? '4' :
  265. (lcr & 0x00030000) == 0x00010000 ? '2' :
  266. (lcr & 0x00030000) == 0x00020000 ? '1' :
  267. '-'
  268. );
  269. }
  270. #endif
  271. #if 0
  272. printk("\n");
  273. #endif
  274. } /* end dump_memory_map() */
  275. /*****************************************************************************/
  276. /*
  277. * attempt to detect a VDK motherboard and DAV daughter board on an MB93091 system
  278. */
  279. #ifdef CONFIG_MB93091_VDK
  280. static void __init detect_mb93091(void)
  281. {
  282. #ifdef CONFIG_MB93090_MB00
  283. /* Detect CB70 without motherboard */
  284. if (!(cpu_system == __frv_mb93091_cb70 && ((*(unsigned short *)0xffc00030) & 0x100))) {
  285. cpu_board1 = __frv_mb93090_mb00;
  286. mb93090_mb00_detected = 1;
  287. }
  288. #endif
  289. #ifdef CONFIG_FUJITSU_MB93493
  290. cpu_board2 = __frv_mb93493;
  291. #endif
  292. } /* end detect_mb93091() */
  293. #endif
  294. /*****************************************************************************/
  295. /*
  296. * determine the CPU type and set appropriate parameters
  297. *
  298. * Family Series CPU Core Silicon Imple Vers
  299. * ----------------------------------------------------------
  300. * FR-V --+-> FR400 --+-> FR401 --+-> MB93401 02 00 [1]
  301. * | | |
  302. * | | +-> MB93401/A 02 01
  303. * | | |
  304. * | | +-> MB93403 02 02
  305. * | |
  306. * | +-> FR405 ----> MB93405 04 00
  307. * |
  308. * +-> FR450 ----> FR451 ----> MB93451 05 00
  309. * |
  310. * +-> FR500 ----> FR501 --+-> MB93501 01 01 [2]
  311. * | |
  312. * | +-> MB93501/A 01 02
  313. * |
  314. * +-> FR550 --+-> FR551 ----> MB93555 03 01
  315. *
  316. * [1] The MB93401 is an obsolete CPU replaced by the MB93401A
  317. * [2] The MB93501 is an obsolete CPU replaced by the MB93501A
  318. *
  319. * Imple is PSR(Processor Status Register)[31:28].
  320. * Vers is PSR(Processor Status Register)[27:24].
  321. *
  322. * A "Silicon" consists of CPU core and some on-chip peripherals.
  323. */
  324. static void __init determine_cpu(void)
  325. {
  326. unsigned long hsr0 = __get_HSR(0);
  327. unsigned long psr = __get_PSR();
  328. /* work out what selectable services the CPU supports */
  329. __set_PSR(psr | PSR_EM | PSR_EF | PSR_CM | PSR_NEM);
  330. cpu_psr_all = __get_PSR();
  331. __set_PSR(psr);
  332. __set_HSR(0, hsr0 | HSR0_GRLE | HSR0_GRHE | HSR0_FRLE | HSR0_FRHE);
  333. cpu_hsr0_all = __get_HSR(0);
  334. __set_HSR(0, hsr0);
  335. /* derive other service specs from the CPU type */
  336. cpu_series = "unknown";
  337. cpu_core = "unknown";
  338. cpu_silicon = "unknown";
  339. cpu_mmu = "Prot";
  340. cpu_system = __frv_unknown_system;
  341. clock_cmodes = NULL;
  342. clock_doubled = 0;
  343. #ifdef CONFIG_PM
  344. clock_bits_settable = CLOCK_BIT_CM_H | CLOCK_BIT_CM_M | CLOCK_BIT_P0;
  345. #endif
  346. switch (PSR_IMPLE(psr)) {
  347. case PSR_IMPLE_FR401:
  348. cpu_series = "fr400";
  349. cpu_core = "fr401";
  350. pdm_suspend_mode = HSR0_PDM_PLL_RUN;
  351. switch (PSR_VERSION(psr)) {
  352. case PSR_VERSION_FR401_MB93401:
  353. cpu_silicon = "mb93401";
  354. cpu_system = __frv_mb93091_cb10;
  355. clock_cmodes = clock_cmodes_fr401_fr403;
  356. clock_doubled = 1;
  357. break;
  358. case PSR_VERSION_FR401_MB93401A:
  359. cpu_silicon = "mb93401/A";
  360. cpu_system = __frv_mb93091_cb11;
  361. clock_cmodes = clock_cmodes_fr401_fr403;
  362. break;
  363. case PSR_VERSION_FR401_MB93403:
  364. cpu_silicon = "mb93403";
  365. #ifndef CONFIG_MB93093_PDK
  366. cpu_system = __frv_mb93091_cb30;
  367. #else
  368. cpu_system = __frv_mb93093;
  369. #endif
  370. clock_cmodes = clock_cmodes_fr401_fr403;
  371. break;
  372. default:
  373. break;
  374. }
  375. break;
  376. case PSR_IMPLE_FR405:
  377. cpu_series = "fr400";
  378. cpu_core = "fr405";
  379. pdm_suspend_mode = HSR0_PDM_PLL_STOP;
  380. switch (PSR_VERSION(psr)) {
  381. case PSR_VERSION_FR405_MB93405:
  382. cpu_silicon = "mb93405";
  383. cpu_system = __frv_mb93091_cb60;
  384. clock_cmodes = clock_cmodes_fr405;
  385. #ifdef CONFIG_PM
  386. clock_bits_settable |= CLOCK_BIT_CMODE;
  387. clock_cmodes_permitted = CLOCK_CMODES_PERMITTED_FR405;
  388. #endif
  389. /* the FPGA on the CB70 has extra registers
  390. * - it has 0x0046 in the VDK_ID FPGA register at 0x1a0, which is
  391. * how we tell the difference between it and a CB60
  392. */
  393. if (*(volatile unsigned short *) 0xffc001a0 == 0x0046)
  394. cpu_system = __frv_mb93091_cb70;
  395. break;
  396. default:
  397. break;
  398. }
  399. break;
  400. case PSR_IMPLE_FR451:
  401. cpu_series = "fr450";
  402. cpu_core = "fr451";
  403. pdm_suspend_mode = HSR0_PDM_PLL_STOP;
  404. #ifdef CONFIG_PM
  405. clock_bits_settable |= CLOCK_BIT_CMODE;
  406. clock_cmodes_permitted = CLOCK_CMODES_PERMITTED_FR405;
  407. #endif
  408. switch (PSR_VERSION(psr)) {
  409. case PSR_VERSION_FR451_MB93451:
  410. cpu_silicon = "mb93451";
  411. cpu_mmu = "Prot, SAT, xSAT, DAT";
  412. cpu_system = __frv_mb93091_cb451;
  413. clock_cmodes = clock_cmodes_fr405;
  414. break;
  415. default:
  416. break;
  417. }
  418. break;
  419. case PSR_IMPLE_FR501:
  420. cpu_series = "fr500";
  421. cpu_core = "fr501";
  422. pdm_suspend_mode = HSR0_PDM_PLL_STOP;
  423. switch (PSR_VERSION(psr)) {
  424. case PSR_VERSION_FR501_MB93501: cpu_silicon = "mb93501"; break;
  425. case PSR_VERSION_FR501_MB93501A: cpu_silicon = "mb93501/A"; break;
  426. default:
  427. break;
  428. }
  429. break;
  430. case PSR_IMPLE_FR551:
  431. cpu_series = "fr550";
  432. cpu_core = "fr551";
  433. pdm_suspend_mode = HSR0_PDM_PLL_RUN;
  434. switch (PSR_VERSION(psr)) {
  435. case PSR_VERSION_FR551_MB93555:
  436. cpu_silicon = "mb93555";
  437. cpu_mmu = "Prot, SAT";
  438. cpu_system = __frv_mb93091_cb41;
  439. clock_cmodes = clock_cmodes_fr555;
  440. clock_doubled = 1;
  441. break;
  442. default:
  443. break;
  444. }
  445. break;
  446. default:
  447. break;
  448. }
  449. printk("- Series:%s CPU:%s Silicon:%s\n",
  450. cpu_series, cpu_core, cpu_silicon);
  451. #ifdef CONFIG_MB93091_VDK
  452. detect_mb93091();
  453. #endif
  454. #if defined(CONFIG_MB93093_PDK) && defined(CONFIG_FUJITSU_MB93493)
  455. cpu_board2 = __frv_mb93493;
  456. #endif
  457. } /* end determine_cpu() */
  458. /*****************************************************************************/
  459. /*
  460. * calculate the bus clock speed
  461. */
  462. void __pminit determine_clocks(int verbose)
  463. {
  464. const struct clock_cmode *mode, *tmode;
  465. unsigned long clkc, psr, quot;
  466. clkc = __get_CLKC();
  467. psr = __get_PSR();
  468. clock_p0_current = !!(clkc & CLKC_P0);
  469. clock_cm_current = clkc & CLKC_CM;
  470. clock_cmode_current = (clkc & CLKC_CMODE) >> CLKC_CMODE_s;
  471. if (verbose)
  472. printk("psr=%08lx hsr0=%08lx clkc=%08lx\n", psr, __get_HSR(0), clkc);
  473. /* the CB70 has some alternative ways of setting the clock speed through switches accessed
  474. * through the FPGA. */
  475. if (cpu_system == __frv_mb93091_cb70) {
  476. unsigned short clkswr = *(volatile unsigned short *) 0xffc00104UL & 0x1fffUL;
  477. if (clkswr & 0x1000)
  478. __clkin_clock_speed_HZ = 60000000UL;
  479. else
  480. __clkin_clock_speed_HZ =
  481. ((clkswr >> 8) & 0xf) * 10000000 +
  482. ((clkswr >> 4) & 0xf) * 1000000 +
  483. ((clkswr ) & 0xf) * 100000;
  484. }
  485. /* the FR451 is currently fixed at 24MHz */
  486. else if (cpu_system == __frv_mb93091_cb451) {
  487. //__clkin_clock_speed_HZ = 24000000UL; // CB451-FPGA
  488. unsigned short clkswr = *(volatile unsigned short *) 0xffc00104UL & 0x1fffUL;
  489. if (clkswr & 0x1000)
  490. __clkin_clock_speed_HZ = 60000000UL;
  491. else
  492. __clkin_clock_speed_HZ =
  493. ((clkswr >> 8) & 0xf) * 10000000 +
  494. ((clkswr >> 4) & 0xf) * 1000000 +
  495. ((clkswr ) & 0xf) * 100000;
  496. }
  497. /* otherwise determine the clockspeed from VDK or other registers */
  498. else {
  499. __clkin_clock_speed_HZ = __get_CLKIN();
  500. }
  501. /* look up the appropriate clock relationships table entry */
  502. mode = &undef_clock_cmode;
  503. if (clock_cmodes) {
  504. tmode = &clock_cmodes[(clkc & CLKC_CMODE) >> CLKC_CMODE_s];
  505. if (tmode->xbus)
  506. mode = tmode;
  507. }
  508. #define CLOCK(SRC,RATIO) ((SRC) * (((RATIO) >> 4) & 0x0f) / ((RATIO) & 0x0f))
  509. if (clock_doubled)
  510. __clkin_clock_speed_HZ <<= 1;
  511. __ext_bus_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->xbus);
  512. __sdram_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->sdram);
  513. __dsu_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->dsu);
  514. switch (clkc & CLKC_CM) {
  515. case 0: /* High */
  516. __core_bus_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->corebus);
  517. __core_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->core);
  518. break;
  519. case 1: /* Medium */
  520. __core_bus_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->sdram);
  521. __core_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->sdram);
  522. break;
  523. case 2: /* Low; not supported */
  524. case 3: /* UNDEF */
  525. printk("Unsupported CLKC CM %ld\n", clkc & CLKC_CM);
  526. panic("Bye");
  527. }
  528. __res_bus_clock_speed_HZ = __ext_bus_clock_speed_HZ;
  529. if (clkc & CLKC_P0)
  530. __res_bus_clock_speed_HZ >>= 1;
  531. if (verbose) {
  532. printk("CLKIN: %lu.%3.3luMHz\n",
  533. __clkin_clock_speed_HZ / 1000000,
  534. (__clkin_clock_speed_HZ / 1000) % 1000);
  535. printk("CLKS:"
  536. " ext=%luMHz res=%luMHz sdram=%luMHz cbus=%luMHz core=%luMHz dsu=%luMHz\n",
  537. __ext_bus_clock_speed_HZ / 1000000,
  538. __res_bus_clock_speed_HZ / 1000000,
  539. __sdram_clock_speed_HZ / 1000000,
  540. __core_bus_clock_speed_HZ / 1000000,
  541. __core_clock_speed_HZ / 1000000,
  542. __dsu_clock_speed_HZ / 1000000
  543. );
  544. }
  545. /* calculate the number of __delay() loop iterations per sec (2 insn loop) */
  546. __delay_loops_MHz = __core_clock_speed_HZ / (1000000 * 2);
  547. /* set the serial prescaler */
  548. __serial_clock_speed_HZ = __res_bus_clock_speed_HZ;
  549. quot = 1;
  550. while (__serial_clock_speed_HZ / quot / 16 / 65536 > 3000)
  551. quot += 1;
  552. /* double the divisor if P0 is clear, so that if/when P0 is set, it's still achievable
  553. * - we have to be careful - dividing too much can mean we can't get 115200 baud
  554. */
  555. if (__serial_clock_speed_HZ > 32000000 && !(clkc & CLKC_P0))
  556. quot <<= 1;
  557. __serial_clock_speed_HZ /= quot;
  558. __frv_uart0.uartclk = __serial_clock_speed_HZ;
  559. __frv_uart1.uartclk = __serial_clock_speed_HZ;
  560. if (verbose)
  561. printk(" uart=%luMHz\n", __serial_clock_speed_HZ / 1000000 * quot);
  562. while (!(__get_UART0_LSR() & UART_LSR_TEMT))
  563. continue;
  564. while (!(__get_UART1_LSR() & UART_LSR_TEMT))
  565. continue;
  566. __set_UCPVR(quot);
  567. __set_UCPSR(0);
  568. } /* end determine_clocks() */
  569. /*****************************************************************************/
  570. /*
  571. * reserve some DMA consistent memory
  572. */
  573. #ifdef CONFIG_RESERVE_DMA_COHERENT
  574. static void __init reserve_dma_coherent(void)
  575. {
  576. unsigned long ampr;
  577. /* find the first non-kernel memory tile and steal it */
  578. #define __steal_AMPR(r) \
  579. if (__get_DAMPR(r) & xAMPRx_V) { \
  580. ampr = __get_DAMPR(r); \
  581. __set_DAMPR(r, ampr | xAMPRx_S | xAMPRx_C); \
  582. __set_IAMPR(r, 0); \
  583. goto found; \
  584. }
  585. __steal_AMPR(1);
  586. __steal_AMPR(2);
  587. __steal_AMPR(3);
  588. __steal_AMPR(4);
  589. __steal_AMPR(5);
  590. __steal_AMPR(6);
  591. if (PSR_IMPLE(__get_PSR()) == PSR_IMPLE_FR551) {
  592. __steal_AMPR(7);
  593. __steal_AMPR(8);
  594. __steal_AMPR(9);
  595. __steal_AMPR(10);
  596. __steal_AMPR(11);
  597. __steal_AMPR(12);
  598. __steal_AMPR(13);
  599. __steal_AMPR(14);
  600. }
  601. /* unable to grant any DMA consistent memory */
  602. printk("No DMA consistent memory reserved\n");
  603. return;
  604. found:
  605. dma_coherent_mem_start = ampr & xAMPRx_PPFN;
  606. ampr &= xAMPRx_SS;
  607. ampr >>= 4;
  608. ampr = 1 << (ampr - 3 + 20);
  609. dma_coherent_mem_end = dma_coherent_mem_start + ampr;
  610. printk("DMA consistent memory reserved %lx-%lx\n",
  611. dma_coherent_mem_start, dma_coherent_mem_end);
  612. } /* end reserve_dma_coherent() */
  613. #endif
  614. /*****************************************************************************/
  615. /*
  616. * calibrate the delay loop
  617. */
  618. void calibrate_delay(void)
  619. {
  620. loops_per_jiffy = __delay_loops_MHz * (1000000 / HZ);
  621. printk("Calibrating delay loop... %lu.%02lu BogoMIPS\n",
  622. loops_per_jiffy / (500000 / HZ),
  623. (loops_per_jiffy / (5000 / HZ)) % 100);
  624. } /* end calibrate_delay() */
  625. /*****************************************************************************/
  626. /*
  627. * look through the command line for some things we need to know immediately
  628. */
  629. static void __init parse_cmdline_early(char *cmdline)
  630. {
  631. if (!cmdline)
  632. return;
  633. while (*cmdline) {
  634. if (*cmdline == ' ')
  635. cmdline++;
  636. /* "mem=XXX[kKmM]" sets SDRAM size to <mem>, overriding the value we worked
  637. * out from the SDRAM controller mask register
  638. */
  639. if (!strncmp(cmdline, "mem=", 4)) {
  640. unsigned long long mem_size;
  641. mem_size = memparse(cmdline + 4, &cmdline);
  642. memory_end = memory_start + mem_size;
  643. }
  644. while (*cmdline && *cmdline != ' ')
  645. cmdline++;
  646. }
  647. } /* end parse_cmdline_early() */
  648. /*****************************************************************************/
  649. /*
  650. *
  651. */
  652. void __init setup_arch(char **cmdline_p)
  653. {
  654. #ifdef CONFIG_MMU
  655. printk("Linux FR-V port done by Red Hat Inc <dhowells@redhat.com>\n");
  656. #else
  657. printk("uClinux FR-V port done by Red Hat Inc <dhowells@redhat.com>\n");
  658. #endif
  659. memcpy(boot_command_line, redboot_command_line, COMMAND_LINE_SIZE);
  660. determine_cpu();
  661. determine_clocks(1);
  662. /* For printk-directly-beats-on-serial-hardware hack */
  663. console_set_baud(115200);
  664. #ifdef CONFIG_GDBSTUB
  665. gdbstub_set_baud(115200);
  666. #endif
  667. #ifdef CONFIG_RESERVE_DMA_COHERENT
  668. reserve_dma_coherent();
  669. #endif
  670. dump_memory_map();
  671. #ifdef CONFIG_MB93090_MB00
  672. if (mb93090_mb00_detected)
  673. mb93090_display();
  674. #endif
  675. /* register those serial ports that are available */
  676. #ifdef CONFIG_FRV_ONCPU_SERIAL
  677. #ifndef CONFIG_GDBSTUB_UART0
  678. __reg(UART0_BASE + UART_IER * 8) = 0;
  679. early_serial_setup(&__frv_uart0);
  680. #endif
  681. #ifndef CONFIG_GDBSTUB_UART1
  682. __reg(UART1_BASE + UART_IER * 8) = 0;
  683. early_serial_setup(&__frv_uart1);
  684. #endif
  685. #endif
  686. /* deal with the command line - RedBoot may have passed one to the kernel */
  687. memcpy(command_line, boot_command_line, sizeof(command_line));
  688. *cmdline_p = &command_line[0];
  689. parse_cmdline_early(command_line);
  690. /* set up the memory description
  691. * - by now the stack is part of the init task */
  692. printk("Memory %08lx-%08lx\n", memory_start, memory_end);
  693. BUG_ON(memory_start == memory_end);
  694. init_mm.start_code = (unsigned long) _stext;
  695. init_mm.end_code = (unsigned long) _etext;
  696. init_mm.end_data = (unsigned long) _edata;
  697. #if 0 /* DAVIDM - don't set brk just incase someone decides to use it */
  698. init_mm.brk = (unsigned long) &_end;
  699. #else
  700. init_mm.brk = (unsigned long) 0;
  701. #endif
  702. #ifdef DEBUG
  703. printk("KERNEL -> TEXT=0x%p-0x%p DATA=0x%p-0x%p BSS=0x%p-0x%p\n",
  704. _stext, _etext, _sdata, _edata, __bss_start, __bss_stop);
  705. #endif
  706. #ifdef CONFIG_VT
  707. #if defined(CONFIG_VGA_CONSOLE)
  708. conswitchp = &vga_con;
  709. #elif defined(CONFIG_DUMMY_CONSOLE)
  710. conswitchp = &dummy_con;
  711. #endif
  712. #endif
  713. #ifdef CONFIG_MMU
  714. setup_linux_memory();
  715. #else
  716. setup_uclinux_memory();
  717. #endif
  718. /* get kmalloc into gear */
  719. paging_init();
  720. /* init DMA */
  721. frv_dma_init();
  722. #ifdef DEBUG
  723. printk("Done setup_arch\n");
  724. #endif
  725. /* start the decrement timer running */
  726. // asm volatile("movgs %0,timerd" :: "r"(10000000));
  727. // __set_HSR(0, __get_HSR(0) | HSR0_ETMD);
  728. } /* end setup_arch() */
  729. #if 0
  730. /*****************************************************************************/
  731. /*
  732. *
  733. */
  734. static int setup_arch_serial(void)
  735. {
  736. /* register those serial ports that are available */
  737. #ifndef CONFIG_GDBSTUB_UART0
  738. early_serial_setup(&__frv_uart0);
  739. #endif
  740. #ifndef CONFIG_GDBSTUB_UART1
  741. early_serial_setup(&__frv_uart1);
  742. #endif
  743. return 0;
  744. } /* end setup_arch_serial() */
  745. late_initcall(setup_arch_serial);
  746. #endif
  747. /*****************************************************************************/
  748. /*
  749. * set up the memory map for normal MMU linux
  750. */
  751. #ifdef CONFIG_MMU
  752. static void __init setup_linux_memory(void)
  753. {
  754. unsigned long bootmap_size, low_top_pfn, kstart, kend, high_mem;
  755. unsigned long physpages;
  756. kstart = (unsigned long) &__kernel_image_start - PAGE_OFFSET;
  757. kend = (unsigned long) &__kernel_image_end - PAGE_OFFSET;
  758. kstart = kstart & PAGE_MASK;
  759. kend = (kend + PAGE_SIZE - 1) & PAGE_MASK;
  760. /* give all the memory to the bootmap allocator, tell it to put the
  761. * boot mem_map immediately following the kernel image
  762. */
  763. bootmap_size = init_bootmem_node(NODE_DATA(0),
  764. kend >> PAGE_SHIFT, /* map addr */
  765. memory_start >> PAGE_SHIFT, /* start of RAM */
  766. memory_end >> PAGE_SHIFT /* end of RAM */
  767. );
  768. /* pass the memory that the kernel can immediately use over to the bootmem allocator */
  769. max_mapnr = physpages = (memory_end - memory_start) >> PAGE_SHIFT;
  770. low_top_pfn = (KERNEL_LOWMEM_END - KERNEL_LOWMEM_START) >> PAGE_SHIFT;
  771. high_mem = 0;
  772. if (physpages > low_top_pfn) {
  773. #ifdef CONFIG_HIGHMEM
  774. high_mem = physpages - low_top_pfn;
  775. #else
  776. max_mapnr = physpages = low_top_pfn;
  777. #endif
  778. }
  779. else {
  780. low_top_pfn = physpages;
  781. }
  782. min_low_pfn = memory_start >> PAGE_SHIFT;
  783. max_low_pfn = low_top_pfn;
  784. max_pfn = memory_end >> PAGE_SHIFT;
  785. num_mappedpages = low_top_pfn;
  786. printk(KERN_NOTICE "%ldMB LOWMEM available.\n", low_top_pfn >> (20 - PAGE_SHIFT));
  787. free_bootmem(memory_start, low_top_pfn << PAGE_SHIFT);
  788. #ifdef CONFIG_HIGHMEM
  789. if (high_mem)
  790. printk(KERN_NOTICE "%ldMB HIGHMEM available.\n", high_mem >> (20 - PAGE_SHIFT));
  791. #endif
  792. /* take back the memory occupied by the kernel image and the bootmem alloc map */
  793. reserve_bootmem(kstart, kend - kstart + bootmap_size,
  794. BOOTMEM_DEFAULT);
  795. /* reserve the memory occupied by the initial ramdisk */
  796. #ifdef CONFIG_BLK_DEV_INITRD
  797. if (LOADER_TYPE && INITRD_START) {
  798. if (INITRD_START + INITRD_SIZE <= (low_top_pfn << PAGE_SHIFT)) {
  799. reserve_bootmem(INITRD_START, INITRD_SIZE,
  800. BOOTMEM_DEFAULT);
  801. initrd_start = INITRD_START + PAGE_OFFSET;
  802. initrd_end = initrd_start + INITRD_SIZE;
  803. }
  804. else {
  805. printk(KERN_ERR
  806. "initrd extends beyond end of memory (0x%08lx > 0x%08lx)\n"
  807. "disabling initrd\n",
  808. INITRD_START + INITRD_SIZE,
  809. low_top_pfn << PAGE_SHIFT);
  810. initrd_start = 0;
  811. }
  812. }
  813. #endif
  814. } /* end setup_linux_memory() */
  815. #endif
  816. /*****************************************************************************/
  817. /*
  818. * set up the memory map for uClinux
  819. */
  820. #ifndef CONFIG_MMU
  821. static void __init setup_uclinux_memory(void)
  822. {
  823. #ifdef CONFIG_PROTECT_KERNEL
  824. unsigned long dampr;
  825. #endif
  826. unsigned long kend;
  827. int bootmap_size;
  828. kend = (unsigned long) &__kernel_image_end;
  829. kend = (kend + PAGE_SIZE - 1) & PAGE_MASK;
  830. /* give all the memory to the bootmap allocator, tell it to put the
  831. * boot mem_map immediately following the kernel image
  832. */
  833. bootmap_size = init_bootmem_node(NODE_DATA(0),
  834. kend >> PAGE_SHIFT, /* map addr */
  835. memory_start >> PAGE_SHIFT, /* start of RAM */
  836. memory_end >> PAGE_SHIFT /* end of RAM */
  837. );
  838. /* free all the usable memory */
  839. free_bootmem(memory_start, memory_end - memory_start);
  840. high_memory = (void *) (memory_end & PAGE_MASK);
  841. max_mapnr = ((unsigned long) high_memory - PAGE_OFFSET) >> PAGE_SHIFT;
  842. min_low_pfn = memory_start >> PAGE_SHIFT;
  843. max_low_pfn = memory_end >> PAGE_SHIFT;
  844. max_pfn = max_low_pfn;
  845. /* now take back the bits the core kernel is occupying */
  846. #ifndef CONFIG_PROTECT_KERNEL
  847. reserve_bootmem(kend, bootmap_size, BOOTMEM_DEFAULT);
  848. reserve_bootmem((unsigned long) &__kernel_image_start,
  849. kend - (unsigned long) &__kernel_image_start,
  850. BOOTMEM_DEFAULT);
  851. #else
  852. dampr = __get_DAMPR(0);
  853. dampr &= xAMPRx_SS;
  854. dampr = (dampr >> 4) + 17;
  855. dampr = 1 << dampr;
  856. reserve_bootmem(__get_DAMPR(0) & xAMPRx_PPFN, dampr, BOOTMEM_DEFAULT);
  857. #endif
  858. /* reserve some memory to do uncached DMA through if requested */
  859. #ifdef CONFIG_RESERVE_DMA_COHERENT
  860. if (dma_coherent_mem_start)
  861. reserve_bootmem(dma_coherent_mem_start,
  862. dma_coherent_mem_end - dma_coherent_mem_start,
  863. BOOTMEM_DEFAULT);
  864. #endif
  865. } /* end setup_uclinux_memory() */
  866. #endif
  867. /*****************************************************************************/
  868. /*
  869. * get CPU information for use by procfs
  870. */
  871. static int show_cpuinfo(struct seq_file *m, void *v)
  872. {
  873. const char *gr, *fr, *fm, *fp, *cm, *nem, *ble;
  874. #ifdef CONFIG_PM
  875. const char *sep;
  876. #endif
  877. gr = cpu_hsr0_all & HSR0_GRHE ? "gr0-63" : "gr0-31";
  878. fr = cpu_hsr0_all & HSR0_FRHE ? "fr0-63" : "fr0-31";
  879. fm = cpu_psr_all & PSR_EM ? ", Media" : "";
  880. fp = cpu_psr_all & PSR_EF ? ", FPU" : "";
  881. cm = cpu_psr_all & PSR_CM ? ", CCCR" : "";
  882. nem = cpu_psr_all & PSR_NEM ? ", NE" : "";
  883. ble = cpu_psr_all & PSR_BE ? "BE" : "LE";
  884. seq_printf(m,
  885. "CPU-Series:\t%s\n"
  886. "CPU-Core:\t%s, %s, %s%s%s\n"
  887. "CPU:\t\t%s\n"
  888. "MMU:\t\t%s\n"
  889. "FP-Media:\t%s%s%s\n"
  890. "System:\t\t%s",
  891. cpu_series,
  892. cpu_core, gr, ble, cm, nem,
  893. cpu_silicon,
  894. cpu_mmu,
  895. fr, fm, fp,
  896. cpu_system);
  897. if (cpu_board1)
  898. seq_printf(m, ", %s", cpu_board1);
  899. if (cpu_board2)
  900. seq_printf(m, ", %s", cpu_board2);
  901. seq_printf(m, "\n");
  902. #ifdef CONFIG_PM
  903. seq_printf(m, "PM-Controls:");
  904. sep = "\t";
  905. if (clock_bits_settable & CLOCK_BIT_CMODE) {
  906. seq_printf(m, "%scmode=0x%04hx", sep, clock_cmodes_permitted);
  907. sep = ", ";
  908. }
  909. if (clock_bits_settable & CLOCK_BIT_CM) {
  910. seq_printf(m, "%scm=0x%lx", sep, clock_bits_settable & CLOCK_BIT_CM);
  911. sep = ", ";
  912. }
  913. if (clock_bits_settable & CLOCK_BIT_P0) {
  914. seq_printf(m, "%sp0=0x3", sep);
  915. sep = ", ";
  916. }
  917. seq_printf(m, "%ssuspend=0x22\n", sep);
  918. #endif
  919. seq_printf(m,
  920. "PM-Status:\tcmode=%d, cm=%d, p0=%d\n",
  921. clock_cmode_current, clock_cm_current, clock_p0_current);
  922. #define print_clk(TAG, VAR) \
  923. seq_printf(m, "Clock-" TAG ":\t%lu.%2.2lu MHz\n", VAR / 1000000, (VAR / 10000) % 100)
  924. print_clk("In", __clkin_clock_speed_HZ);
  925. print_clk("Core", __core_clock_speed_HZ);
  926. print_clk("SDRAM", __sdram_clock_speed_HZ);
  927. print_clk("CBus", __core_bus_clock_speed_HZ);
  928. print_clk("Res", __res_bus_clock_speed_HZ);
  929. print_clk("Ext", __ext_bus_clock_speed_HZ);
  930. print_clk("DSU", __dsu_clock_speed_HZ);
  931. seq_printf(m,
  932. "BogoMips:\t%lu.%02lu\n",
  933. (loops_per_jiffy * HZ) / 500000, ((loops_per_jiffy * HZ) / 5000) % 100);
  934. return 0;
  935. } /* end show_cpuinfo() */
  936. static void *c_start(struct seq_file *m, loff_t *pos)
  937. {
  938. return *pos < NR_CPUS ? (void *) 0x12345678 : NULL;
  939. }
  940. static void *c_next(struct seq_file *m, void *v, loff_t *pos)
  941. {
  942. ++*pos;
  943. return c_start(m, pos);
  944. }
  945. static void c_stop(struct seq_file *m, void *v)
  946. {
  947. }
  948. const struct seq_operations cpuinfo_op = {
  949. .start = c_start,
  950. .next = c_next,
  951. .stop = c_stop,
  952. .show = show_cpuinfo,
  953. };
  954. void arch_gettod(int *year, int *mon, int *day, int *hour,
  955. int *min, int *sec)
  956. {
  957. *year = *mon = *day = *hour = *min = *sec = 0;
  958. }
  959. /*****************************************************************************/
  960. /*
  961. *
  962. */
  963. #ifdef CONFIG_MB93090_MB00
  964. static void __init mb93090_sendlcdcmd(uint32_t cmd)
  965. {
  966. unsigned long base = __addr_LCD();
  967. int loop;
  968. /* request reading of the busy flag */
  969. __set_LCD(base, LCD_CMD_READ_BUSY);
  970. __set_LCD(base, LCD_CMD_READ_BUSY & ~LCD_E);
  971. /* wait for the busy flag to become clear */
  972. for (loop = 10000; loop > 0; loop--)
  973. if (!(__get_LCD(base) & 0x80))
  974. break;
  975. /* send the command */
  976. __set_LCD(base, cmd);
  977. __set_LCD(base, cmd & ~LCD_E);
  978. } /* end mb93090_sendlcdcmd() */
  979. /*****************************************************************************/
  980. /*
  981. * write to the MB93090 LEDs and LCD
  982. */
  983. static void __init mb93090_display(void)
  984. {
  985. const char *p;
  986. __set_LEDS(0);
  987. /* set up the LCD */
  988. mb93090_sendlcdcmd(LCD_CMD_CLEAR);
  989. mb93090_sendlcdcmd(LCD_CMD_FUNCSET(1,1,0));
  990. mb93090_sendlcdcmd(LCD_CMD_ON(0,0));
  991. mb93090_sendlcdcmd(LCD_CMD_HOME);
  992. mb93090_sendlcdcmd(LCD_CMD_SET_DD_ADDR(0));
  993. for (p = mb93090_banner; *p; p++)
  994. mb93090_sendlcdcmd(LCD_DATA_WRITE(*p));
  995. mb93090_sendlcdcmd(LCD_CMD_SET_DD_ADDR(64));
  996. for (p = mb93090_version; *p; p++)
  997. mb93090_sendlcdcmd(LCD_DATA_WRITE(*p));
  998. } /* end mb93090_display() */
  999. #endif // CONFIG_MB93090_MB00