irq.c 4.7 KB

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  1. /*
  2. * linux/arch/ia64/kernel/irq.c
  3. *
  4. * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
  5. *
  6. * This file contains the code used by various IRQ handling routines:
  7. * asking for different IRQs should be done through these routines
  8. * instead of just grabbing them. Thus setups with different IRQ numbers
  9. * shouldn't result in any weird surprises, and installing new handlers
  10. * should be easier.
  11. *
  12. * Copyright (C) Ashok Raj<ashok.raj@intel.com>, Intel Corporation 2004
  13. *
  14. * 4/14/2004: Added code to handle cpu migration and do safe irq
  15. * migration without losing interrupts for iosapic
  16. * architecture.
  17. */
  18. #include <asm/delay.h>
  19. #include <asm/uaccess.h>
  20. #include <linux/module.h>
  21. #include <linux/seq_file.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/kernel_stat.h>
  24. #include <asm/mca.h>
  25. /*
  26. * 'what should we do if we get a hw irq event on an illegal vector'.
  27. * each architecture has to answer this themselves.
  28. */
  29. void ack_bad_irq(unsigned int irq)
  30. {
  31. printk(KERN_ERR "Unexpected irq vector 0x%x on CPU %u!\n", irq, smp_processor_id());
  32. }
  33. #ifdef CONFIG_IA64_GENERIC
  34. ia64_vector __ia64_irq_to_vector(int irq)
  35. {
  36. return irq_cfg[irq].vector;
  37. }
  38. unsigned int __ia64_local_vector_to_irq (ia64_vector vec)
  39. {
  40. return __this_cpu_read(vector_irq[vec]);
  41. }
  42. #endif
  43. /*
  44. * Interrupt statistics:
  45. */
  46. atomic_t irq_err_count;
  47. /*
  48. * /proc/interrupts printing:
  49. */
  50. int arch_show_interrupts(struct seq_file *p, int prec)
  51. {
  52. seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
  53. return 0;
  54. }
  55. #ifdef CONFIG_SMP
  56. static char irq_redir [NR_IRQS]; // = { [0 ... NR_IRQS-1] = 1 };
  57. void set_irq_affinity_info (unsigned int irq, int hwid, int redir)
  58. {
  59. if (irq < NR_IRQS) {
  60. cpumask_copy(irq_get_affinity_mask(irq),
  61. cpumask_of(cpu_logical_id(hwid)));
  62. irq_redir[irq] = (char) (redir & 0xff);
  63. }
  64. }
  65. bool is_affinity_mask_valid(const struct cpumask *cpumask)
  66. {
  67. if (ia64_platform_is("sn2")) {
  68. /* Only allow one CPU to be specified in the smp_affinity mask */
  69. if (cpumask_weight(cpumask) != 1)
  70. return false;
  71. }
  72. return true;
  73. }
  74. #endif /* CONFIG_SMP */
  75. int __init arch_early_irq_init(void)
  76. {
  77. ia64_mca_irq_init();
  78. return 0;
  79. }
  80. #ifdef CONFIG_HOTPLUG_CPU
  81. unsigned int vectors_in_migration[NR_IRQS];
  82. /*
  83. * Since cpu_online_mask is already updated, we just need to check for
  84. * affinity that has zeros
  85. */
  86. static void migrate_irqs(void)
  87. {
  88. int irq, new_cpu;
  89. for (irq=0; irq < NR_IRQS; irq++) {
  90. struct irq_desc *desc = irq_to_desc(irq);
  91. struct irq_data *data = irq_desc_get_irq_data(desc);
  92. struct irq_chip *chip = irq_data_get_irq_chip(data);
  93. if (irqd_irq_disabled(data))
  94. continue;
  95. /*
  96. * No handling for now.
  97. * TBD: Implement a disable function so we can now
  98. * tell CPU not to respond to these local intr sources.
  99. * such as ITV,CPEI,MCA etc.
  100. */
  101. if (irqd_is_per_cpu(data))
  102. continue;
  103. if (cpumask_any_and(irq_data_get_affinity_mask(data),
  104. cpu_online_mask) >= nr_cpu_ids) {
  105. /*
  106. * Save it for phase 2 processing
  107. */
  108. vectors_in_migration[irq] = irq;
  109. new_cpu = cpumask_any(cpu_online_mask);
  110. /*
  111. * Al three are essential, currently WARN_ON.. maybe panic?
  112. */
  113. if (chip && chip->irq_disable &&
  114. chip->irq_enable && chip->irq_set_affinity) {
  115. chip->irq_disable(data);
  116. chip->irq_set_affinity(data,
  117. cpumask_of(new_cpu), false);
  118. chip->irq_enable(data);
  119. } else {
  120. WARN_ON((!chip || !chip->irq_disable ||
  121. !chip->irq_enable ||
  122. !chip->irq_set_affinity));
  123. }
  124. }
  125. }
  126. }
  127. void fixup_irqs(void)
  128. {
  129. unsigned int irq;
  130. extern void ia64_process_pending_intr(void);
  131. extern volatile int time_keeper_id;
  132. /* Mask ITV to disable timer */
  133. ia64_set_itv(1 << 16);
  134. /*
  135. * Find a new timesync master
  136. */
  137. if (smp_processor_id() == time_keeper_id) {
  138. time_keeper_id = cpumask_first(cpu_online_mask);
  139. printk ("CPU %d is now promoted to time-keeper master\n", time_keeper_id);
  140. }
  141. /*
  142. * Phase 1: Locate IRQs bound to this cpu and
  143. * relocate them for cpu removal.
  144. */
  145. migrate_irqs();
  146. /*
  147. * Phase 2: Perform interrupt processing for all entries reported in
  148. * local APIC.
  149. */
  150. ia64_process_pending_intr();
  151. /*
  152. * Phase 3: Now handle any interrupts not captured in local APIC.
  153. * This is to account for cases that device interrupted during the time the
  154. * rte was being disabled and re-programmed.
  155. */
  156. for (irq=0; irq < NR_IRQS; irq++) {
  157. if (vectors_in_migration[irq]) {
  158. struct pt_regs *old_regs = set_irq_regs(NULL);
  159. vectors_in_migration[irq]=0;
  160. generic_handle_irq(irq);
  161. set_irq_regs(old_regs);
  162. }
  163. }
  164. /*
  165. * Now let processor die. We do irq disable and max_xtp() to
  166. * ensure there is no more interrupts routed to this processor.
  167. * But the local timer interrupt can have 1 pending which we
  168. * take care in timer_interrupt().
  169. */
  170. max_xtp();
  171. local_irq_disable();
  172. }
  173. #endif