ptrace.c 57 KB

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  1. /*
  2. * Kernel support for the ptrace() and syscall tracing interfaces.
  3. *
  4. * Copyright (C) 1999-2005 Hewlett-Packard Co
  5. * David Mosberger-Tang <davidm@hpl.hp.com>
  6. * Copyright (C) 2006 Intel Co
  7. * 2006-08-12 - IA64 Native Utrace implementation support added by
  8. * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
  9. *
  10. * Derived from the x86 and Alpha versions.
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/sched.h>
  14. #include <linux/mm.h>
  15. #include <linux/errno.h>
  16. #include <linux/ptrace.h>
  17. #include <linux/user.h>
  18. #include <linux/security.h>
  19. #include <linux/audit.h>
  20. #include <linux/signal.h>
  21. #include <linux/regset.h>
  22. #include <linux/elf.h>
  23. #include <linux/tracehook.h>
  24. #include <asm/pgtable.h>
  25. #include <asm/processor.h>
  26. #include <asm/ptrace_offsets.h>
  27. #include <asm/rse.h>
  28. #include <asm/uaccess.h>
  29. #include <asm/unwind.h>
  30. #ifdef CONFIG_PERFMON
  31. #include <asm/perfmon.h>
  32. #endif
  33. #include "entry.h"
  34. /*
  35. * Bits in the PSR that we allow ptrace() to change:
  36. * be, up, ac, mfl, mfh (the user mask; five bits total)
  37. * db (debug breakpoint fault; one bit)
  38. * id (instruction debug fault disable; one bit)
  39. * dd (data debug fault disable; one bit)
  40. * ri (restart instruction; two bits)
  41. * is (instruction set; one bit)
  42. */
  43. #define IPSR_MASK (IA64_PSR_UM | IA64_PSR_DB | IA64_PSR_IS \
  44. | IA64_PSR_ID | IA64_PSR_DD | IA64_PSR_RI)
  45. #define MASK(nbits) ((1UL << (nbits)) - 1) /* mask with NBITS bits set */
  46. #define PFM_MASK MASK(38)
  47. #define PTRACE_DEBUG 0
  48. #if PTRACE_DEBUG
  49. # define dprintk(format...) printk(format)
  50. # define inline
  51. #else
  52. # define dprintk(format...)
  53. #endif
  54. /* Return TRUE if PT was created due to kernel-entry via a system-call. */
  55. static inline int
  56. in_syscall (struct pt_regs *pt)
  57. {
  58. return (long) pt->cr_ifs >= 0;
  59. }
  60. /*
  61. * Collect the NaT bits for r1-r31 from scratch_unat and return a NaT
  62. * bitset where bit i is set iff the NaT bit of register i is set.
  63. */
  64. unsigned long
  65. ia64_get_scratch_nat_bits (struct pt_regs *pt, unsigned long scratch_unat)
  66. {
  67. # define GET_BITS(first, last, unat) \
  68. ({ \
  69. unsigned long bit = ia64_unat_pos(&pt->r##first); \
  70. unsigned long nbits = (last - first + 1); \
  71. unsigned long mask = MASK(nbits) << first; \
  72. unsigned long dist; \
  73. if (bit < first) \
  74. dist = 64 + bit - first; \
  75. else \
  76. dist = bit - first; \
  77. ia64_rotr(unat, dist) & mask; \
  78. })
  79. unsigned long val;
  80. /*
  81. * Registers that are stored consecutively in struct pt_regs
  82. * can be handled in parallel. If the register order in
  83. * struct_pt_regs changes, this code MUST be updated.
  84. */
  85. val = GET_BITS( 1, 1, scratch_unat);
  86. val |= GET_BITS( 2, 3, scratch_unat);
  87. val |= GET_BITS(12, 13, scratch_unat);
  88. val |= GET_BITS(14, 14, scratch_unat);
  89. val |= GET_BITS(15, 15, scratch_unat);
  90. val |= GET_BITS( 8, 11, scratch_unat);
  91. val |= GET_BITS(16, 31, scratch_unat);
  92. return val;
  93. # undef GET_BITS
  94. }
  95. /*
  96. * Set the NaT bits for the scratch registers according to NAT and
  97. * return the resulting unat (assuming the scratch registers are
  98. * stored in PT).
  99. */
  100. unsigned long
  101. ia64_put_scratch_nat_bits (struct pt_regs *pt, unsigned long nat)
  102. {
  103. # define PUT_BITS(first, last, nat) \
  104. ({ \
  105. unsigned long bit = ia64_unat_pos(&pt->r##first); \
  106. unsigned long nbits = (last - first + 1); \
  107. unsigned long mask = MASK(nbits) << first; \
  108. long dist; \
  109. if (bit < first) \
  110. dist = 64 + bit - first; \
  111. else \
  112. dist = bit - first; \
  113. ia64_rotl(nat & mask, dist); \
  114. })
  115. unsigned long scratch_unat;
  116. /*
  117. * Registers that are stored consecutively in struct pt_regs
  118. * can be handled in parallel. If the register order in
  119. * struct_pt_regs changes, this code MUST be updated.
  120. */
  121. scratch_unat = PUT_BITS( 1, 1, nat);
  122. scratch_unat |= PUT_BITS( 2, 3, nat);
  123. scratch_unat |= PUT_BITS(12, 13, nat);
  124. scratch_unat |= PUT_BITS(14, 14, nat);
  125. scratch_unat |= PUT_BITS(15, 15, nat);
  126. scratch_unat |= PUT_BITS( 8, 11, nat);
  127. scratch_unat |= PUT_BITS(16, 31, nat);
  128. return scratch_unat;
  129. # undef PUT_BITS
  130. }
  131. #define IA64_MLX_TEMPLATE 0x2
  132. #define IA64_MOVL_OPCODE 6
  133. void
  134. ia64_increment_ip (struct pt_regs *regs)
  135. {
  136. unsigned long w0, ri = ia64_psr(regs)->ri + 1;
  137. if (ri > 2) {
  138. ri = 0;
  139. regs->cr_iip += 16;
  140. } else if (ri == 2) {
  141. get_user(w0, (char __user *) regs->cr_iip + 0);
  142. if (((w0 >> 1) & 0xf) == IA64_MLX_TEMPLATE) {
  143. /*
  144. * rfi'ing to slot 2 of an MLX bundle causes
  145. * an illegal operation fault. We don't want
  146. * that to happen...
  147. */
  148. ri = 0;
  149. regs->cr_iip += 16;
  150. }
  151. }
  152. ia64_psr(regs)->ri = ri;
  153. }
  154. void
  155. ia64_decrement_ip (struct pt_regs *regs)
  156. {
  157. unsigned long w0, ri = ia64_psr(regs)->ri - 1;
  158. if (ia64_psr(regs)->ri == 0) {
  159. regs->cr_iip -= 16;
  160. ri = 2;
  161. get_user(w0, (char __user *) regs->cr_iip + 0);
  162. if (((w0 >> 1) & 0xf) == IA64_MLX_TEMPLATE) {
  163. /*
  164. * rfi'ing to slot 2 of an MLX bundle causes
  165. * an illegal operation fault. We don't want
  166. * that to happen...
  167. */
  168. ri = 1;
  169. }
  170. }
  171. ia64_psr(regs)->ri = ri;
  172. }
  173. /*
  174. * This routine is used to read an rnat bits that are stored on the
  175. * kernel backing store. Since, in general, the alignment of the user
  176. * and kernel are different, this is not completely trivial. In
  177. * essence, we need to construct the user RNAT based on up to two
  178. * kernel RNAT values and/or the RNAT value saved in the child's
  179. * pt_regs.
  180. *
  181. * user rbs
  182. *
  183. * +--------+ <-- lowest address
  184. * | slot62 |
  185. * +--------+
  186. * | rnat | 0x....1f8
  187. * +--------+
  188. * | slot00 | \
  189. * +--------+ |
  190. * | slot01 | > child_regs->ar_rnat
  191. * +--------+ |
  192. * | slot02 | / kernel rbs
  193. * +--------+ +--------+
  194. * <- child_regs->ar_bspstore | slot61 | <-- krbs
  195. * +- - - - + +--------+
  196. * | slot62 |
  197. * +- - - - + +--------+
  198. * | rnat |
  199. * +- - - - + +--------+
  200. * vrnat | slot00 |
  201. * +- - - - + +--------+
  202. * = =
  203. * +--------+
  204. * | slot00 | \
  205. * +--------+ |
  206. * | slot01 | > child_stack->ar_rnat
  207. * +--------+ |
  208. * | slot02 | /
  209. * +--------+
  210. * <--- child_stack->ar_bspstore
  211. *
  212. * The way to think of this code is as follows: bit 0 in the user rnat
  213. * corresponds to some bit N (0 <= N <= 62) in one of the kernel rnat
  214. * value. The kernel rnat value holding this bit is stored in
  215. * variable rnat0. rnat1 is loaded with the kernel rnat value that
  216. * form the upper bits of the user rnat value.
  217. *
  218. * Boundary cases:
  219. *
  220. * o when reading the rnat "below" the first rnat slot on the kernel
  221. * backing store, rnat0/rnat1 are set to 0 and the low order bits are
  222. * merged in from pt->ar_rnat.
  223. *
  224. * o when reading the rnat "above" the last rnat slot on the kernel
  225. * backing store, rnat0/rnat1 gets its value from sw->ar_rnat.
  226. */
  227. static unsigned long
  228. get_rnat (struct task_struct *task, struct switch_stack *sw,
  229. unsigned long *krbs, unsigned long *urnat_addr,
  230. unsigned long *urbs_end)
  231. {
  232. unsigned long rnat0 = 0, rnat1 = 0, urnat = 0, *slot0_kaddr;
  233. unsigned long umask = 0, mask, m;
  234. unsigned long *kbsp, *ubspstore, *rnat0_kaddr, *rnat1_kaddr, shift;
  235. long num_regs, nbits;
  236. struct pt_regs *pt;
  237. pt = task_pt_regs(task);
  238. kbsp = (unsigned long *) sw->ar_bspstore;
  239. ubspstore = (unsigned long *) pt->ar_bspstore;
  240. if (urbs_end < urnat_addr)
  241. nbits = ia64_rse_num_regs(urnat_addr - 63, urbs_end);
  242. else
  243. nbits = 63;
  244. mask = MASK(nbits);
  245. /*
  246. * First, figure out which bit number slot 0 in user-land maps
  247. * to in the kernel rnat. Do this by figuring out how many
  248. * register slots we're beyond the user's backingstore and
  249. * then computing the equivalent address in kernel space.
  250. */
  251. num_regs = ia64_rse_num_regs(ubspstore, urnat_addr + 1);
  252. slot0_kaddr = ia64_rse_skip_regs(krbs, num_regs);
  253. shift = ia64_rse_slot_num(slot0_kaddr);
  254. rnat1_kaddr = ia64_rse_rnat_addr(slot0_kaddr);
  255. rnat0_kaddr = rnat1_kaddr - 64;
  256. if (ubspstore + 63 > urnat_addr) {
  257. /* some bits need to be merged in from pt->ar_rnat */
  258. umask = MASK(ia64_rse_slot_num(ubspstore)) & mask;
  259. urnat = (pt->ar_rnat & umask);
  260. mask &= ~umask;
  261. if (!mask)
  262. return urnat;
  263. }
  264. m = mask << shift;
  265. if (rnat0_kaddr >= kbsp)
  266. rnat0 = sw->ar_rnat;
  267. else if (rnat0_kaddr > krbs)
  268. rnat0 = *rnat0_kaddr;
  269. urnat |= (rnat0 & m) >> shift;
  270. m = mask >> (63 - shift);
  271. if (rnat1_kaddr >= kbsp)
  272. rnat1 = sw->ar_rnat;
  273. else if (rnat1_kaddr > krbs)
  274. rnat1 = *rnat1_kaddr;
  275. urnat |= (rnat1 & m) << (63 - shift);
  276. return urnat;
  277. }
  278. /*
  279. * The reverse of get_rnat.
  280. */
  281. static void
  282. put_rnat (struct task_struct *task, struct switch_stack *sw,
  283. unsigned long *krbs, unsigned long *urnat_addr, unsigned long urnat,
  284. unsigned long *urbs_end)
  285. {
  286. unsigned long rnat0 = 0, rnat1 = 0, *slot0_kaddr, umask = 0, mask, m;
  287. unsigned long *kbsp, *ubspstore, *rnat0_kaddr, *rnat1_kaddr, shift;
  288. long num_regs, nbits;
  289. struct pt_regs *pt;
  290. unsigned long cfm, *urbs_kargs;
  291. pt = task_pt_regs(task);
  292. kbsp = (unsigned long *) sw->ar_bspstore;
  293. ubspstore = (unsigned long *) pt->ar_bspstore;
  294. urbs_kargs = urbs_end;
  295. if (in_syscall(pt)) {
  296. /*
  297. * If entered via syscall, don't allow user to set rnat bits
  298. * for syscall args.
  299. */
  300. cfm = pt->cr_ifs;
  301. urbs_kargs = ia64_rse_skip_regs(urbs_end, -(cfm & 0x7f));
  302. }
  303. if (urbs_kargs >= urnat_addr)
  304. nbits = 63;
  305. else {
  306. if ((urnat_addr - 63) >= urbs_kargs)
  307. return;
  308. nbits = ia64_rse_num_regs(urnat_addr - 63, urbs_kargs);
  309. }
  310. mask = MASK(nbits);
  311. /*
  312. * First, figure out which bit number slot 0 in user-land maps
  313. * to in the kernel rnat. Do this by figuring out how many
  314. * register slots we're beyond the user's backingstore and
  315. * then computing the equivalent address in kernel space.
  316. */
  317. num_regs = ia64_rse_num_regs(ubspstore, urnat_addr + 1);
  318. slot0_kaddr = ia64_rse_skip_regs(krbs, num_regs);
  319. shift = ia64_rse_slot_num(slot0_kaddr);
  320. rnat1_kaddr = ia64_rse_rnat_addr(slot0_kaddr);
  321. rnat0_kaddr = rnat1_kaddr - 64;
  322. if (ubspstore + 63 > urnat_addr) {
  323. /* some bits need to be place in pt->ar_rnat: */
  324. umask = MASK(ia64_rse_slot_num(ubspstore)) & mask;
  325. pt->ar_rnat = (pt->ar_rnat & ~umask) | (urnat & umask);
  326. mask &= ~umask;
  327. if (!mask)
  328. return;
  329. }
  330. /*
  331. * Note: Section 11.1 of the EAS guarantees that bit 63 of an
  332. * rnat slot is ignored. so we don't have to clear it here.
  333. */
  334. rnat0 = (urnat << shift);
  335. m = mask << shift;
  336. if (rnat0_kaddr >= kbsp)
  337. sw->ar_rnat = (sw->ar_rnat & ~m) | (rnat0 & m);
  338. else if (rnat0_kaddr > krbs)
  339. *rnat0_kaddr = ((*rnat0_kaddr & ~m) | (rnat0 & m));
  340. rnat1 = (urnat >> (63 - shift));
  341. m = mask >> (63 - shift);
  342. if (rnat1_kaddr >= kbsp)
  343. sw->ar_rnat = (sw->ar_rnat & ~m) | (rnat1 & m);
  344. else if (rnat1_kaddr > krbs)
  345. *rnat1_kaddr = ((*rnat1_kaddr & ~m) | (rnat1 & m));
  346. }
  347. static inline int
  348. on_kernel_rbs (unsigned long addr, unsigned long bspstore,
  349. unsigned long urbs_end)
  350. {
  351. unsigned long *rnat_addr = ia64_rse_rnat_addr((unsigned long *)
  352. urbs_end);
  353. return (addr >= bspstore && addr <= (unsigned long) rnat_addr);
  354. }
  355. /*
  356. * Read a word from the user-level backing store of task CHILD. ADDR
  357. * is the user-level address to read the word from, VAL a pointer to
  358. * the return value, and USER_BSP gives the end of the user-level
  359. * backing store (i.e., it's the address that would be in ar.bsp after
  360. * the user executed a "cover" instruction).
  361. *
  362. * This routine takes care of accessing the kernel register backing
  363. * store for those registers that got spilled there. It also takes
  364. * care of calculating the appropriate RNaT collection words.
  365. */
  366. long
  367. ia64_peek (struct task_struct *child, struct switch_stack *child_stack,
  368. unsigned long user_rbs_end, unsigned long addr, long *val)
  369. {
  370. unsigned long *bspstore, *krbs, regnum, *laddr, *urbs_end, *rnat_addr;
  371. struct pt_regs *child_regs;
  372. size_t copied;
  373. long ret;
  374. urbs_end = (long *) user_rbs_end;
  375. laddr = (unsigned long *) addr;
  376. child_regs = task_pt_regs(child);
  377. bspstore = (unsigned long *) child_regs->ar_bspstore;
  378. krbs = (unsigned long *) child + IA64_RBS_OFFSET/8;
  379. if (on_kernel_rbs(addr, (unsigned long) bspstore,
  380. (unsigned long) urbs_end))
  381. {
  382. /*
  383. * Attempt to read the RBS in an area that's actually
  384. * on the kernel RBS => read the corresponding bits in
  385. * the kernel RBS.
  386. */
  387. rnat_addr = ia64_rse_rnat_addr(laddr);
  388. ret = get_rnat(child, child_stack, krbs, rnat_addr, urbs_end);
  389. if (laddr == rnat_addr) {
  390. /* return NaT collection word itself */
  391. *val = ret;
  392. return 0;
  393. }
  394. if (((1UL << ia64_rse_slot_num(laddr)) & ret) != 0) {
  395. /*
  396. * It is implementation dependent whether the
  397. * data portion of a NaT value gets saved on a
  398. * st8.spill or RSE spill (e.g., see EAS 2.6,
  399. * 4.4.4.6 Register Spill and Fill). To get
  400. * consistent behavior across all possible
  401. * IA-64 implementations, we return zero in
  402. * this case.
  403. */
  404. *val = 0;
  405. return 0;
  406. }
  407. if (laddr < urbs_end) {
  408. /*
  409. * The desired word is on the kernel RBS and
  410. * is not a NaT.
  411. */
  412. regnum = ia64_rse_num_regs(bspstore, laddr);
  413. *val = *ia64_rse_skip_regs(krbs, regnum);
  414. return 0;
  415. }
  416. }
  417. copied = access_process_vm(child, addr, &ret, sizeof(ret), 0);
  418. if (copied != sizeof(ret))
  419. return -EIO;
  420. *val = ret;
  421. return 0;
  422. }
  423. long
  424. ia64_poke (struct task_struct *child, struct switch_stack *child_stack,
  425. unsigned long user_rbs_end, unsigned long addr, long val)
  426. {
  427. unsigned long *bspstore, *krbs, regnum, *laddr;
  428. unsigned long *urbs_end = (long *) user_rbs_end;
  429. struct pt_regs *child_regs;
  430. laddr = (unsigned long *) addr;
  431. child_regs = task_pt_regs(child);
  432. bspstore = (unsigned long *) child_regs->ar_bspstore;
  433. krbs = (unsigned long *) child + IA64_RBS_OFFSET/8;
  434. if (on_kernel_rbs(addr, (unsigned long) bspstore,
  435. (unsigned long) urbs_end))
  436. {
  437. /*
  438. * Attempt to write the RBS in an area that's actually
  439. * on the kernel RBS => write the corresponding bits
  440. * in the kernel RBS.
  441. */
  442. if (ia64_rse_is_rnat_slot(laddr))
  443. put_rnat(child, child_stack, krbs, laddr, val,
  444. urbs_end);
  445. else {
  446. if (laddr < urbs_end) {
  447. regnum = ia64_rse_num_regs(bspstore, laddr);
  448. *ia64_rse_skip_regs(krbs, regnum) = val;
  449. }
  450. }
  451. } else if (access_process_vm(child, addr, &val, sizeof(val), 1)
  452. != sizeof(val))
  453. return -EIO;
  454. return 0;
  455. }
  456. /*
  457. * Calculate the address of the end of the user-level register backing
  458. * store. This is the address that would have been stored in ar.bsp
  459. * if the user had executed a "cover" instruction right before
  460. * entering the kernel. If CFMP is not NULL, it is used to return the
  461. * "current frame mask" that was active at the time the kernel was
  462. * entered.
  463. */
  464. unsigned long
  465. ia64_get_user_rbs_end (struct task_struct *child, struct pt_regs *pt,
  466. unsigned long *cfmp)
  467. {
  468. unsigned long *krbs, *bspstore, cfm = pt->cr_ifs;
  469. long ndirty;
  470. krbs = (unsigned long *) child + IA64_RBS_OFFSET/8;
  471. bspstore = (unsigned long *) pt->ar_bspstore;
  472. ndirty = ia64_rse_num_regs(krbs, krbs + (pt->loadrs >> 19));
  473. if (in_syscall(pt))
  474. ndirty += (cfm & 0x7f);
  475. else
  476. cfm &= ~(1UL << 63); /* clear valid bit */
  477. if (cfmp)
  478. *cfmp = cfm;
  479. return (unsigned long) ia64_rse_skip_regs(bspstore, ndirty);
  480. }
  481. /*
  482. * Synchronize (i.e, write) the RSE backing store living in kernel
  483. * space to the VM of the CHILD task. SW and PT are the pointers to
  484. * the switch_stack and pt_regs structures, respectively.
  485. * USER_RBS_END is the user-level address at which the backing store
  486. * ends.
  487. */
  488. long
  489. ia64_sync_user_rbs (struct task_struct *child, struct switch_stack *sw,
  490. unsigned long user_rbs_start, unsigned long user_rbs_end)
  491. {
  492. unsigned long addr, val;
  493. long ret;
  494. /* now copy word for word from kernel rbs to user rbs: */
  495. for (addr = user_rbs_start; addr < user_rbs_end; addr += 8) {
  496. ret = ia64_peek(child, sw, user_rbs_end, addr, &val);
  497. if (ret < 0)
  498. return ret;
  499. if (access_process_vm(child, addr, &val, sizeof(val), 1)
  500. != sizeof(val))
  501. return -EIO;
  502. }
  503. return 0;
  504. }
  505. static long
  506. ia64_sync_kernel_rbs (struct task_struct *child, struct switch_stack *sw,
  507. unsigned long user_rbs_start, unsigned long user_rbs_end)
  508. {
  509. unsigned long addr, val;
  510. long ret;
  511. /* now copy word for word from user rbs to kernel rbs: */
  512. for (addr = user_rbs_start; addr < user_rbs_end; addr += 8) {
  513. if (access_process_vm(child, addr, &val, sizeof(val), 0)
  514. != sizeof(val))
  515. return -EIO;
  516. ret = ia64_poke(child, sw, user_rbs_end, addr, val);
  517. if (ret < 0)
  518. return ret;
  519. }
  520. return 0;
  521. }
  522. typedef long (*syncfunc_t)(struct task_struct *, struct switch_stack *,
  523. unsigned long, unsigned long);
  524. static void do_sync_rbs(struct unw_frame_info *info, void *arg)
  525. {
  526. struct pt_regs *pt;
  527. unsigned long urbs_end;
  528. syncfunc_t fn = arg;
  529. if (unw_unwind_to_user(info) < 0)
  530. return;
  531. pt = task_pt_regs(info->task);
  532. urbs_end = ia64_get_user_rbs_end(info->task, pt, NULL);
  533. fn(info->task, info->sw, pt->ar_bspstore, urbs_end);
  534. }
  535. /*
  536. * when a thread is stopped (ptraced), debugger might change thread's user
  537. * stack (change memory directly), and we must avoid the RSE stored in kernel
  538. * to override user stack (user space's RSE is newer than kernel's in the
  539. * case). To workaround the issue, we copy kernel RSE to user RSE before the
  540. * task is stopped, so user RSE has updated data. we then copy user RSE to
  541. * kernel after the task is resummed from traced stop and kernel will use the
  542. * newer RSE to return to user. TIF_RESTORE_RSE is the flag to indicate we need
  543. * synchronize user RSE to kernel.
  544. */
  545. void ia64_ptrace_stop(void)
  546. {
  547. if (test_and_set_tsk_thread_flag(current, TIF_RESTORE_RSE))
  548. return;
  549. set_notify_resume(current);
  550. unw_init_running(do_sync_rbs, ia64_sync_user_rbs);
  551. }
  552. /*
  553. * This is called to read back the register backing store.
  554. */
  555. void ia64_sync_krbs(void)
  556. {
  557. clear_tsk_thread_flag(current, TIF_RESTORE_RSE);
  558. unw_init_running(do_sync_rbs, ia64_sync_kernel_rbs);
  559. }
  560. /*
  561. * After PTRACE_ATTACH, a thread's register backing store area in user
  562. * space is assumed to contain correct data whenever the thread is
  563. * stopped. arch_ptrace_stop takes care of this on tracing stops.
  564. * But if the child was already stopped for job control when we attach
  565. * to it, then it might not ever get into ptrace_stop by the time we
  566. * want to examine the user memory containing the RBS.
  567. */
  568. void
  569. ptrace_attach_sync_user_rbs (struct task_struct *child)
  570. {
  571. int stopped = 0;
  572. struct unw_frame_info info;
  573. /*
  574. * If the child is in TASK_STOPPED, we need to change that to
  575. * TASK_TRACED momentarily while we operate on it. This ensures
  576. * that the child won't be woken up and return to user mode while
  577. * we are doing the sync. (It can only be woken up for SIGKILL.)
  578. */
  579. read_lock(&tasklist_lock);
  580. if (child->sighand) {
  581. spin_lock_irq(&child->sighand->siglock);
  582. if (child->state == TASK_STOPPED &&
  583. !test_and_set_tsk_thread_flag(child, TIF_RESTORE_RSE)) {
  584. set_notify_resume(child);
  585. child->state = TASK_TRACED;
  586. stopped = 1;
  587. }
  588. spin_unlock_irq(&child->sighand->siglock);
  589. }
  590. read_unlock(&tasklist_lock);
  591. if (!stopped)
  592. return;
  593. unw_init_from_blocked_task(&info, child);
  594. do_sync_rbs(&info, ia64_sync_user_rbs);
  595. /*
  596. * Now move the child back into TASK_STOPPED if it should be in a
  597. * job control stop, so that SIGCONT can be used to wake it up.
  598. */
  599. read_lock(&tasklist_lock);
  600. if (child->sighand) {
  601. spin_lock_irq(&child->sighand->siglock);
  602. if (child->state == TASK_TRACED &&
  603. (child->signal->flags & SIGNAL_STOP_STOPPED)) {
  604. child->state = TASK_STOPPED;
  605. }
  606. spin_unlock_irq(&child->sighand->siglock);
  607. }
  608. read_unlock(&tasklist_lock);
  609. }
  610. /*
  611. * Write f32-f127 back to task->thread.fph if it has been modified.
  612. */
  613. inline void
  614. ia64_flush_fph (struct task_struct *task)
  615. {
  616. struct ia64_psr *psr = ia64_psr(task_pt_regs(task));
  617. /*
  618. * Prevent migrating this task while
  619. * we're fiddling with the FPU state
  620. */
  621. preempt_disable();
  622. if (ia64_is_local_fpu_owner(task) && psr->mfh) {
  623. psr->mfh = 0;
  624. task->thread.flags |= IA64_THREAD_FPH_VALID;
  625. ia64_save_fpu(&task->thread.fph[0]);
  626. }
  627. preempt_enable();
  628. }
  629. /*
  630. * Sync the fph state of the task so that it can be manipulated
  631. * through thread.fph. If necessary, f32-f127 are written back to
  632. * thread.fph or, if the fph state hasn't been used before, thread.fph
  633. * is cleared to zeroes. Also, access to f32-f127 is disabled to
  634. * ensure that the task picks up the state from thread.fph when it
  635. * executes again.
  636. */
  637. void
  638. ia64_sync_fph (struct task_struct *task)
  639. {
  640. struct ia64_psr *psr = ia64_psr(task_pt_regs(task));
  641. ia64_flush_fph(task);
  642. if (!(task->thread.flags & IA64_THREAD_FPH_VALID)) {
  643. task->thread.flags |= IA64_THREAD_FPH_VALID;
  644. memset(&task->thread.fph, 0, sizeof(task->thread.fph));
  645. }
  646. ia64_drop_fpu(task);
  647. psr->dfh = 1;
  648. }
  649. /*
  650. * Change the machine-state of CHILD such that it will return via the normal
  651. * kernel exit-path, rather than the syscall-exit path.
  652. */
  653. static void
  654. convert_to_non_syscall (struct task_struct *child, struct pt_regs *pt,
  655. unsigned long cfm)
  656. {
  657. struct unw_frame_info info, prev_info;
  658. unsigned long ip, sp, pr;
  659. unw_init_from_blocked_task(&info, child);
  660. while (1) {
  661. prev_info = info;
  662. if (unw_unwind(&info) < 0)
  663. return;
  664. unw_get_sp(&info, &sp);
  665. if ((long)((unsigned long)child + IA64_STK_OFFSET - sp)
  666. < IA64_PT_REGS_SIZE) {
  667. dprintk("ptrace.%s: ran off the top of the kernel "
  668. "stack\n", __func__);
  669. return;
  670. }
  671. if (unw_get_pr (&prev_info, &pr) < 0) {
  672. unw_get_rp(&prev_info, &ip);
  673. dprintk("ptrace.%s: failed to read "
  674. "predicate register (ip=0x%lx)\n",
  675. __func__, ip);
  676. return;
  677. }
  678. if (unw_is_intr_frame(&info)
  679. && (pr & (1UL << PRED_USER_STACK)))
  680. break;
  681. }
  682. /*
  683. * Note: at the time of this call, the target task is blocked
  684. * in notify_resume_user() and by clearling PRED_LEAVE_SYSCALL
  685. * (aka, "pLvSys") we redirect execution from
  686. * .work_pending_syscall_end to .work_processed_kernel.
  687. */
  688. unw_get_pr(&prev_info, &pr);
  689. pr &= ~((1UL << PRED_SYSCALL) | (1UL << PRED_LEAVE_SYSCALL));
  690. pr |= (1UL << PRED_NON_SYSCALL);
  691. unw_set_pr(&prev_info, pr);
  692. pt->cr_ifs = (1UL << 63) | cfm;
  693. /*
  694. * Clear the memory that is NOT written on syscall-entry to
  695. * ensure we do not leak kernel-state to user when execution
  696. * resumes.
  697. */
  698. pt->r2 = 0;
  699. pt->r3 = 0;
  700. pt->r14 = 0;
  701. memset(&pt->r16, 0, 16*8); /* clear r16-r31 */
  702. memset(&pt->f6, 0, 6*16); /* clear f6-f11 */
  703. pt->b7 = 0;
  704. pt->ar_ccv = 0;
  705. pt->ar_csd = 0;
  706. pt->ar_ssd = 0;
  707. }
  708. static int
  709. access_nat_bits (struct task_struct *child, struct pt_regs *pt,
  710. struct unw_frame_info *info,
  711. unsigned long *data, int write_access)
  712. {
  713. unsigned long regnum, nat_bits, scratch_unat, dummy = 0;
  714. char nat = 0;
  715. if (write_access) {
  716. nat_bits = *data;
  717. scratch_unat = ia64_put_scratch_nat_bits(pt, nat_bits);
  718. if (unw_set_ar(info, UNW_AR_UNAT, scratch_unat) < 0) {
  719. dprintk("ptrace: failed to set ar.unat\n");
  720. return -1;
  721. }
  722. for (regnum = 4; regnum <= 7; ++regnum) {
  723. unw_get_gr(info, regnum, &dummy, &nat);
  724. unw_set_gr(info, regnum, dummy,
  725. (nat_bits >> regnum) & 1);
  726. }
  727. } else {
  728. if (unw_get_ar(info, UNW_AR_UNAT, &scratch_unat) < 0) {
  729. dprintk("ptrace: failed to read ar.unat\n");
  730. return -1;
  731. }
  732. nat_bits = ia64_get_scratch_nat_bits(pt, scratch_unat);
  733. for (regnum = 4; regnum <= 7; ++regnum) {
  734. unw_get_gr(info, regnum, &dummy, &nat);
  735. nat_bits |= (nat != 0) << regnum;
  736. }
  737. *data = nat_bits;
  738. }
  739. return 0;
  740. }
  741. static int
  742. access_uarea (struct task_struct *child, unsigned long addr,
  743. unsigned long *data, int write_access);
  744. static long
  745. ptrace_getregs (struct task_struct *child, struct pt_all_user_regs __user *ppr)
  746. {
  747. unsigned long psr, ec, lc, rnat, bsp, cfm, nat_bits, val;
  748. struct unw_frame_info info;
  749. struct ia64_fpreg fpval;
  750. struct switch_stack *sw;
  751. struct pt_regs *pt;
  752. long ret, retval = 0;
  753. char nat = 0;
  754. int i;
  755. if (!access_ok(VERIFY_WRITE, ppr, sizeof(struct pt_all_user_regs)))
  756. return -EIO;
  757. pt = task_pt_regs(child);
  758. sw = (struct switch_stack *) (child->thread.ksp + 16);
  759. unw_init_from_blocked_task(&info, child);
  760. if (unw_unwind_to_user(&info) < 0) {
  761. return -EIO;
  762. }
  763. if (((unsigned long) ppr & 0x7) != 0) {
  764. dprintk("ptrace:unaligned register address %p\n", ppr);
  765. return -EIO;
  766. }
  767. if (access_uarea(child, PT_CR_IPSR, &psr, 0) < 0
  768. || access_uarea(child, PT_AR_EC, &ec, 0) < 0
  769. || access_uarea(child, PT_AR_LC, &lc, 0) < 0
  770. || access_uarea(child, PT_AR_RNAT, &rnat, 0) < 0
  771. || access_uarea(child, PT_AR_BSP, &bsp, 0) < 0
  772. || access_uarea(child, PT_CFM, &cfm, 0)
  773. || access_uarea(child, PT_NAT_BITS, &nat_bits, 0))
  774. return -EIO;
  775. /* control regs */
  776. retval |= __put_user(pt->cr_iip, &ppr->cr_iip);
  777. retval |= __put_user(psr, &ppr->cr_ipsr);
  778. /* app regs */
  779. retval |= __put_user(pt->ar_pfs, &ppr->ar[PT_AUR_PFS]);
  780. retval |= __put_user(pt->ar_rsc, &ppr->ar[PT_AUR_RSC]);
  781. retval |= __put_user(pt->ar_bspstore, &ppr->ar[PT_AUR_BSPSTORE]);
  782. retval |= __put_user(pt->ar_unat, &ppr->ar[PT_AUR_UNAT]);
  783. retval |= __put_user(pt->ar_ccv, &ppr->ar[PT_AUR_CCV]);
  784. retval |= __put_user(pt->ar_fpsr, &ppr->ar[PT_AUR_FPSR]);
  785. retval |= __put_user(ec, &ppr->ar[PT_AUR_EC]);
  786. retval |= __put_user(lc, &ppr->ar[PT_AUR_LC]);
  787. retval |= __put_user(rnat, &ppr->ar[PT_AUR_RNAT]);
  788. retval |= __put_user(bsp, &ppr->ar[PT_AUR_BSP]);
  789. retval |= __put_user(cfm, &ppr->cfm);
  790. /* gr1-gr3 */
  791. retval |= __copy_to_user(&ppr->gr[1], &pt->r1, sizeof(long));
  792. retval |= __copy_to_user(&ppr->gr[2], &pt->r2, sizeof(long) *2);
  793. /* gr4-gr7 */
  794. for (i = 4; i < 8; i++) {
  795. if (unw_access_gr(&info, i, &val, &nat, 0) < 0)
  796. return -EIO;
  797. retval |= __put_user(val, &ppr->gr[i]);
  798. }
  799. /* gr8-gr11 */
  800. retval |= __copy_to_user(&ppr->gr[8], &pt->r8, sizeof(long) * 4);
  801. /* gr12-gr15 */
  802. retval |= __copy_to_user(&ppr->gr[12], &pt->r12, sizeof(long) * 2);
  803. retval |= __copy_to_user(&ppr->gr[14], &pt->r14, sizeof(long));
  804. retval |= __copy_to_user(&ppr->gr[15], &pt->r15, sizeof(long));
  805. /* gr16-gr31 */
  806. retval |= __copy_to_user(&ppr->gr[16], &pt->r16, sizeof(long) * 16);
  807. /* b0 */
  808. retval |= __put_user(pt->b0, &ppr->br[0]);
  809. /* b1-b5 */
  810. for (i = 1; i < 6; i++) {
  811. if (unw_access_br(&info, i, &val, 0) < 0)
  812. return -EIO;
  813. __put_user(val, &ppr->br[i]);
  814. }
  815. /* b6-b7 */
  816. retval |= __put_user(pt->b6, &ppr->br[6]);
  817. retval |= __put_user(pt->b7, &ppr->br[7]);
  818. /* fr2-fr5 */
  819. for (i = 2; i < 6; i++) {
  820. if (unw_get_fr(&info, i, &fpval) < 0)
  821. return -EIO;
  822. retval |= __copy_to_user(&ppr->fr[i], &fpval, sizeof (fpval));
  823. }
  824. /* fr6-fr11 */
  825. retval |= __copy_to_user(&ppr->fr[6], &pt->f6,
  826. sizeof(struct ia64_fpreg) * 6);
  827. /* fp scratch regs(12-15) */
  828. retval |= __copy_to_user(&ppr->fr[12], &sw->f12,
  829. sizeof(struct ia64_fpreg) * 4);
  830. /* fr16-fr31 */
  831. for (i = 16; i < 32; i++) {
  832. if (unw_get_fr(&info, i, &fpval) < 0)
  833. return -EIO;
  834. retval |= __copy_to_user(&ppr->fr[i], &fpval, sizeof (fpval));
  835. }
  836. /* fph */
  837. ia64_flush_fph(child);
  838. retval |= __copy_to_user(&ppr->fr[32], &child->thread.fph,
  839. sizeof(ppr->fr[32]) * 96);
  840. /* preds */
  841. retval |= __put_user(pt->pr, &ppr->pr);
  842. /* nat bits */
  843. retval |= __put_user(nat_bits, &ppr->nat);
  844. ret = retval ? -EIO : 0;
  845. return ret;
  846. }
  847. static long
  848. ptrace_setregs (struct task_struct *child, struct pt_all_user_regs __user *ppr)
  849. {
  850. unsigned long psr, rsc, ec, lc, rnat, bsp, cfm, nat_bits, val = 0;
  851. struct unw_frame_info info;
  852. struct switch_stack *sw;
  853. struct ia64_fpreg fpval;
  854. struct pt_regs *pt;
  855. long ret, retval = 0;
  856. int i;
  857. memset(&fpval, 0, sizeof(fpval));
  858. if (!access_ok(VERIFY_READ, ppr, sizeof(struct pt_all_user_regs)))
  859. return -EIO;
  860. pt = task_pt_regs(child);
  861. sw = (struct switch_stack *) (child->thread.ksp + 16);
  862. unw_init_from_blocked_task(&info, child);
  863. if (unw_unwind_to_user(&info) < 0) {
  864. return -EIO;
  865. }
  866. if (((unsigned long) ppr & 0x7) != 0) {
  867. dprintk("ptrace:unaligned register address %p\n", ppr);
  868. return -EIO;
  869. }
  870. /* control regs */
  871. retval |= __get_user(pt->cr_iip, &ppr->cr_iip);
  872. retval |= __get_user(psr, &ppr->cr_ipsr);
  873. /* app regs */
  874. retval |= __get_user(pt->ar_pfs, &ppr->ar[PT_AUR_PFS]);
  875. retval |= __get_user(rsc, &ppr->ar[PT_AUR_RSC]);
  876. retval |= __get_user(pt->ar_bspstore, &ppr->ar[PT_AUR_BSPSTORE]);
  877. retval |= __get_user(pt->ar_unat, &ppr->ar[PT_AUR_UNAT]);
  878. retval |= __get_user(pt->ar_ccv, &ppr->ar[PT_AUR_CCV]);
  879. retval |= __get_user(pt->ar_fpsr, &ppr->ar[PT_AUR_FPSR]);
  880. retval |= __get_user(ec, &ppr->ar[PT_AUR_EC]);
  881. retval |= __get_user(lc, &ppr->ar[PT_AUR_LC]);
  882. retval |= __get_user(rnat, &ppr->ar[PT_AUR_RNAT]);
  883. retval |= __get_user(bsp, &ppr->ar[PT_AUR_BSP]);
  884. retval |= __get_user(cfm, &ppr->cfm);
  885. /* gr1-gr3 */
  886. retval |= __copy_from_user(&pt->r1, &ppr->gr[1], sizeof(long));
  887. retval |= __copy_from_user(&pt->r2, &ppr->gr[2], sizeof(long) * 2);
  888. /* gr4-gr7 */
  889. for (i = 4; i < 8; i++) {
  890. retval |= __get_user(val, &ppr->gr[i]);
  891. /* NaT bit will be set via PT_NAT_BITS: */
  892. if (unw_set_gr(&info, i, val, 0) < 0)
  893. return -EIO;
  894. }
  895. /* gr8-gr11 */
  896. retval |= __copy_from_user(&pt->r8, &ppr->gr[8], sizeof(long) * 4);
  897. /* gr12-gr15 */
  898. retval |= __copy_from_user(&pt->r12, &ppr->gr[12], sizeof(long) * 2);
  899. retval |= __copy_from_user(&pt->r14, &ppr->gr[14], sizeof(long));
  900. retval |= __copy_from_user(&pt->r15, &ppr->gr[15], sizeof(long));
  901. /* gr16-gr31 */
  902. retval |= __copy_from_user(&pt->r16, &ppr->gr[16], sizeof(long) * 16);
  903. /* b0 */
  904. retval |= __get_user(pt->b0, &ppr->br[0]);
  905. /* b1-b5 */
  906. for (i = 1; i < 6; i++) {
  907. retval |= __get_user(val, &ppr->br[i]);
  908. unw_set_br(&info, i, val);
  909. }
  910. /* b6-b7 */
  911. retval |= __get_user(pt->b6, &ppr->br[6]);
  912. retval |= __get_user(pt->b7, &ppr->br[7]);
  913. /* fr2-fr5 */
  914. for (i = 2; i < 6; i++) {
  915. retval |= __copy_from_user(&fpval, &ppr->fr[i], sizeof(fpval));
  916. if (unw_set_fr(&info, i, fpval) < 0)
  917. return -EIO;
  918. }
  919. /* fr6-fr11 */
  920. retval |= __copy_from_user(&pt->f6, &ppr->fr[6],
  921. sizeof(ppr->fr[6]) * 6);
  922. /* fp scratch regs(12-15) */
  923. retval |= __copy_from_user(&sw->f12, &ppr->fr[12],
  924. sizeof(ppr->fr[12]) * 4);
  925. /* fr16-fr31 */
  926. for (i = 16; i < 32; i++) {
  927. retval |= __copy_from_user(&fpval, &ppr->fr[i],
  928. sizeof(fpval));
  929. if (unw_set_fr(&info, i, fpval) < 0)
  930. return -EIO;
  931. }
  932. /* fph */
  933. ia64_sync_fph(child);
  934. retval |= __copy_from_user(&child->thread.fph, &ppr->fr[32],
  935. sizeof(ppr->fr[32]) * 96);
  936. /* preds */
  937. retval |= __get_user(pt->pr, &ppr->pr);
  938. /* nat bits */
  939. retval |= __get_user(nat_bits, &ppr->nat);
  940. retval |= access_uarea(child, PT_CR_IPSR, &psr, 1);
  941. retval |= access_uarea(child, PT_AR_RSC, &rsc, 1);
  942. retval |= access_uarea(child, PT_AR_EC, &ec, 1);
  943. retval |= access_uarea(child, PT_AR_LC, &lc, 1);
  944. retval |= access_uarea(child, PT_AR_RNAT, &rnat, 1);
  945. retval |= access_uarea(child, PT_AR_BSP, &bsp, 1);
  946. retval |= access_uarea(child, PT_CFM, &cfm, 1);
  947. retval |= access_uarea(child, PT_NAT_BITS, &nat_bits, 1);
  948. ret = retval ? -EIO : 0;
  949. return ret;
  950. }
  951. void
  952. user_enable_single_step (struct task_struct *child)
  953. {
  954. struct ia64_psr *child_psr = ia64_psr(task_pt_regs(child));
  955. set_tsk_thread_flag(child, TIF_SINGLESTEP);
  956. child_psr->ss = 1;
  957. }
  958. void
  959. user_enable_block_step (struct task_struct *child)
  960. {
  961. struct ia64_psr *child_psr = ia64_psr(task_pt_regs(child));
  962. set_tsk_thread_flag(child, TIF_SINGLESTEP);
  963. child_psr->tb = 1;
  964. }
  965. void
  966. user_disable_single_step (struct task_struct *child)
  967. {
  968. struct ia64_psr *child_psr = ia64_psr(task_pt_regs(child));
  969. /* make sure the single step/taken-branch trap bits are not set: */
  970. clear_tsk_thread_flag(child, TIF_SINGLESTEP);
  971. child_psr->ss = 0;
  972. child_psr->tb = 0;
  973. }
  974. /*
  975. * Called by kernel/ptrace.c when detaching..
  976. *
  977. * Make sure the single step bit is not set.
  978. */
  979. void
  980. ptrace_disable (struct task_struct *child)
  981. {
  982. user_disable_single_step(child);
  983. }
  984. long
  985. arch_ptrace (struct task_struct *child, long request,
  986. unsigned long addr, unsigned long data)
  987. {
  988. switch (request) {
  989. case PTRACE_PEEKTEXT:
  990. case PTRACE_PEEKDATA:
  991. /* read word at location addr */
  992. if (access_process_vm(child, addr, &data, sizeof(data), 0)
  993. != sizeof(data))
  994. return -EIO;
  995. /* ensure return value is not mistaken for error code */
  996. force_successful_syscall_return();
  997. return data;
  998. /* PTRACE_POKETEXT and PTRACE_POKEDATA is handled
  999. * by the generic ptrace_request().
  1000. */
  1001. case PTRACE_PEEKUSR:
  1002. /* read the word at addr in the USER area */
  1003. if (access_uarea(child, addr, &data, 0) < 0)
  1004. return -EIO;
  1005. /* ensure return value is not mistaken for error code */
  1006. force_successful_syscall_return();
  1007. return data;
  1008. case PTRACE_POKEUSR:
  1009. /* write the word at addr in the USER area */
  1010. if (access_uarea(child, addr, &data, 1) < 0)
  1011. return -EIO;
  1012. return 0;
  1013. case PTRACE_OLD_GETSIGINFO:
  1014. /* for backwards-compatibility */
  1015. return ptrace_request(child, PTRACE_GETSIGINFO, addr, data);
  1016. case PTRACE_OLD_SETSIGINFO:
  1017. /* for backwards-compatibility */
  1018. return ptrace_request(child, PTRACE_SETSIGINFO, addr, data);
  1019. case PTRACE_GETREGS:
  1020. return ptrace_getregs(child,
  1021. (struct pt_all_user_regs __user *) data);
  1022. case PTRACE_SETREGS:
  1023. return ptrace_setregs(child,
  1024. (struct pt_all_user_regs __user *) data);
  1025. default:
  1026. return ptrace_request(child, request, addr, data);
  1027. }
  1028. }
  1029. /* "asmlinkage" so the input arguments are preserved... */
  1030. asmlinkage long
  1031. syscall_trace_enter (long arg0, long arg1, long arg2, long arg3,
  1032. long arg4, long arg5, long arg6, long arg7,
  1033. struct pt_regs regs)
  1034. {
  1035. if (test_thread_flag(TIF_SYSCALL_TRACE))
  1036. if (tracehook_report_syscall_entry(&regs))
  1037. return -ENOSYS;
  1038. /* copy user rbs to kernel rbs */
  1039. if (test_thread_flag(TIF_RESTORE_RSE))
  1040. ia64_sync_krbs();
  1041. audit_syscall_entry(regs.r15, arg0, arg1, arg2, arg3);
  1042. return 0;
  1043. }
  1044. /* "asmlinkage" so the input arguments are preserved... */
  1045. asmlinkage void
  1046. syscall_trace_leave (long arg0, long arg1, long arg2, long arg3,
  1047. long arg4, long arg5, long arg6, long arg7,
  1048. struct pt_regs regs)
  1049. {
  1050. int step;
  1051. audit_syscall_exit(&regs);
  1052. step = test_thread_flag(TIF_SINGLESTEP);
  1053. if (step || test_thread_flag(TIF_SYSCALL_TRACE))
  1054. tracehook_report_syscall_exit(&regs, step);
  1055. /* copy user rbs to kernel rbs */
  1056. if (test_thread_flag(TIF_RESTORE_RSE))
  1057. ia64_sync_krbs();
  1058. }
  1059. /* Utrace implementation starts here */
  1060. struct regset_get {
  1061. void *kbuf;
  1062. void __user *ubuf;
  1063. };
  1064. struct regset_set {
  1065. const void *kbuf;
  1066. const void __user *ubuf;
  1067. };
  1068. struct regset_getset {
  1069. struct task_struct *target;
  1070. const struct user_regset *regset;
  1071. union {
  1072. struct regset_get get;
  1073. struct regset_set set;
  1074. } u;
  1075. unsigned int pos;
  1076. unsigned int count;
  1077. int ret;
  1078. };
  1079. static int
  1080. access_elf_gpreg(struct task_struct *target, struct unw_frame_info *info,
  1081. unsigned long addr, unsigned long *data, int write_access)
  1082. {
  1083. struct pt_regs *pt;
  1084. unsigned long *ptr = NULL;
  1085. int ret;
  1086. char nat = 0;
  1087. pt = task_pt_regs(target);
  1088. switch (addr) {
  1089. case ELF_GR_OFFSET(1):
  1090. ptr = &pt->r1;
  1091. break;
  1092. case ELF_GR_OFFSET(2):
  1093. case ELF_GR_OFFSET(3):
  1094. ptr = (void *)&pt->r2 + (addr - ELF_GR_OFFSET(2));
  1095. break;
  1096. case ELF_GR_OFFSET(4) ... ELF_GR_OFFSET(7):
  1097. if (write_access) {
  1098. /* read NaT bit first: */
  1099. unsigned long dummy;
  1100. ret = unw_get_gr(info, addr/8, &dummy, &nat);
  1101. if (ret < 0)
  1102. return ret;
  1103. }
  1104. return unw_access_gr(info, addr/8, data, &nat, write_access);
  1105. case ELF_GR_OFFSET(8) ... ELF_GR_OFFSET(11):
  1106. ptr = (void *)&pt->r8 + addr - ELF_GR_OFFSET(8);
  1107. break;
  1108. case ELF_GR_OFFSET(12):
  1109. case ELF_GR_OFFSET(13):
  1110. ptr = (void *)&pt->r12 + addr - ELF_GR_OFFSET(12);
  1111. break;
  1112. case ELF_GR_OFFSET(14):
  1113. ptr = &pt->r14;
  1114. break;
  1115. case ELF_GR_OFFSET(15):
  1116. ptr = &pt->r15;
  1117. }
  1118. if (write_access)
  1119. *ptr = *data;
  1120. else
  1121. *data = *ptr;
  1122. return 0;
  1123. }
  1124. static int
  1125. access_elf_breg(struct task_struct *target, struct unw_frame_info *info,
  1126. unsigned long addr, unsigned long *data, int write_access)
  1127. {
  1128. struct pt_regs *pt;
  1129. unsigned long *ptr = NULL;
  1130. pt = task_pt_regs(target);
  1131. switch (addr) {
  1132. case ELF_BR_OFFSET(0):
  1133. ptr = &pt->b0;
  1134. break;
  1135. case ELF_BR_OFFSET(1) ... ELF_BR_OFFSET(5):
  1136. return unw_access_br(info, (addr - ELF_BR_OFFSET(0))/8,
  1137. data, write_access);
  1138. case ELF_BR_OFFSET(6):
  1139. ptr = &pt->b6;
  1140. break;
  1141. case ELF_BR_OFFSET(7):
  1142. ptr = &pt->b7;
  1143. }
  1144. if (write_access)
  1145. *ptr = *data;
  1146. else
  1147. *data = *ptr;
  1148. return 0;
  1149. }
  1150. static int
  1151. access_elf_areg(struct task_struct *target, struct unw_frame_info *info,
  1152. unsigned long addr, unsigned long *data, int write_access)
  1153. {
  1154. struct pt_regs *pt;
  1155. unsigned long cfm, urbs_end;
  1156. unsigned long *ptr = NULL;
  1157. pt = task_pt_regs(target);
  1158. if (addr >= ELF_AR_RSC_OFFSET && addr <= ELF_AR_SSD_OFFSET) {
  1159. switch (addr) {
  1160. case ELF_AR_RSC_OFFSET:
  1161. /* force PL3 */
  1162. if (write_access)
  1163. pt->ar_rsc = *data | (3 << 2);
  1164. else
  1165. *data = pt->ar_rsc;
  1166. return 0;
  1167. case ELF_AR_BSP_OFFSET:
  1168. /*
  1169. * By convention, we use PT_AR_BSP to refer to
  1170. * the end of the user-level backing store.
  1171. * Use ia64_rse_skip_regs(PT_AR_BSP, -CFM.sof)
  1172. * to get the real value of ar.bsp at the time
  1173. * the kernel was entered.
  1174. *
  1175. * Furthermore, when changing the contents of
  1176. * PT_AR_BSP (or PT_CFM) while the task is
  1177. * blocked in a system call, convert the state
  1178. * so that the non-system-call exit
  1179. * path is used. This ensures that the proper
  1180. * state will be picked up when resuming
  1181. * execution. However, it *also* means that
  1182. * once we write PT_AR_BSP/PT_CFM, it won't be
  1183. * possible to modify the syscall arguments of
  1184. * the pending system call any longer. This
  1185. * shouldn't be an issue because modifying
  1186. * PT_AR_BSP/PT_CFM generally implies that
  1187. * we're either abandoning the pending system
  1188. * call or that we defer it's re-execution
  1189. * (e.g., due to GDB doing an inferior
  1190. * function call).
  1191. */
  1192. urbs_end = ia64_get_user_rbs_end(target, pt, &cfm);
  1193. if (write_access) {
  1194. if (*data != urbs_end) {
  1195. if (in_syscall(pt))
  1196. convert_to_non_syscall(target,
  1197. pt,
  1198. cfm);
  1199. /*
  1200. * Simulate user-level write
  1201. * of ar.bsp:
  1202. */
  1203. pt->loadrs = 0;
  1204. pt->ar_bspstore = *data;
  1205. }
  1206. } else
  1207. *data = urbs_end;
  1208. return 0;
  1209. case ELF_AR_BSPSTORE_OFFSET:
  1210. ptr = &pt->ar_bspstore;
  1211. break;
  1212. case ELF_AR_RNAT_OFFSET:
  1213. ptr = &pt->ar_rnat;
  1214. break;
  1215. case ELF_AR_CCV_OFFSET:
  1216. ptr = &pt->ar_ccv;
  1217. break;
  1218. case ELF_AR_UNAT_OFFSET:
  1219. ptr = &pt->ar_unat;
  1220. break;
  1221. case ELF_AR_FPSR_OFFSET:
  1222. ptr = &pt->ar_fpsr;
  1223. break;
  1224. case ELF_AR_PFS_OFFSET:
  1225. ptr = &pt->ar_pfs;
  1226. break;
  1227. case ELF_AR_LC_OFFSET:
  1228. return unw_access_ar(info, UNW_AR_LC, data,
  1229. write_access);
  1230. case ELF_AR_EC_OFFSET:
  1231. return unw_access_ar(info, UNW_AR_EC, data,
  1232. write_access);
  1233. case ELF_AR_CSD_OFFSET:
  1234. ptr = &pt->ar_csd;
  1235. break;
  1236. case ELF_AR_SSD_OFFSET:
  1237. ptr = &pt->ar_ssd;
  1238. }
  1239. } else if (addr >= ELF_CR_IIP_OFFSET && addr <= ELF_CR_IPSR_OFFSET) {
  1240. switch (addr) {
  1241. case ELF_CR_IIP_OFFSET:
  1242. ptr = &pt->cr_iip;
  1243. break;
  1244. case ELF_CFM_OFFSET:
  1245. urbs_end = ia64_get_user_rbs_end(target, pt, &cfm);
  1246. if (write_access) {
  1247. if (((cfm ^ *data) & PFM_MASK) != 0) {
  1248. if (in_syscall(pt))
  1249. convert_to_non_syscall(target,
  1250. pt,
  1251. cfm);
  1252. pt->cr_ifs = ((pt->cr_ifs & ~PFM_MASK)
  1253. | (*data & PFM_MASK));
  1254. }
  1255. } else
  1256. *data = cfm;
  1257. return 0;
  1258. case ELF_CR_IPSR_OFFSET:
  1259. if (write_access) {
  1260. unsigned long tmp = *data;
  1261. /* psr.ri==3 is a reserved value: SDM 2:25 */
  1262. if ((tmp & IA64_PSR_RI) == IA64_PSR_RI)
  1263. tmp &= ~IA64_PSR_RI;
  1264. pt->cr_ipsr = ((tmp & IPSR_MASK)
  1265. | (pt->cr_ipsr & ~IPSR_MASK));
  1266. } else
  1267. *data = (pt->cr_ipsr & IPSR_MASK);
  1268. return 0;
  1269. }
  1270. } else if (addr == ELF_NAT_OFFSET)
  1271. return access_nat_bits(target, pt, info,
  1272. data, write_access);
  1273. else if (addr == ELF_PR_OFFSET)
  1274. ptr = &pt->pr;
  1275. else
  1276. return -1;
  1277. if (write_access)
  1278. *ptr = *data;
  1279. else
  1280. *data = *ptr;
  1281. return 0;
  1282. }
  1283. static int
  1284. access_elf_reg(struct task_struct *target, struct unw_frame_info *info,
  1285. unsigned long addr, unsigned long *data, int write_access)
  1286. {
  1287. if (addr >= ELF_GR_OFFSET(1) && addr <= ELF_GR_OFFSET(15))
  1288. return access_elf_gpreg(target, info, addr, data, write_access);
  1289. else if (addr >= ELF_BR_OFFSET(0) && addr <= ELF_BR_OFFSET(7))
  1290. return access_elf_breg(target, info, addr, data, write_access);
  1291. else
  1292. return access_elf_areg(target, info, addr, data, write_access);
  1293. }
  1294. void do_gpregs_get(struct unw_frame_info *info, void *arg)
  1295. {
  1296. struct pt_regs *pt;
  1297. struct regset_getset *dst = arg;
  1298. elf_greg_t tmp[16];
  1299. unsigned int i, index, min_copy;
  1300. if (unw_unwind_to_user(info) < 0)
  1301. return;
  1302. /*
  1303. * coredump format:
  1304. * r0-r31
  1305. * NaT bits (for r0-r31; bit N == 1 iff rN is a NaT)
  1306. * predicate registers (p0-p63)
  1307. * b0-b7
  1308. * ip cfm user-mask
  1309. * ar.rsc ar.bsp ar.bspstore ar.rnat
  1310. * ar.ccv ar.unat ar.fpsr ar.pfs ar.lc ar.ec
  1311. */
  1312. /* Skip r0 */
  1313. if (dst->count > 0 && dst->pos < ELF_GR_OFFSET(1)) {
  1314. dst->ret = user_regset_copyout_zero(&dst->pos, &dst->count,
  1315. &dst->u.get.kbuf,
  1316. &dst->u.get.ubuf,
  1317. 0, ELF_GR_OFFSET(1));
  1318. if (dst->ret || dst->count == 0)
  1319. return;
  1320. }
  1321. /* gr1 - gr15 */
  1322. if (dst->count > 0 && dst->pos < ELF_GR_OFFSET(16)) {
  1323. index = (dst->pos - ELF_GR_OFFSET(1)) / sizeof(elf_greg_t);
  1324. min_copy = ELF_GR_OFFSET(16) > (dst->pos + dst->count) ?
  1325. (dst->pos + dst->count) : ELF_GR_OFFSET(16);
  1326. for (i = dst->pos; i < min_copy; i += sizeof(elf_greg_t),
  1327. index++)
  1328. if (access_elf_reg(dst->target, info, i,
  1329. &tmp[index], 0) < 0) {
  1330. dst->ret = -EIO;
  1331. return;
  1332. }
  1333. dst->ret = user_regset_copyout(&dst->pos, &dst->count,
  1334. &dst->u.get.kbuf, &dst->u.get.ubuf, tmp,
  1335. ELF_GR_OFFSET(1), ELF_GR_OFFSET(16));
  1336. if (dst->ret || dst->count == 0)
  1337. return;
  1338. }
  1339. /* r16-r31 */
  1340. if (dst->count > 0 && dst->pos < ELF_NAT_OFFSET) {
  1341. pt = task_pt_regs(dst->target);
  1342. dst->ret = user_regset_copyout(&dst->pos, &dst->count,
  1343. &dst->u.get.kbuf, &dst->u.get.ubuf, &pt->r16,
  1344. ELF_GR_OFFSET(16), ELF_NAT_OFFSET);
  1345. if (dst->ret || dst->count == 0)
  1346. return;
  1347. }
  1348. /* nat, pr, b0 - b7 */
  1349. if (dst->count > 0 && dst->pos < ELF_CR_IIP_OFFSET) {
  1350. index = (dst->pos - ELF_NAT_OFFSET) / sizeof(elf_greg_t);
  1351. min_copy = ELF_CR_IIP_OFFSET > (dst->pos + dst->count) ?
  1352. (dst->pos + dst->count) : ELF_CR_IIP_OFFSET;
  1353. for (i = dst->pos; i < min_copy; i += sizeof(elf_greg_t),
  1354. index++)
  1355. if (access_elf_reg(dst->target, info, i,
  1356. &tmp[index], 0) < 0) {
  1357. dst->ret = -EIO;
  1358. return;
  1359. }
  1360. dst->ret = user_regset_copyout(&dst->pos, &dst->count,
  1361. &dst->u.get.kbuf, &dst->u.get.ubuf, tmp,
  1362. ELF_NAT_OFFSET, ELF_CR_IIP_OFFSET);
  1363. if (dst->ret || dst->count == 0)
  1364. return;
  1365. }
  1366. /* ip cfm psr ar.rsc ar.bsp ar.bspstore ar.rnat
  1367. * ar.ccv ar.unat ar.fpsr ar.pfs ar.lc ar.ec ar.csd ar.ssd
  1368. */
  1369. if (dst->count > 0 && dst->pos < (ELF_AR_END_OFFSET)) {
  1370. index = (dst->pos - ELF_CR_IIP_OFFSET) / sizeof(elf_greg_t);
  1371. min_copy = ELF_AR_END_OFFSET > (dst->pos + dst->count) ?
  1372. (dst->pos + dst->count) : ELF_AR_END_OFFSET;
  1373. for (i = dst->pos; i < min_copy; i += sizeof(elf_greg_t),
  1374. index++)
  1375. if (access_elf_reg(dst->target, info, i,
  1376. &tmp[index], 0) < 0) {
  1377. dst->ret = -EIO;
  1378. return;
  1379. }
  1380. dst->ret = user_regset_copyout(&dst->pos, &dst->count,
  1381. &dst->u.get.kbuf, &dst->u.get.ubuf, tmp,
  1382. ELF_CR_IIP_OFFSET, ELF_AR_END_OFFSET);
  1383. }
  1384. }
  1385. void do_gpregs_set(struct unw_frame_info *info, void *arg)
  1386. {
  1387. struct pt_regs *pt;
  1388. struct regset_getset *dst = arg;
  1389. elf_greg_t tmp[16];
  1390. unsigned int i, index;
  1391. if (unw_unwind_to_user(info) < 0)
  1392. return;
  1393. /* Skip r0 */
  1394. if (dst->count > 0 && dst->pos < ELF_GR_OFFSET(1)) {
  1395. dst->ret = user_regset_copyin_ignore(&dst->pos, &dst->count,
  1396. &dst->u.set.kbuf,
  1397. &dst->u.set.ubuf,
  1398. 0, ELF_GR_OFFSET(1));
  1399. if (dst->ret || dst->count == 0)
  1400. return;
  1401. }
  1402. /* gr1-gr15 */
  1403. if (dst->count > 0 && dst->pos < ELF_GR_OFFSET(16)) {
  1404. i = dst->pos;
  1405. index = (dst->pos - ELF_GR_OFFSET(1)) / sizeof(elf_greg_t);
  1406. dst->ret = user_regset_copyin(&dst->pos, &dst->count,
  1407. &dst->u.set.kbuf, &dst->u.set.ubuf, tmp,
  1408. ELF_GR_OFFSET(1), ELF_GR_OFFSET(16));
  1409. if (dst->ret)
  1410. return;
  1411. for ( ; i < dst->pos; i += sizeof(elf_greg_t), index++)
  1412. if (access_elf_reg(dst->target, info, i,
  1413. &tmp[index], 1) < 0) {
  1414. dst->ret = -EIO;
  1415. return;
  1416. }
  1417. if (dst->count == 0)
  1418. return;
  1419. }
  1420. /* gr16-gr31 */
  1421. if (dst->count > 0 && dst->pos < ELF_NAT_OFFSET) {
  1422. pt = task_pt_regs(dst->target);
  1423. dst->ret = user_regset_copyin(&dst->pos, &dst->count,
  1424. &dst->u.set.kbuf, &dst->u.set.ubuf, &pt->r16,
  1425. ELF_GR_OFFSET(16), ELF_NAT_OFFSET);
  1426. if (dst->ret || dst->count == 0)
  1427. return;
  1428. }
  1429. /* nat, pr, b0 - b7 */
  1430. if (dst->count > 0 && dst->pos < ELF_CR_IIP_OFFSET) {
  1431. i = dst->pos;
  1432. index = (dst->pos - ELF_NAT_OFFSET) / sizeof(elf_greg_t);
  1433. dst->ret = user_regset_copyin(&dst->pos, &dst->count,
  1434. &dst->u.set.kbuf, &dst->u.set.ubuf, tmp,
  1435. ELF_NAT_OFFSET, ELF_CR_IIP_OFFSET);
  1436. if (dst->ret)
  1437. return;
  1438. for (; i < dst->pos; i += sizeof(elf_greg_t), index++)
  1439. if (access_elf_reg(dst->target, info, i,
  1440. &tmp[index], 1) < 0) {
  1441. dst->ret = -EIO;
  1442. return;
  1443. }
  1444. if (dst->count == 0)
  1445. return;
  1446. }
  1447. /* ip cfm psr ar.rsc ar.bsp ar.bspstore ar.rnat
  1448. * ar.ccv ar.unat ar.fpsr ar.pfs ar.lc ar.ec ar.csd ar.ssd
  1449. */
  1450. if (dst->count > 0 && dst->pos < (ELF_AR_END_OFFSET)) {
  1451. i = dst->pos;
  1452. index = (dst->pos - ELF_CR_IIP_OFFSET) / sizeof(elf_greg_t);
  1453. dst->ret = user_regset_copyin(&dst->pos, &dst->count,
  1454. &dst->u.set.kbuf, &dst->u.set.ubuf, tmp,
  1455. ELF_CR_IIP_OFFSET, ELF_AR_END_OFFSET);
  1456. if (dst->ret)
  1457. return;
  1458. for ( ; i < dst->pos; i += sizeof(elf_greg_t), index++)
  1459. if (access_elf_reg(dst->target, info, i,
  1460. &tmp[index], 1) < 0) {
  1461. dst->ret = -EIO;
  1462. return;
  1463. }
  1464. }
  1465. }
  1466. #define ELF_FP_OFFSET(i) (i * sizeof(elf_fpreg_t))
  1467. void do_fpregs_get(struct unw_frame_info *info, void *arg)
  1468. {
  1469. struct regset_getset *dst = arg;
  1470. struct task_struct *task = dst->target;
  1471. elf_fpreg_t tmp[30];
  1472. int index, min_copy, i;
  1473. if (unw_unwind_to_user(info) < 0)
  1474. return;
  1475. /* Skip pos 0 and 1 */
  1476. if (dst->count > 0 && dst->pos < ELF_FP_OFFSET(2)) {
  1477. dst->ret = user_regset_copyout_zero(&dst->pos, &dst->count,
  1478. &dst->u.get.kbuf,
  1479. &dst->u.get.ubuf,
  1480. 0, ELF_FP_OFFSET(2));
  1481. if (dst->count == 0 || dst->ret)
  1482. return;
  1483. }
  1484. /* fr2-fr31 */
  1485. if (dst->count > 0 && dst->pos < ELF_FP_OFFSET(32)) {
  1486. index = (dst->pos - ELF_FP_OFFSET(2)) / sizeof(elf_fpreg_t);
  1487. min_copy = min(((unsigned int)ELF_FP_OFFSET(32)),
  1488. dst->pos + dst->count);
  1489. for (i = dst->pos; i < min_copy; i += sizeof(elf_fpreg_t),
  1490. index++)
  1491. if (unw_get_fr(info, i / sizeof(elf_fpreg_t),
  1492. &tmp[index])) {
  1493. dst->ret = -EIO;
  1494. return;
  1495. }
  1496. dst->ret = user_regset_copyout(&dst->pos, &dst->count,
  1497. &dst->u.get.kbuf, &dst->u.get.ubuf, tmp,
  1498. ELF_FP_OFFSET(2), ELF_FP_OFFSET(32));
  1499. if (dst->count == 0 || dst->ret)
  1500. return;
  1501. }
  1502. /* fph */
  1503. if (dst->count > 0) {
  1504. ia64_flush_fph(dst->target);
  1505. if (task->thread.flags & IA64_THREAD_FPH_VALID)
  1506. dst->ret = user_regset_copyout(
  1507. &dst->pos, &dst->count,
  1508. &dst->u.get.kbuf, &dst->u.get.ubuf,
  1509. &dst->target->thread.fph,
  1510. ELF_FP_OFFSET(32), -1);
  1511. else
  1512. /* Zero fill instead. */
  1513. dst->ret = user_regset_copyout_zero(
  1514. &dst->pos, &dst->count,
  1515. &dst->u.get.kbuf, &dst->u.get.ubuf,
  1516. ELF_FP_OFFSET(32), -1);
  1517. }
  1518. }
  1519. void do_fpregs_set(struct unw_frame_info *info, void *arg)
  1520. {
  1521. struct regset_getset *dst = arg;
  1522. elf_fpreg_t fpreg, tmp[30];
  1523. int index, start, end;
  1524. if (unw_unwind_to_user(info) < 0)
  1525. return;
  1526. /* Skip pos 0 and 1 */
  1527. if (dst->count > 0 && dst->pos < ELF_FP_OFFSET(2)) {
  1528. dst->ret = user_regset_copyin_ignore(&dst->pos, &dst->count,
  1529. &dst->u.set.kbuf,
  1530. &dst->u.set.ubuf,
  1531. 0, ELF_FP_OFFSET(2));
  1532. if (dst->count == 0 || dst->ret)
  1533. return;
  1534. }
  1535. /* fr2-fr31 */
  1536. if (dst->count > 0 && dst->pos < ELF_FP_OFFSET(32)) {
  1537. start = dst->pos;
  1538. end = min(((unsigned int)ELF_FP_OFFSET(32)),
  1539. dst->pos + dst->count);
  1540. dst->ret = user_regset_copyin(&dst->pos, &dst->count,
  1541. &dst->u.set.kbuf, &dst->u.set.ubuf, tmp,
  1542. ELF_FP_OFFSET(2), ELF_FP_OFFSET(32));
  1543. if (dst->ret)
  1544. return;
  1545. if (start & 0xF) { /* only write high part */
  1546. if (unw_get_fr(info, start / sizeof(elf_fpreg_t),
  1547. &fpreg)) {
  1548. dst->ret = -EIO;
  1549. return;
  1550. }
  1551. tmp[start / sizeof(elf_fpreg_t) - 2].u.bits[0]
  1552. = fpreg.u.bits[0];
  1553. start &= ~0xFUL;
  1554. }
  1555. if (end & 0xF) { /* only write low part */
  1556. if (unw_get_fr(info, end / sizeof(elf_fpreg_t),
  1557. &fpreg)) {
  1558. dst->ret = -EIO;
  1559. return;
  1560. }
  1561. tmp[end / sizeof(elf_fpreg_t) - 2].u.bits[1]
  1562. = fpreg.u.bits[1];
  1563. end = (end + 0xF) & ~0xFUL;
  1564. }
  1565. for ( ; start < end ; start += sizeof(elf_fpreg_t)) {
  1566. index = start / sizeof(elf_fpreg_t);
  1567. if (unw_set_fr(info, index, tmp[index - 2])) {
  1568. dst->ret = -EIO;
  1569. return;
  1570. }
  1571. }
  1572. if (dst->ret || dst->count == 0)
  1573. return;
  1574. }
  1575. /* fph */
  1576. if (dst->count > 0 && dst->pos < ELF_FP_OFFSET(128)) {
  1577. ia64_sync_fph(dst->target);
  1578. dst->ret = user_regset_copyin(&dst->pos, &dst->count,
  1579. &dst->u.set.kbuf,
  1580. &dst->u.set.ubuf,
  1581. &dst->target->thread.fph,
  1582. ELF_FP_OFFSET(32), -1);
  1583. }
  1584. }
  1585. static int
  1586. do_regset_call(void (*call)(struct unw_frame_info *, void *),
  1587. struct task_struct *target,
  1588. const struct user_regset *regset,
  1589. unsigned int pos, unsigned int count,
  1590. const void *kbuf, const void __user *ubuf)
  1591. {
  1592. struct regset_getset info = { .target = target, .regset = regset,
  1593. .pos = pos, .count = count,
  1594. .u.set = { .kbuf = kbuf, .ubuf = ubuf },
  1595. .ret = 0 };
  1596. if (target == current)
  1597. unw_init_running(call, &info);
  1598. else {
  1599. struct unw_frame_info ufi;
  1600. memset(&ufi, 0, sizeof(ufi));
  1601. unw_init_from_blocked_task(&ufi, target);
  1602. (*call)(&ufi, &info);
  1603. }
  1604. return info.ret;
  1605. }
  1606. static int
  1607. gpregs_get(struct task_struct *target,
  1608. const struct user_regset *regset,
  1609. unsigned int pos, unsigned int count,
  1610. void *kbuf, void __user *ubuf)
  1611. {
  1612. return do_regset_call(do_gpregs_get, target, regset, pos, count,
  1613. kbuf, ubuf);
  1614. }
  1615. static int gpregs_set(struct task_struct *target,
  1616. const struct user_regset *regset,
  1617. unsigned int pos, unsigned int count,
  1618. const void *kbuf, const void __user *ubuf)
  1619. {
  1620. return do_regset_call(do_gpregs_set, target, regset, pos, count,
  1621. kbuf, ubuf);
  1622. }
  1623. static void do_gpregs_writeback(struct unw_frame_info *info, void *arg)
  1624. {
  1625. do_sync_rbs(info, ia64_sync_user_rbs);
  1626. }
  1627. /*
  1628. * This is called to write back the register backing store.
  1629. * ptrace does this before it stops, so that a tracer reading the user
  1630. * memory after the thread stops will get the current register data.
  1631. */
  1632. static int
  1633. gpregs_writeback(struct task_struct *target,
  1634. const struct user_regset *regset,
  1635. int now)
  1636. {
  1637. if (test_and_set_tsk_thread_flag(target, TIF_RESTORE_RSE))
  1638. return 0;
  1639. set_notify_resume(target);
  1640. return do_regset_call(do_gpregs_writeback, target, regset, 0, 0,
  1641. NULL, NULL);
  1642. }
  1643. static int
  1644. fpregs_active(struct task_struct *target, const struct user_regset *regset)
  1645. {
  1646. return (target->thread.flags & IA64_THREAD_FPH_VALID) ? 128 : 32;
  1647. }
  1648. static int fpregs_get(struct task_struct *target,
  1649. const struct user_regset *regset,
  1650. unsigned int pos, unsigned int count,
  1651. void *kbuf, void __user *ubuf)
  1652. {
  1653. return do_regset_call(do_fpregs_get, target, regset, pos, count,
  1654. kbuf, ubuf);
  1655. }
  1656. static int fpregs_set(struct task_struct *target,
  1657. const struct user_regset *regset,
  1658. unsigned int pos, unsigned int count,
  1659. const void *kbuf, const void __user *ubuf)
  1660. {
  1661. return do_regset_call(do_fpregs_set, target, regset, pos, count,
  1662. kbuf, ubuf);
  1663. }
  1664. static int
  1665. access_uarea(struct task_struct *child, unsigned long addr,
  1666. unsigned long *data, int write_access)
  1667. {
  1668. unsigned int pos = -1; /* an invalid value */
  1669. int ret;
  1670. unsigned long *ptr, regnum;
  1671. if ((addr & 0x7) != 0) {
  1672. dprintk("ptrace: unaligned register address 0x%lx\n", addr);
  1673. return -1;
  1674. }
  1675. if ((addr >= PT_NAT_BITS + 8 && addr < PT_F2) ||
  1676. (addr >= PT_R7 + 8 && addr < PT_B1) ||
  1677. (addr >= PT_AR_LC + 8 && addr < PT_CR_IPSR) ||
  1678. (addr >= PT_AR_SSD + 8 && addr < PT_DBR)) {
  1679. dprintk("ptrace: rejecting access to register "
  1680. "address 0x%lx\n", addr);
  1681. return -1;
  1682. }
  1683. switch (addr) {
  1684. case PT_F32 ... (PT_F127 + 15):
  1685. pos = addr - PT_F32 + ELF_FP_OFFSET(32);
  1686. break;
  1687. case PT_F2 ... (PT_F5 + 15):
  1688. pos = addr - PT_F2 + ELF_FP_OFFSET(2);
  1689. break;
  1690. case PT_F10 ... (PT_F31 + 15):
  1691. pos = addr - PT_F10 + ELF_FP_OFFSET(10);
  1692. break;
  1693. case PT_F6 ... (PT_F9 + 15):
  1694. pos = addr - PT_F6 + ELF_FP_OFFSET(6);
  1695. break;
  1696. }
  1697. if (pos != -1) {
  1698. if (write_access)
  1699. ret = fpregs_set(child, NULL, pos,
  1700. sizeof(unsigned long), data, NULL);
  1701. else
  1702. ret = fpregs_get(child, NULL, pos,
  1703. sizeof(unsigned long), data, NULL);
  1704. if (ret != 0)
  1705. return -1;
  1706. return 0;
  1707. }
  1708. switch (addr) {
  1709. case PT_NAT_BITS:
  1710. pos = ELF_NAT_OFFSET;
  1711. break;
  1712. case PT_R4 ... PT_R7:
  1713. pos = addr - PT_R4 + ELF_GR_OFFSET(4);
  1714. break;
  1715. case PT_B1 ... PT_B5:
  1716. pos = addr - PT_B1 + ELF_BR_OFFSET(1);
  1717. break;
  1718. case PT_AR_EC:
  1719. pos = ELF_AR_EC_OFFSET;
  1720. break;
  1721. case PT_AR_LC:
  1722. pos = ELF_AR_LC_OFFSET;
  1723. break;
  1724. case PT_CR_IPSR:
  1725. pos = ELF_CR_IPSR_OFFSET;
  1726. break;
  1727. case PT_CR_IIP:
  1728. pos = ELF_CR_IIP_OFFSET;
  1729. break;
  1730. case PT_CFM:
  1731. pos = ELF_CFM_OFFSET;
  1732. break;
  1733. case PT_AR_UNAT:
  1734. pos = ELF_AR_UNAT_OFFSET;
  1735. break;
  1736. case PT_AR_PFS:
  1737. pos = ELF_AR_PFS_OFFSET;
  1738. break;
  1739. case PT_AR_RSC:
  1740. pos = ELF_AR_RSC_OFFSET;
  1741. break;
  1742. case PT_AR_RNAT:
  1743. pos = ELF_AR_RNAT_OFFSET;
  1744. break;
  1745. case PT_AR_BSPSTORE:
  1746. pos = ELF_AR_BSPSTORE_OFFSET;
  1747. break;
  1748. case PT_PR:
  1749. pos = ELF_PR_OFFSET;
  1750. break;
  1751. case PT_B6:
  1752. pos = ELF_BR_OFFSET(6);
  1753. break;
  1754. case PT_AR_BSP:
  1755. pos = ELF_AR_BSP_OFFSET;
  1756. break;
  1757. case PT_R1 ... PT_R3:
  1758. pos = addr - PT_R1 + ELF_GR_OFFSET(1);
  1759. break;
  1760. case PT_R12 ... PT_R15:
  1761. pos = addr - PT_R12 + ELF_GR_OFFSET(12);
  1762. break;
  1763. case PT_R8 ... PT_R11:
  1764. pos = addr - PT_R8 + ELF_GR_OFFSET(8);
  1765. break;
  1766. case PT_R16 ... PT_R31:
  1767. pos = addr - PT_R16 + ELF_GR_OFFSET(16);
  1768. break;
  1769. case PT_AR_CCV:
  1770. pos = ELF_AR_CCV_OFFSET;
  1771. break;
  1772. case PT_AR_FPSR:
  1773. pos = ELF_AR_FPSR_OFFSET;
  1774. break;
  1775. case PT_B0:
  1776. pos = ELF_BR_OFFSET(0);
  1777. break;
  1778. case PT_B7:
  1779. pos = ELF_BR_OFFSET(7);
  1780. break;
  1781. case PT_AR_CSD:
  1782. pos = ELF_AR_CSD_OFFSET;
  1783. break;
  1784. case PT_AR_SSD:
  1785. pos = ELF_AR_SSD_OFFSET;
  1786. break;
  1787. }
  1788. if (pos != -1) {
  1789. if (write_access)
  1790. ret = gpregs_set(child, NULL, pos,
  1791. sizeof(unsigned long), data, NULL);
  1792. else
  1793. ret = gpregs_get(child, NULL, pos,
  1794. sizeof(unsigned long), data, NULL);
  1795. if (ret != 0)
  1796. return -1;
  1797. return 0;
  1798. }
  1799. /* access debug registers */
  1800. if (addr >= PT_IBR) {
  1801. regnum = (addr - PT_IBR) >> 3;
  1802. ptr = &child->thread.ibr[0];
  1803. } else {
  1804. regnum = (addr - PT_DBR) >> 3;
  1805. ptr = &child->thread.dbr[0];
  1806. }
  1807. if (regnum >= 8) {
  1808. dprintk("ptrace: rejecting access to register "
  1809. "address 0x%lx\n", addr);
  1810. return -1;
  1811. }
  1812. #ifdef CONFIG_PERFMON
  1813. /*
  1814. * Check if debug registers are used by perfmon. This
  1815. * test must be done once we know that we can do the
  1816. * operation, i.e. the arguments are all valid, but
  1817. * before we start modifying the state.
  1818. *
  1819. * Perfmon needs to keep a count of how many processes
  1820. * are trying to modify the debug registers for system
  1821. * wide monitoring sessions.
  1822. *
  1823. * We also include read access here, because they may
  1824. * cause the PMU-installed debug register state
  1825. * (dbr[], ibr[]) to be reset. The two arrays are also
  1826. * used by perfmon, but we do not use
  1827. * IA64_THREAD_DBG_VALID. The registers are restored
  1828. * by the PMU context switch code.
  1829. */
  1830. if (pfm_use_debug_registers(child))
  1831. return -1;
  1832. #endif
  1833. if (!(child->thread.flags & IA64_THREAD_DBG_VALID)) {
  1834. child->thread.flags |= IA64_THREAD_DBG_VALID;
  1835. memset(child->thread.dbr, 0,
  1836. sizeof(child->thread.dbr));
  1837. memset(child->thread.ibr, 0,
  1838. sizeof(child->thread.ibr));
  1839. }
  1840. ptr += regnum;
  1841. if ((regnum & 1) && write_access) {
  1842. /* don't let the user set kernel-level breakpoints: */
  1843. *ptr = *data & ~(7UL << 56);
  1844. return 0;
  1845. }
  1846. if (write_access)
  1847. *ptr = *data;
  1848. else
  1849. *data = *ptr;
  1850. return 0;
  1851. }
  1852. static const struct user_regset native_regsets[] = {
  1853. {
  1854. .core_note_type = NT_PRSTATUS,
  1855. .n = ELF_NGREG,
  1856. .size = sizeof(elf_greg_t), .align = sizeof(elf_greg_t),
  1857. .get = gpregs_get, .set = gpregs_set,
  1858. .writeback = gpregs_writeback
  1859. },
  1860. {
  1861. .core_note_type = NT_PRFPREG,
  1862. .n = ELF_NFPREG,
  1863. .size = sizeof(elf_fpreg_t), .align = sizeof(elf_fpreg_t),
  1864. .get = fpregs_get, .set = fpregs_set, .active = fpregs_active
  1865. },
  1866. };
  1867. static const struct user_regset_view user_ia64_view = {
  1868. .name = "ia64",
  1869. .e_machine = EM_IA_64,
  1870. .regsets = native_regsets, .n = ARRAY_SIZE(native_regsets)
  1871. };
  1872. const struct user_regset_view *task_user_regset_view(struct task_struct *tsk)
  1873. {
  1874. return &user_ia64_view;
  1875. }
  1876. struct syscall_get_set_args {
  1877. unsigned int i;
  1878. unsigned int n;
  1879. unsigned long *args;
  1880. struct pt_regs *regs;
  1881. int rw;
  1882. };
  1883. static void syscall_get_set_args_cb(struct unw_frame_info *info, void *data)
  1884. {
  1885. struct syscall_get_set_args *args = data;
  1886. struct pt_regs *pt = args->regs;
  1887. unsigned long *krbs, cfm, ndirty;
  1888. int i, count;
  1889. if (unw_unwind_to_user(info) < 0)
  1890. return;
  1891. cfm = pt->cr_ifs;
  1892. krbs = (unsigned long *)info->task + IA64_RBS_OFFSET/8;
  1893. ndirty = ia64_rse_num_regs(krbs, krbs + (pt->loadrs >> 19));
  1894. count = 0;
  1895. if (in_syscall(pt))
  1896. count = min_t(int, args->n, cfm & 0x7f);
  1897. for (i = 0; i < count; i++) {
  1898. if (args->rw)
  1899. *ia64_rse_skip_regs(krbs, ndirty + i + args->i) =
  1900. args->args[i];
  1901. else
  1902. args->args[i] = *ia64_rse_skip_regs(krbs,
  1903. ndirty + i + args->i);
  1904. }
  1905. if (!args->rw) {
  1906. while (i < args->n) {
  1907. args->args[i] = 0;
  1908. i++;
  1909. }
  1910. }
  1911. }
  1912. void ia64_syscall_get_set_arguments(struct task_struct *task,
  1913. struct pt_regs *regs, unsigned int i, unsigned int n,
  1914. unsigned long *args, int rw)
  1915. {
  1916. struct syscall_get_set_args data = {
  1917. .i = i,
  1918. .n = n,
  1919. .args = args,
  1920. .regs = regs,
  1921. .rw = rw,
  1922. };
  1923. if (task == current)
  1924. unw_init_running(syscall_get_set_args_cb, &data);
  1925. else {
  1926. struct unw_frame_info ufi;
  1927. memset(&ufi, 0, sizeof(ufi));
  1928. unw_init_from_blocked_task(&ufi, task);
  1929. syscall_get_set_args_cb(&ufi, &data);
  1930. }
  1931. }