clock.c 12 KB

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  1. /*
  2. * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
  3. * Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
  4. * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  19. */
  20. #include <linux/kernel.h>
  21. #include <linux/init.h>
  22. #include <linux/types.h>
  23. #include <linux/module.h>
  24. #include <linux/delay.h>
  25. #include <linux/gcd.h>
  26. #include <linux/io.h>
  27. #include <linux/err.h>
  28. #include <linux/clk.h>
  29. #include <asm/addrspace.h>
  30. #include <asm/mach-ar7/ar7.h>
  31. #define BOOT_PLL_SOURCE_MASK 0x3
  32. #define CPU_PLL_SOURCE_SHIFT 16
  33. #define BUS_PLL_SOURCE_SHIFT 14
  34. #define USB_PLL_SOURCE_SHIFT 18
  35. #define DSP_PLL_SOURCE_SHIFT 22
  36. #define BOOT_PLL_SOURCE_AFE 0
  37. #define BOOT_PLL_SOURCE_BUS 0
  38. #define BOOT_PLL_SOURCE_REF 1
  39. #define BOOT_PLL_SOURCE_XTAL 2
  40. #define BOOT_PLL_SOURCE_CPU 3
  41. #define BOOT_PLL_BYPASS 0x00000020
  42. #define BOOT_PLL_ASYNC_MODE 0x02000000
  43. #define BOOT_PLL_2TO1_MODE 0x00008000
  44. #define TNETD7200_CLOCK_ID_CPU 0
  45. #define TNETD7200_CLOCK_ID_DSP 1
  46. #define TNETD7200_CLOCK_ID_USB 2
  47. #define TNETD7200_DEF_CPU_CLK 211000000
  48. #define TNETD7200_DEF_DSP_CLK 125000000
  49. #define TNETD7200_DEF_USB_CLK 48000000
  50. struct tnetd7300_clock {
  51. u32 ctrl;
  52. #define PREDIV_MASK 0x001f0000
  53. #define PREDIV_SHIFT 16
  54. #define POSTDIV_MASK 0x0000001f
  55. u32 unused1[3];
  56. u32 pll;
  57. #define MUL_MASK 0x0000f000
  58. #define MUL_SHIFT 12
  59. #define PLL_MODE_MASK 0x00000001
  60. #define PLL_NDIV 0x00000800
  61. #define PLL_DIV 0x00000002
  62. #define PLL_STATUS 0x00000001
  63. u32 unused2[3];
  64. };
  65. struct tnetd7300_clocks {
  66. struct tnetd7300_clock bus;
  67. struct tnetd7300_clock cpu;
  68. struct tnetd7300_clock usb;
  69. struct tnetd7300_clock dsp;
  70. };
  71. struct tnetd7200_clock {
  72. u32 ctrl;
  73. u32 unused1[3];
  74. #define DIVISOR_ENABLE_MASK 0x00008000
  75. u32 mul;
  76. u32 prediv;
  77. u32 postdiv;
  78. u32 postdiv2;
  79. u32 unused2[6];
  80. u32 cmd;
  81. u32 status;
  82. u32 cmden;
  83. u32 padding[15];
  84. };
  85. struct tnetd7200_clocks {
  86. struct tnetd7200_clock cpu;
  87. struct tnetd7200_clock dsp;
  88. struct tnetd7200_clock usb;
  89. };
  90. static struct clk bus_clk = {
  91. .rate = 125000000,
  92. };
  93. static struct clk cpu_clk = {
  94. .rate = 150000000,
  95. };
  96. static struct clk dsp_clk;
  97. static struct clk vbus_clk;
  98. static void approximate(int base, int target, int *prediv,
  99. int *postdiv, int *mul)
  100. {
  101. int i, j, k, freq, res = target;
  102. for (i = 1; i <= 16; i++)
  103. for (j = 1; j <= 32; j++)
  104. for (k = 1; k <= 32; k++) {
  105. freq = abs(base / j * i / k - target);
  106. if (freq < res) {
  107. res = freq;
  108. *mul = i;
  109. *prediv = j;
  110. *postdiv = k;
  111. }
  112. }
  113. }
  114. static void calculate(int base, int target, int *prediv, int *postdiv,
  115. int *mul)
  116. {
  117. int tmp_gcd, tmp_base, tmp_freq;
  118. for (*prediv = 1; *prediv <= 32; (*prediv)++) {
  119. tmp_base = base / *prediv;
  120. tmp_gcd = gcd(target, tmp_base);
  121. *mul = target / tmp_gcd;
  122. *postdiv = tmp_base / tmp_gcd;
  123. if ((*mul < 1) || (*mul >= 16))
  124. continue;
  125. if ((*postdiv > 0) & (*postdiv <= 32))
  126. break;
  127. }
  128. if (base / *prediv * *mul / *postdiv != target) {
  129. approximate(base, target, prediv, postdiv, mul);
  130. tmp_freq = base / *prediv * *mul / *postdiv;
  131. printk(KERN_WARNING
  132. "Adjusted requested frequency %d to %d\n",
  133. target, tmp_freq);
  134. }
  135. printk(KERN_DEBUG "Clocks: prediv: %d, postdiv: %d, mul: %d\n",
  136. *prediv, *postdiv, *mul);
  137. }
  138. static int tnetd7300_dsp_clock(void)
  139. {
  140. u32 didr1, didr2;
  141. u8 rev = ar7_chip_rev();
  142. didr1 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x18));
  143. didr2 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x1c));
  144. if (didr2 & (1 << 23))
  145. return 0;
  146. if ((rev >= 0x23) && (rev != 0x57))
  147. return 250000000;
  148. if ((((didr2 & 0x1fff) << 10) | ((didr1 & 0xffc00000) >> 22))
  149. > 4208000)
  150. return 250000000;
  151. return 0;
  152. }
  153. static int tnetd7300_get_clock(u32 shift, struct tnetd7300_clock *clock,
  154. u32 *bootcr, u32 bus_clock)
  155. {
  156. int product;
  157. int base_clock = AR7_REF_CLOCK;
  158. u32 ctrl = readl(&clock->ctrl);
  159. u32 pll = readl(&clock->pll);
  160. int prediv = ((ctrl & PREDIV_MASK) >> PREDIV_SHIFT) + 1;
  161. int postdiv = (ctrl & POSTDIV_MASK) + 1;
  162. int divisor = prediv * postdiv;
  163. int mul = ((pll & MUL_MASK) >> MUL_SHIFT) + 1;
  164. switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
  165. case BOOT_PLL_SOURCE_BUS:
  166. base_clock = bus_clock;
  167. break;
  168. case BOOT_PLL_SOURCE_REF:
  169. base_clock = AR7_REF_CLOCK;
  170. break;
  171. case BOOT_PLL_SOURCE_XTAL:
  172. base_clock = AR7_XTAL_CLOCK;
  173. break;
  174. case BOOT_PLL_SOURCE_CPU:
  175. base_clock = cpu_clk.rate;
  176. break;
  177. }
  178. if (*bootcr & BOOT_PLL_BYPASS)
  179. return base_clock / divisor;
  180. if ((pll & PLL_MODE_MASK) == 0)
  181. return (base_clock >> (mul / 16 + 1)) / divisor;
  182. if ((pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) {
  183. product = (mul & 1) ?
  184. (base_clock * mul) >> 1 :
  185. (base_clock * (mul - 1)) >> 2;
  186. return product / divisor;
  187. }
  188. if (mul == 16)
  189. return base_clock / divisor;
  190. return base_clock * mul / divisor;
  191. }
  192. static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock,
  193. u32 *bootcr, u32 frequency)
  194. {
  195. int prediv, postdiv, mul;
  196. int base_clock = bus_clk.rate;
  197. switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
  198. case BOOT_PLL_SOURCE_BUS:
  199. base_clock = bus_clk.rate;
  200. break;
  201. case BOOT_PLL_SOURCE_REF:
  202. base_clock = AR7_REF_CLOCK;
  203. break;
  204. case BOOT_PLL_SOURCE_XTAL:
  205. base_clock = AR7_XTAL_CLOCK;
  206. break;
  207. case BOOT_PLL_SOURCE_CPU:
  208. base_clock = cpu_clk.rate;
  209. break;
  210. }
  211. calculate(base_clock, frequency, &prediv, &postdiv, &mul);
  212. writel(((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1), &clock->ctrl);
  213. mdelay(1);
  214. writel(4, &clock->pll);
  215. while (readl(&clock->pll) & PLL_STATUS)
  216. ;
  217. writel(((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e, &clock->pll);
  218. mdelay(75);
  219. }
  220. static void __init tnetd7300_init_clocks(void)
  221. {
  222. u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
  223. struct tnetd7300_clocks *clocks =
  224. ioremap_nocache(UR8_REGS_CLOCKS,
  225. sizeof(struct tnetd7300_clocks));
  226. bus_clk.rate = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT,
  227. &clocks->bus, bootcr, AR7_AFE_CLOCK);
  228. if (*bootcr & BOOT_PLL_ASYNC_MODE)
  229. cpu_clk.rate = tnetd7300_get_clock(CPU_PLL_SOURCE_SHIFT,
  230. &clocks->cpu, bootcr, AR7_AFE_CLOCK);
  231. else
  232. cpu_clk.rate = bus_clk.rate;
  233. if (dsp_clk.rate == 250000000)
  234. tnetd7300_set_clock(DSP_PLL_SOURCE_SHIFT, &clocks->dsp,
  235. bootcr, dsp_clk.rate);
  236. iounmap(clocks);
  237. iounmap(bootcr);
  238. }
  239. static void tnetd7200_set_clock(int base, struct tnetd7200_clock *clock,
  240. int prediv, int postdiv, int postdiv2, int mul, u32 frequency)
  241. {
  242. printk(KERN_INFO
  243. "Clocks: base = %d, frequency = %u, prediv = %d, "
  244. "postdiv = %d, postdiv2 = %d, mul = %d\n",
  245. base, frequency, prediv, postdiv, postdiv2, mul);
  246. writel(0, &clock->ctrl);
  247. writel(DIVISOR_ENABLE_MASK | ((prediv - 1) & 0x1F), &clock->prediv);
  248. writel((mul - 1) & 0xF, &clock->mul);
  249. while (readl(&clock->status) & 0x1)
  250. ; /* nop */
  251. writel(DIVISOR_ENABLE_MASK | ((postdiv - 1) & 0x1F), &clock->postdiv);
  252. writel(readl(&clock->cmden) | 1, &clock->cmden);
  253. writel(readl(&clock->cmd) | 1, &clock->cmd);
  254. while (readl(&clock->status) & 0x1)
  255. ; /* nop */
  256. writel(DIVISOR_ENABLE_MASK | ((postdiv2 - 1) & 0x1F), &clock->postdiv2);
  257. writel(readl(&clock->cmden) | 1, &clock->cmden);
  258. writel(readl(&clock->cmd) | 1, &clock->cmd);
  259. while (readl(&clock->status) & 0x1)
  260. ; /* nop */
  261. writel(readl(&clock->ctrl) | 1, &clock->ctrl);
  262. }
  263. static int tnetd7200_get_clock_base(int clock_id, u32 *bootcr)
  264. {
  265. if (*bootcr & BOOT_PLL_ASYNC_MODE)
  266. /* Async */
  267. switch (clock_id) {
  268. case TNETD7200_CLOCK_ID_DSP:
  269. return AR7_REF_CLOCK;
  270. default:
  271. return AR7_AFE_CLOCK;
  272. }
  273. else
  274. /* Sync */
  275. if (*bootcr & BOOT_PLL_2TO1_MODE)
  276. /* 2:1 */
  277. switch (clock_id) {
  278. case TNETD7200_CLOCK_ID_DSP:
  279. return AR7_REF_CLOCK;
  280. default:
  281. return AR7_AFE_CLOCK;
  282. }
  283. else
  284. /* 1:1 */
  285. return AR7_REF_CLOCK;
  286. }
  287. static void __init tnetd7200_init_clocks(void)
  288. {
  289. u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
  290. struct tnetd7200_clocks *clocks =
  291. ioremap_nocache(AR7_REGS_CLOCKS,
  292. sizeof(struct tnetd7200_clocks));
  293. int cpu_base, cpu_mul, cpu_prediv, cpu_postdiv;
  294. int dsp_base, dsp_mul, dsp_prediv, dsp_postdiv;
  295. int usb_base, usb_mul, usb_prediv, usb_postdiv;
  296. cpu_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_CPU, bootcr);
  297. dsp_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_DSP, bootcr);
  298. if (*bootcr & BOOT_PLL_ASYNC_MODE) {
  299. printk(KERN_INFO "Clocks: Async mode\n");
  300. printk(KERN_INFO "Clocks: Setting DSP clock\n");
  301. calculate(dsp_base, TNETD7200_DEF_DSP_CLK,
  302. &dsp_prediv, &dsp_postdiv, &dsp_mul);
  303. bus_clk.rate =
  304. ((dsp_base / dsp_prediv) * dsp_mul) / dsp_postdiv;
  305. tnetd7200_set_clock(dsp_base, &clocks->dsp,
  306. dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2,
  307. bus_clk.rate);
  308. printk(KERN_INFO "Clocks: Setting CPU clock\n");
  309. calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv,
  310. &cpu_postdiv, &cpu_mul);
  311. cpu_clk.rate =
  312. ((cpu_base / cpu_prediv) * cpu_mul) / cpu_postdiv;
  313. tnetd7200_set_clock(cpu_base, &clocks->cpu,
  314. cpu_prediv, cpu_postdiv, -1, cpu_mul,
  315. cpu_clk.rate);
  316. } else
  317. if (*bootcr & BOOT_PLL_2TO1_MODE) {
  318. printk(KERN_INFO "Clocks: Sync 2:1 mode\n");
  319. printk(KERN_INFO "Clocks: Setting CPU clock\n");
  320. calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv,
  321. &cpu_postdiv, &cpu_mul);
  322. cpu_clk.rate = ((cpu_base / cpu_prediv) * cpu_mul)
  323. / cpu_postdiv;
  324. tnetd7200_set_clock(cpu_base, &clocks->cpu,
  325. cpu_prediv, cpu_postdiv, -1, cpu_mul,
  326. cpu_clk.rate);
  327. printk(KERN_INFO "Clocks: Setting DSP clock\n");
  328. calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv,
  329. &dsp_postdiv, &dsp_mul);
  330. bus_clk.rate = cpu_clk.rate / 2;
  331. tnetd7200_set_clock(dsp_base, &clocks->dsp,
  332. dsp_prediv, dsp_postdiv * 2, dsp_postdiv,
  333. dsp_mul * 2, bus_clk.rate);
  334. } else {
  335. printk(KERN_INFO "Clocks: Sync 1:1 mode\n");
  336. printk(KERN_INFO "Clocks: Setting DSP clock\n");
  337. calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv,
  338. &dsp_postdiv, &dsp_mul);
  339. bus_clk.rate = ((dsp_base / dsp_prediv) * dsp_mul)
  340. / dsp_postdiv;
  341. tnetd7200_set_clock(dsp_base, &clocks->dsp,
  342. dsp_prediv, dsp_postdiv * 2, dsp_postdiv,
  343. dsp_mul * 2, bus_clk.rate);
  344. cpu_clk.rate = bus_clk.rate;
  345. }
  346. printk(KERN_INFO "Clocks: Setting USB clock\n");
  347. usb_base = bus_clk.rate;
  348. calculate(usb_base, TNETD7200_DEF_USB_CLK, &usb_prediv,
  349. &usb_postdiv, &usb_mul);
  350. tnetd7200_set_clock(usb_base, &clocks->usb,
  351. usb_prediv, usb_postdiv, -1, usb_mul,
  352. TNETD7200_DEF_USB_CLK);
  353. dsp_clk.rate = cpu_clk.rate;
  354. iounmap(clocks);
  355. iounmap(bootcr);
  356. }
  357. /*
  358. * Linux clock API
  359. */
  360. int clk_enable(struct clk *clk)
  361. {
  362. return 0;
  363. }
  364. EXPORT_SYMBOL(clk_enable);
  365. void clk_disable(struct clk *clk)
  366. {
  367. }
  368. EXPORT_SYMBOL(clk_disable);
  369. unsigned long clk_get_rate(struct clk *clk)
  370. {
  371. return clk->rate;
  372. }
  373. EXPORT_SYMBOL(clk_get_rate);
  374. struct clk *clk_get(struct device *dev, const char *id)
  375. {
  376. if (!strcmp(id, "bus"))
  377. return &bus_clk;
  378. /* cpmac and vbus share the same rate */
  379. if (!strcmp(id, "cpmac"))
  380. return &vbus_clk;
  381. if (!strcmp(id, "cpu"))
  382. return &cpu_clk;
  383. if (!strcmp(id, "dsp"))
  384. return &dsp_clk;
  385. if (!strcmp(id, "vbus"))
  386. return &vbus_clk;
  387. return ERR_PTR(-ENOENT);
  388. }
  389. EXPORT_SYMBOL(clk_get);
  390. void clk_put(struct clk *clk)
  391. {
  392. }
  393. EXPORT_SYMBOL(clk_put);
  394. void __init ar7_init_clocks(void)
  395. {
  396. switch (ar7_chip_id()) {
  397. case AR7_CHIP_7100:
  398. case AR7_CHIP_7200:
  399. tnetd7200_init_clocks();
  400. break;
  401. case AR7_CHIP_7300:
  402. dsp_clk.rate = tnetd7300_dsp_clock();
  403. tnetd7300_init_clocks();
  404. break;
  405. default:
  406. break;
  407. }
  408. /* adjust vbus clock rate */
  409. vbus_clk.rate = bus_clk.rate / 2;
  410. }