setup.c 4.7 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
  7. * Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com>
  8. */
  9. #include <linux/init.h>
  10. #include <linux/bitops.h>
  11. #include <linux/bootmem.h>
  12. #include <linux/clk-provider.h>
  13. #include <linux/ioport.h>
  14. #include <linux/kernel.h>
  15. #include <linux/io.h>
  16. #include <linux/of.h>
  17. #include <linux/of_fdt.h>
  18. #include <linux/of_platform.h>
  19. #include <linux/smp.h>
  20. #include <asm/addrspace.h>
  21. #include <asm/bmips.h>
  22. #include <asm/bootinfo.h>
  23. #include <asm/cpu-type.h>
  24. #include <asm/mipsregs.h>
  25. #include <asm/prom.h>
  26. #include <asm/smp-ops.h>
  27. #include <asm/time.h>
  28. #include <asm/traps.h>
  29. #define RELO_NORMAL_VEC BIT(18)
  30. #define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c))
  31. #define BCM6328_TP1_DISABLED BIT(9)
  32. static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000;
  33. struct bmips_quirk {
  34. const char *compatible;
  35. void (*quirk_fn)(void);
  36. };
  37. static void kbase_setup(void)
  38. {
  39. __raw_writel(kbase | RELO_NORMAL_VEC,
  40. BMIPS_GET_CBR() + BMIPS_RELO_VECTOR_CONTROL_1);
  41. ebase = kbase;
  42. }
  43. static void bcm3384_viper_quirks(void)
  44. {
  45. /*
  46. * Some experimental CM boxes are set up to let CM own the Viper TP0
  47. * and let Linux own TP1. This requires moving the kernel
  48. * load address to a non-conflicting region (e.g. via
  49. * CONFIG_PHYSICAL_START) and supplying an alternate DTB.
  50. * If we detect this condition, we need to move the MIPS exception
  51. * vectors up to an area that we own.
  52. *
  53. * This is distinct from the OTHER special case mentioned in
  54. * smp-bmips.c (boot on TP1, but enable SMP, then TP0 becomes our
  55. * logical CPU#1). For the Viper TP1 case, SMP is off limits.
  56. *
  57. * Also note that many BMIPS435x CPUs do not have a
  58. * BMIPS_RELO_VECTOR_CONTROL_1 register, so it isn't safe to just
  59. * write VMLINUX_LOAD_ADDRESS into that register on every SoC.
  60. */
  61. board_ebase_setup = &kbase_setup;
  62. bmips_smp_enabled = 0;
  63. }
  64. static void bcm63xx_fixup_cpu1(void)
  65. {
  66. /*
  67. * The bootloader has set up the CPU1 reset vector at
  68. * 0xa000_0200.
  69. * This conflicts with the special interrupt vector (IV).
  70. * The bootloader has also set up CPU1 to respond to the wrong
  71. * IPI interrupt.
  72. * Here we will start up CPU1 in the background and ask it to
  73. * reconfigure itself then go back to sleep.
  74. */
  75. memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20);
  76. __sync();
  77. set_c0_cause(C_SW0);
  78. cpumask_set_cpu(1, &bmips_booted_mask);
  79. }
  80. static void bcm6328_quirks(void)
  81. {
  82. /* Check CPU1 status in OTP (it is usually disabled) */
  83. if (__raw_readl(REG_BCM6328_OTP) & BCM6328_TP1_DISABLED)
  84. bmips_smp_enabled = 0;
  85. else
  86. bcm63xx_fixup_cpu1();
  87. }
  88. static void bcm6368_quirks(void)
  89. {
  90. bcm63xx_fixup_cpu1();
  91. }
  92. static const struct bmips_quirk bmips_quirk_list[] = {
  93. { "brcm,bcm3384-viper", &bcm3384_viper_quirks },
  94. { "brcm,bcm33843-viper", &bcm3384_viper_quirks },
  95. { "brcm,bcm6328", &bcm6328_quirks },
  96. { "brcm,bcm6368", &bcm6368_quirks },
  97. { },
  98. };
  99. void __init prom_init(void)
  100. {
  101. register_bmips_smp_ops();
  102. }
  103. void __init prom_free_prom_memory(void)
  104. {
  105. }
  106. const char *get_system_type(void)
  107. {
  108. return "Generic BMIPS kernel";
  109. }
  110. void __init plat_time_init(void)
  111. {
  112. struct device_node *np;
  113. u32 freq;
  114. np = of_find_node_by_name(NULL, "cpus");
  115. if (!np)
  116. panic("missing 'cpus' DT node");
  117. if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0)
  118. panic("missing 'mips-hpt-frequency' property");
  119. of_node_put(np);
  120. mips_hpt_frequency = freq;
  121. }
  122. void __init plat_mem_setup(void)
  123. {
  124. void *dtb;
  125. const struct bmips_quirk *q;
  126. set_io_port_base(0);
  127. ioport_resource.start = 0;
  128. ioport_resource.end = ~0;
  129. /* intended to somewhat resemble ARM; see Documentation/arm/Booting */
  130. if (fw_arg0 == 0 && fw_arg1 == 0xffffffff)
  131. dtb = phys_to_virt(fw_arg2);
  132. else if (fw_arg0 == -2) /* UHI interface */
  133. dtb = (void *)fw_arg1;
  134. else if (__dtb_start != __dtb_end)
  135. dtb = (void *)__dtb_start;
  136. else
  137. panic("no dtb found");
  138. __dt_setup_arch(dtb);
  139. for (q = bmips_quirk_list; q->quirk_fn; q++) {
  140. if (of_flat_dt_is_compatible(of_get_flat_dt_root(),
  141. q->compatible)) {
  142. q->quirk_fn();
  143. }
  144. }
  145. }
  146. void __init device_tree_init(void)
  147. {
  148. struct device_node *np;
  149. unflatten_and_copy_device_tree();
  150. /* Disable SMP boot unless both CPUs are listed in DT and !disabled */
  151. np = of_find_node_by_name(NULL, "cpus");
  152. if (np && of_get_available_child_count(np) <= 1)
  153. bmips_smp_enabled = 0;
  154. of_node_put(np);
  155. }
  156. int __init plat_of_setup(void)
  157. {
  158. return __dt_register_buses("simple-bus", NULL);
  159. }
  160. arch_initcall(plat_of_setup);
  161. static int __init plat_dev_init(void)
  162. {
  163. of_clk_init(NULL);
  164. return 0;
  165. }
  166. device_initcall(plat_dev_init);