malta-int.c 9.9 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Carsten Langgaard, carstenl@mips.com
  7. * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
  8. * Copyright (C) 2001 Ralf Baechle
  9. * Copyright (C) 2013 Imagination Technologies Ltd.
  10. *
  11. * Routines for generic manipulation of the interrupts found on the MIPS
  12. * Malta board. The interrupt controller is located in the South Bridge
  13. * a PIIX4 device with two internal 82C95 interrupt controllers.
  14. */
  15. #include <linux/init.h>
  16. #include <linux/irq.h>
  17. #include <linux/sched.h>
  18. #include <linux/smp.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/io.h>
  21. #include <linux/irqchip/mips-gic.h>
  22. #include <linux/kernel_stat.h>
  23. #include <linux/kernel.h>
  24. #include <linux/random.h>
  25. #include <asm/traps.h>
  26. #include <asm/i8259.h>
  27. #include <asm/irq_cpu.h>
  28. #include <asm/irq_regs.h>
  29. #include <asm/mips-cm.h>
  30. #include <asm/mips-boards/malta.h>
  31. #include <asm/mips-boards/maltaint.h>
  32. #include <asm/gt64120.h>
  33. #include <asm/mips-boards/generic.h>
  34. #include <asm/mips-boards/msc01_pci.h>
  35. #include <asm/msc01_ic.h>
  36. #include <asm/setup.h>
  37. #include <asm/rtlx.h>
  38. static void __iomem *_msc01_biu_base;
  39. static DEFINE_RAW_SPINLOCK(mips_irq_lock);
  40. static inline int mips_pcibios_iack(void)
  41. {
  42. int irq;
  43. /*
  44. * Determine highest priority pending interrupt by performing
  45. * a PCI Interrupt Acknowledge cycle.
  46. */
  47. switch (mips_revision_sconid) {
  48. case MIPS_REVISION_SCON_SOCIT:
  49. case MIPS_REVISION_SCON_ROCIT:
  50. case MIPS_REVISION_SCON_SOCITSC:
  51. case MIPS_REVISION_SCON_SOCITSCP:
  52. MSC_READ(MSC01_PCI_IACK, irq);
  53. irq &= 0xff;
  54. break;
  55. case MIPS_REVISION_SCON_GT64120:
  56. irq = GT_READ(GT_PCI0_IACK_OFS);
  57. irq &= 0xff;
  58. break;
  59. case MIPS_REVISION_SCON_BONITO:
  60. /* The following will generate a PCI IACK cycle on the
  61. * Bonito controller. It's a little bit kludgy, but it
  62. * was the easiest way to implement it in hardware at
  63. * the given time.
  64. */
  65. BONITO_PCIMAP_CFG = 0x20000;
  66. /* Flush Bonito register block */
  67. (void) BONITO_PCIMAP_CFG;
  68. iob(); /* sync */
  69. irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg);
  70. iob(); /* sync */
  71. irq &= 0xff;
  72. BONITO_PCIMAP_CFG = 0;
  73. break;
  74. default:
  75. pr_emerg("Unknown system controller.\n");
  76. return -1;
  77. }
  78. return irq;
  79. }
  80. static inline int get_int(void)
  81. {
  82. unsigned long flags;
  83. int irq;
  84. raw_spin_lock_irqsave(&mips_irq_lock, flags);
  85. irq = mips_pcibios_iack();
  86. /*
  87. * The only way we can decide if an interrupt is spurious
  88. * is by checking the 8259 registers. This needs a spinlock
  89. * on an SMP system, so leave it up to the generic code...
  90. */
  91. raw_spin_unlock_irqrestore(&mips_irq_lock, flags);
  92. return irq;
  93. }
  94. static void malta_hw0_irqdispatch(void)
  95. {
  96. int irq;
  97. irq = get_int();
  98. if (irq < 0) {
  99. /* interrupt has already been cleared */
  100. return;
  101. }
  102. do_IRQ(MALTA_INT_BASE + irq);
  103. #ifdef CONFIG_MIPS_VPE_APSP_API_MT
  104. if (aprp_hook)
  105. aprp_hook();
  106. #endif
  107. }
  108. static irqreturn_t i8259_handler(int irq, void *dev_id)
  109. {
  110. malta_hw0_irqdispatch();
  111. return IRQ_HANDLED;
  112. }
  113. static void corehi_irqdispatch(void)
  114. {
  115. unsigned int intedge, intsteer, pcicmd, pcibadaddr;
  116. unsigned int pcimstat, intisr, inten, intpol;
  117. unsigned int intrcause, datalo, datahi;
  118. struct pt_regs *regs = get_irq_regs();
  119. pr_emerg("CoreHI interrupt, shouldn't happen, we die here!\n");
  120. pr_emerg("epc : %08lx\nStatus: %08lx\n"
  121. "Cause : %08lx\nbadVaddr : %08lx\n",
  122. regs->cp0_epc, regs->cp0_status,
  123. regs->cp0_cause, regs->cp0_badvaddr);
  124. /* Read all the registers and then print them as there is a
  125. problem with interspersed printk's upsetting the Bonito controller.
  126. Do it for the others too.
  127. */
  128. switch (mips_revision_sconid) {
  129. case MIPS_REVISION_SCON_SOCIT:
  130. case MIPS_REVISION_SCON_ROCIT:
  131. case MIPS_REVISION_SCON_SOCITSC:
  132. case MIPS_REVISION_SCON_SOCITSCP:
  133. ll_msc_irq();
  134. break;
  135. case MIPS_REVISION_SCON_GT64120:
  136. intrcause = GT_READ(GT_INTRCAUSE_OFS);
  137. datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
  138. datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
  139. pr_emerg("GT_INTRCAUSE = %08x\n", intrcause);
  140. pr_emerg("GT_CPUERR_ADDR = %02x%08x\n",
  141. datahi, datalo);
  142. break;
  143. case MIPS_REVISION_SCON_BONITO:
  144. pcibadaddr = BONITO_PCIBADADDR;
  145. pcimstat = BONITO_PCIMSTAT;
  146. intisr = BONITO_INTISR;
  147. inten = BONITO_INTEN;
  148. intpol = BONITO_INTPOL;
  149. intedge = BONITO_INTEDGE;
  150. intsteer = BONITO_INTSTEER;
  151. pcicmd = BONITO_PCICMD;
  152. pr_emerg("BONITO_INTISR = %08x\n", intisr);
  153. pr_emerg("BONITO_INTEN = %08x\n", inten);
  154. pr_emerg("BONITO_INTPOL = %08x\n", intpol);
  155. pr_emerg("BONITO_INTEDGE = %08x\n", intedge);
  156. pr_emerg("BONITO_INTSTEER = %08x\n", intsteer);
  157. pr_emerg("BONITO_PCICMD = %08x\n", pcicmd);
  158. pr_emerg("BONITO_PCIBADADDR = %08x\n", pcibadaddr);
  159. pr_emerg("BONITO_PCIMSTAT = %08x\n", pcimstat);
  160. break;
  161. }
  162. die("CoreHi interrupt", regs);
  163. }
  164. static irqreturn_t corehi_handler(int irq, void *dev_id)
  165. {
  166. corehi_irqdispatch();
  167. return IRQ_HANDLED;
  168. }
  169. #ifdef CONFIG_MIPS_MT_SMP
  170. #define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */
  171. #define C_RESCHED C_SW0
  172. #define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for resched */
  173. #define C_CALL C_SW1
  174. static int cpu_ipi_resched_irq, cpu_ipi_call_irq;
  175. static void ipi_resched_dispatch(void)
  176. {
  177. do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
  178. }
  179. static void ipi_call_dispatch(void)
  180. {
  181. do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
  182. }
  183. static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
  184. {
  185. #ifdef CONFIG_MIPS_VPE_APSP_API_CMP
  186. if (aprp_hook)
  187. aprp_hook();
  188. #endif
  189. scheduler_ipi();
  190. return IRQ_HANDLED;
  191. }
  192. static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
  193. {
  194. generic_smp_call_function_interrupt();
  195. return IRQ_HANDLED;
  196. }
  197. static struct irqaction irq_resched = {
  198. .handler = ipi_resched_interrupt,
  199. .flags = IRQF_PERCPU,
  200. .name = "IPI_resched"
  201. };
  202. static struct irqaction irq_call = {
  203. .handler = ipi_call_interrupt,
  204. .flags = IRQF_PERCPU,
  205. .name = "IPI_call"
  206. };
  207. #endif /* CONFIG_MIPS_MT_SMP */
  208. static struct irqaction i8259irq = {
  209. .handler = i8259_handler,
  210. .name = "XT-PIC cascade",
  211. .flags = IRQF_NO_THREAD,
  212. };
  213. static struct irqaction corehi_irqaction = {
  214. .handler = corehi_handler,
  215. .name = "CoreHi",
  216. .flags = IRQF_NO_THREAD,
  217. };
  218. static msc_irqmap_t msc_irqmap[] __initdata = {
  219. {MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0},
  220. {MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0},
  221. };
  222. static int msc_nr_irqs __initdata = ARRAY_SIZE(msc_irqmap);
  223. static msc_irqmap_t msc_eicirqmap[] __initdata = {
  224. {MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0},
  225. {MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0},
  226. {MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0},
  227. {MSC01E_INT_SMI, MSC01_IRQ_LEVEL, 0},
  228. {MSC01E_INT_COREHI, MSC01_IRQ_LEVEL, 0},
  229. {MSC01E_INT_CORELO, MSC01_IRQ_LEVEL, 0},
  230. {MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0},
  231. {MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0},
  232. {MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0},
  233. {MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0}
  234. };
  235. static int msc_nr_eicirqs __initdata = ARRAY_SIZE(msc_eicirqmap);
  236. void __init arch_init_ipiirq(int irq, struct irqaction *action)
  237. {
  238. setup_irq(irq, action);
  239. irq_set_handler(irq, handle_percpu_irq);
  240. }
  241. void __init arch_init_irq(void)
  242. {
  243. int corehi_irq, i8259_irq;
  244. init_i8259_irqs();
  245. if (!cpu_has_veic)
  246. mips_cpu_irq_init();
  247. if (mips_cm_present()) {
  248. write_gcr_gic_base(GIC_BASE_ADDR | CM_GCR_GIC_BASE_GICEN_MSK);
  249. gic_present = 1;
  250. } else {
  251. if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) {
  252. _msc01_biu_base = ioremap_nocache(MSC01_BIU_REG_BASE,
  253. MSC01_BIU_ADDRSPACE_SZ);
  254. gic_present =
  255. (__raw_readl(_msc01_biu_base + MSC01_SC_CFG_OFS) &
  256. MSC01_SC_CFG_GICPRES_MSK) >>
  257. MSC01_SC_CFG_GICPRES_SHF;
  258. }
  259. }
  260. if (gic_present)
  261. pr_debug("GIC present\n");
  262. switch (mips_revision_sconid) {
  263. case MIPS_REVISION_SCON_SOCIT:
  264. case MIPS_REVISION_SCON_ROCIT:
  265. if (cpu_has_veic)
  266. init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
  267. MSC01E_INT_BASE, msc_eicirqmap,
  268. msc_nr_eicirqs);
  269. else
  270. init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
  271. MSC01C_INT_BASE, msc_irqmap,
  272. msc_nr_irqs);
  273. break;
  274. case MIPS_REVISION_SCON_SOCITSC:
  275. case MIPS_REVISION_SCON_SOCITSCP:
  276. if (cpu_has_veic)
  277. init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
  278. MSC01E_INT_BASE, msc_eicirqmap,
  279. msc_nr_eicirqs);
  280. else
  281. init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
  282. MSC01C_INT_BASE, msc_irqmap,
  283. msc_nr_irqs);
  284. }
  285. if (gic_present) {
  286. int i;
  287. gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, MIPSCPU_INT_GIC,
  288. MIPS_GIC_IRQ_BASE);
  289. if (!mips_cm_present()) {
  290. /* Enable the GIC */
  291. i = __raw_readl(_msc01_biu_base + MSC01_SC_CFG_OFS);
  292. __raw_writel(i | (0x1 << MSC01_SC_CFG_GICENA_SHF),
  293. _msc01_biu_base + MSC01_SC_CFG_OFS);
  294. pr_debug("GIC Enabled\n");
  295. }
  296. i8259_irq = MIPS_GIC_IRQ_BASE + GIC_INT_I8259A;
  297. corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
  298. } else {
  299. #if defined(CONFIG_MIPS_MT_SMP)
  300. /* set up ipi interrupts */
  301. if (cpu_has_veic) {
  302. set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch);
  303. set_vi_handler (MSC01E_INT_SW1, ipi_call_dispatch);
  304. cpu_ipi_resched_irq = MSC01E_INT_SW0;
  305. cpu_ipi_call_irq = MSC01E_INT_SW1;
  306. } else {
  307. cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE +
  308. MIPS_CPU_IPI_RESCHED_IRQ;
  309. cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE +
  310. MIPS_CPU_IPI_CALL_IRQ;
  311. }
  312. arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched);
  313. arch_init_ipiirq(cpu_ipi_call_irq, &irq_call);
  314. #endif
  315. if (cpu_has_veic) {
  316. set_vi_handler(MSC01E_INT_I8259A,
  317. malta_hw0_irqdispatch);
  318. set_vi_handler(MSC01E_INT_COREHI,
  319. corehi_irqdispatch);
  320. i8259_irq = MSC01E_INT_BASE + MSC01E_INT_I8259A;
  321. corehi_irq = MSC01E_INT_BASE + MSC01E_INT_COREHI;
  322. } else {
  323. i8259_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_I8259A;
  324. corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
  325. }
  326. }
  327. setup_irq(i8259_irq, &i8259irq);
  328. setup_irq(corehi_irq, &corehi_irqaction);
  329. }
  330. void malta_be_init(void)
  331. {
  332. /* Could change CM error mask register. */
  333. }
  334. int malta_be_handler(struct pt_regs *regs, int is_fixup)
  335. {
  336. /* This duplicates the handling in do_be which seems wrong */
  337. int retval = is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
  338. mips_cm_error_report();
  339. return retval;
  340. }