smsc911x.h 4.2 KB

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  1. /* Support for the SMSC911x NIC
  2. *
  3. * Copyright (C) 2006 Matsushita Electric Industrial Co., Ltd.
  4. * All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version
  9. * 2 of the License, or (at your option) any later version.
  10. */
  11. #ifndef _ASM_UNIT_SMSC911X_H
  12. #define _ASM_UNIT_SMSC911X_H
  13. #include <linux/netdevice.h>
  14. #include <proc/irq.h>
  15. #include <unit/fpga-regs.h>
  16. #define MN10300_USE_EXT_EEPROM
  17. #define SMSC911X_BASE 0xA8000000UL
  18. #define SMSC911X_BASE_END 0xA8000100UL
  19. #define SMSC911X_IRQ FPGA_LAN_IRQ
  20. /*
  21. * Allow the FPGA to be initialised by the SMSC911x driver
  22. */
  23. #undef SMSC_INITIALIZE
  24. #define SMSC_INITIALIZE() \
  25. do { \
  26. /* release reset */ \
  27. ASB2364_FPGA_REG_RESET_LAN = 0x0001; \
  28. SyncExBus(); \
  29. } while (0)
  30. #ifdef MN10300_USE_EXT_EEPROM
  31. #include <linux/delay.h>
  32. #include <unit/clock.h>
  33. #define EEPROM_ADDRESS 0xA0
  34. #define MAC_OFFSET 0x0008
  35. #define USE_IIC_CH 0 /* 0 or 1 */
  36. #define IIC_OFFSET (0x80000 * USE_IIC_CH)
  37. #define IIC_DTRM __SYSREG(0xd8400000 + IIC_OFFSET, u32)
  38. #define IIC_DREC __SYSREG(0xd8400004 + IIC_OFFSET, u32)
  39. #define IIC_MYADD __SYSREG(0xd8400008 + IIC_OFFSET, u32)
  40. #define IIC_CLK __SYSREG(0xd840000c + IIC_OFFSET, u32)
  41. #define IIC_BRST __SYSREG(0xd8400010 + IIC_OFFSET, u32)
  42. #define IIC_HOLD __SYSREG(0xd8400014 + IIC_OFFSET, u32)
  43. #define IIC_BSTS __SYSREG(0xd8400018 + IIC_OFFSET, u32)
  44. #define IIC_ICR __SYSREG(0xd4000080 + 4 * USE_IIC_CH, u16)
  45. #define IIC_CLK_PLS ((unsigned short)(MN10300_IOCLK / 100000 - 1))
  46. #define IIC_CLK_LOW ((unsigned short)(IIC_CLK_PLS / 2))
  47. #define SYS_IIC_DTRM_Bit_STA ((unsigned short)0x0400)
  48. #define SYS_IIC_DTRM_Bit_STO ((unsigned short)0x0200)
  49. #define SYS_IIC_DTRM_Bit_ACK ((unsigned short)0x0100)
  50. #define SYS_IIC_DTRM_Bit_DATA ((unsigned short)0x00FF)
  51. static inline void POLL_INT_REQ(volatile u16 *icr)
  52. {
  53. unsigned long flags;
  54. u16 tmp;
  55. while (!(*icr & GxICR_REQUEST))
  56. ;
  57. flags = arch_local_cli_save();
  58. tmp = *icr;
  59. *icr = (tmp & GxICR_LEVEL) | GxICR_DETECT;
  60. tmp = *icr;
  61. arch_local_irq_restore(flags);
  62. }
  63. /*
  64. * Implement the SMSC911x hook for MAC address retrieval
  65. */
  66. #undef smsc_get_mac
  67. static inline int smsc_get_mac(struct net_device *dev)
  68. {
  69. unsigned char *mac_buf = dev->dev_addr;
  70. int i;
  71. unsigned short value;
  72. unsigned int data;
  73. int mac_length = 6;
  74. int check;
  75. u16 orig_gicr, tmp;
  76. unsigned long flags;
  77. /* save original GnICR and clear GnICR.IE */
  78. flags = arch_local_cli_save();
  79. orig_gicr = IIC_ICR;
  80. IIC_ICR = orig_gicr & GxICR_LEVEL;
  81. tmp = IIC_ICR;
  82. arch_local_irq_restore(flags);
  83. IIC_MYADD = 0x00000008;
  84. IIC_CLK = (IIC_CLK_LOW << 16) + (IIC_CLK_PLS);
  85. /* bus hung recovery */
  86. while (1) {
  87. check = 0;
  88. for (i = 0; i < 3; i++) {
  89. if ((IIC_BSTS & 0x00000003) == 0x00000003)
  90. check++;
  91. udelay(3);
  92. }
  93. if (check == 3) {
  94. IIC_BRST = 0x00000003;
  95. break;
  96. } else {
  97. for (i = 0; i < 3; i++) {
  98. IIC_BRST = 0x00000002;
  99. udelay(8);
  100. IIC_BRST = 0x00000003;
  101. udelay(8);
  102. }
  103. }
  104. }
  105. IIC_BRST = 0x00000002;
  106. IIC_BRST = 0x00000003;
  107. value = SYS_IIC_DTRM_Bit_STA | SYS_IIC_DTRM_Bit_ACK;
  108. value |= (((unsigned short)EEPROM_ADDRESS & SYS_IIC_DTRM_Bit_DATA) |
  109. (unsigned short)0x0000);
  110. IIC_DTRM = value;
  111. POLL_INT_REQ(&IIC_ICR);
  112. /** send offset of MAC address in EEPROM **/
  113. IIC_DTRM = (unsigned char)((MAC_OFFSET & 0xFF00) >> 8);
  114. POLL_INT_REQ(&IIC_ICR);
  115. IIC_DTRM = (unsigned char)(MAC_OFFSET & 0x00FF);
  116. POLL_INT_REQ(&IIC_ICR);
  117. udelay(1000);
  118. value = SYS_IIC_DTRM_Bit_STA;
  119. value |= (((unsigned short)EEPROM_ADDRESS & SYS_IIC_DTRM_Bit_DATA) |
  120. (unsigned short)0x0001);
  121. IIC_DTRM = value;
  122. POLL_INT_REQ(&IIC_ICR);
  123. IIC_DTRM = 0x00000000;
  124. while (mac_length > 0) {
  125. POLL_INT_REQ(&IIC_ICR);
  126. data = IIC_DREC;
  127. mac_length--;
  128. if (mac_length == 0)
  129. value = 0x00000300; /* stop IIC bus */
  130. else if (mac_length == 1)
  131. value = 0x00000100; /* no ack */
  132. else
  133. value = 0x00000000; /* ack */
  134. IIC_DTRM = value;
  135. *mac_buf++ = (unsigned char)(data & 0xff);
  136. }
  137. /* restore GnICR.LV and GnICR.IE */
  138. flags = arch_local_cli_save();
  139. IIC_ICR = (orig_gicr & (GxICR_LEVEL | GxICR_ENABLE));
  140. tmp = IIC_ICR;
  141. arch_local_irq_restore(flags);
  142. return 0;
  143. }
  144. #endif /* MN10300_USE_EXT_EEPROM */
  145. #endif /* _ASM_UNIT_SMSC911X_H */