insnemu.S 15 KB

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  1. /*
  2. * Copyright (C) 2003-2013 Altera Corporation
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; either version 2 of the License, or
  8. * (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #include <linux/linkage.h>
  19. #include <asm/entry.h>
  20. .set noat
  21. .set nobreak
  22. /*
  23. * Explicitly allow the use of r1 (the assembler temporary register)
  24. * within this code. This register is normally reserved for the use of
  25. * the compiler.
  26. */
  27. ENTRY(instruction_trap)
  28. ldw r1, PT_R1(sp) // Restore registers
  29. ldw r2, PT_R2(sp)
  30. ldw r3, PT_R3(sp)
  31. ldw r4, PT_R4(sp)
  32. ldw r5, PT_R5(sp)
  33. ldw r6, PT_R6(sp)
  34. ldw r7, PT_R7(sp)
  35. ldw r8, PT_R8(sp)
  36. ldw r9, PT_R9(sp)
  37. ldw r10, PT_R10(sp)
  38. ldw r11, PT_R11(sp)
  39. ldw r12, PT_R12(sp)
  40. ldw r13, PT_R13(sp)
  41. ldw r14, PT_R14(sp)
  42. ldw r15, PT_R15(sp)
  43. ldw ra, PT_RA(sp)
  44. ldw fp, PT_FP(sp)
  45. ldw gp, PT_GP(sp)
  46. ldw et, PT_ESTATUS(sp)
  47. wrctl estatus, et
  48. ldw ea, PT_EA(sp)
  49. ldw et, PT_SP(sp) /* backup sp in et */
  50. addi sp, sp, PT_REGS_SIZE
  51. /* INSTRUCTION EMULATION
  52. * ---------------------
  53. *
  54. * Nios II processors generate exceptions for unimplemented instructions.
  55. * The routines below emulate these instructions. Depending on the
  56. * processor core, the only instructions that might need to be emulated
  57. * are div, divu, mul, muli, mulxss, mulxsu, and mulxuu.
  58. *
  59. * The emulations match the instructions, except for the following
  60. * limitations:
  61. *
  62. * 1) The emulation routines do not emulate the use of the exception
  63. * temporary register (et) as a source operand because the exception
  64. * handler already has modified it.
  65. *
  66. * 2) The routines do not emulate the use of the stack pointer (sp) or
  67. * the exception return address register (ea) as a destination because
  68. * modifying these registers crashes the exception handler or the
  69. * interrupted routine.
  70. *
  71. * Detailed Design
  72. * ---------------
  73. *
  74. * The emulation routines expect the contents of integer registers r0-r31
  75. * to be on the stack at addresses sp, 4(sp), 8(sp), ... 124(sp). The
  76. * routines retrieve source operands from the stack and modify the
  77. * destination register's value on the stack prior to the end of the
  78. * exception handler. Then all registers except the destination register
  79. * are restored to their previous values.
  80. *
  81. * The instruction that causes the exception is found at address -4(ea).
  82. * The instruction's OP and OPX fields identify the operation to be
  83. * performed.
  84. *
  85. * One instruction, muli, is an I-type instruction that is identified by
  86. * an OP field of 0x24.
  87. *
  88. * muli AAAAA,BBBBB,IIIIIIIIIIIIIIII,-0x24-
  89. * 27 22 6 0 <-- LSB of field
  90. *
  91. * The remaining emulated instructions are R-type and have an OP field
  92. * of 0x3a. Their OPX fields identify them.
  93. *
  94. * R-type AAAAA,BBBBB,CCCCC,XXXXXX,NNNNN,-0x3a-
  95. * 27 22 17 11 6 0 <-- LSB of field
  96. *
  97. *
  98. * Opcode Encoding. muli is identified by its OP value. Then OPX & 0x02
  99. * is used to differentiate between the division opcodes and the
  100. * remaining multiplication opcodes.
  101. *
  102. * Instruction OP OPX OPX & 0x02
  103. * ----------- ---- ---- ----------
  104. * muli 0x24
  105. * divu 0x3a 0x24 0
  106. * div 0x3a 0x25 0
  107. * mul 0x3a 0x27 != 0
  108. * mulxuu 0x3a 0x07 != 0
  109. * mulxsu 0x3a 0x17 != 0
  110. * mulxss 0x3a 0x1f != 0
  111. */
  112. /*
  113. * Save everything on the stack to make it easy for the emulation
  114. * routines to retrieve the source register operands.
  115. */
  116. addi sp, sp, -128
  117. stw zero, 0(sp) /* Save zero on stack to avoid special case for r0. */
  118. stw r1, 4(sp)
  119. stw r2, 8(sp)
  120. stw r3, 12(sp)
  121. stw r4, 16(sp)
  122. stw r5, 20(sp)
  123. stw r6, 24(sp)
  124. stw r7, 28(sp)
  125. stw r8, 32(sp)
  126. stw r9, 36(sp)
  127. stw r10, 40(sp)
  128. stw r11, 44(sp)
  129. stw r12, 48(sp)
  130. stw r13, 52(sp)
  131. stw r14, 56(sp)
  132. stw r15, 60(sp)
  133. stw r16, 64(sp)
  134. stw r17, 68(sp)
  135. stw r18, 72(sp)
  136. stw r19, 76(sp)
  137. stw r20, 80(sp)
  138. stw r21, 84(sp)
  139. stw r22, 88(sp)
  140. stw r23, 92(sp)
  141. /* Don't bother to save et. It's already been changed. */
  142. rdctl r5, estatus
  143. stw r5, 100(sp)
  144. stw gp, 104(sp)
  145. stw et, 108(sp) /* et contains previous sp value. */
  146. stw fp, 112(sp)
  147. stw ea, 116(sp)
  148. stw ra, 120(sp)
  149. /*
  150. * Split the instruction into its fields. We need 4*A, 4*B, and 4*C as
  151. * offsets to the stack pointer for access to the stored register values.
  152. */
  153. ldw r2,-4(ea) /* r2 = AAAAA,BBBBB,IIIIIIIIIIIIIIII,PPPPPP */
  154. roli r3, r2, 7 /* r3 = BBB,IIIIIIIIIIIIIIII,PPPPPP,AAAAA,BB */
  155. roli r4, r3, 3 /* r4 = IIIIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB */
  156. roli r5, r4, 2 /* r5 = IIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB,II */
  157. srai r4, r4, 16 /* r4 = (sign-extended) IMM16 */
  158. roli r6, r5, 5 /* r6 = XXXX,NNNNN,PPPPPP,AAAAA,BBBBB,CCCCC,XX */
  159. andi r2, r2, 0x3f /* r2 = 00000000000000000000000000,PPPPPP */
  160. andi r3, r3, 0x7c /* r3 = 0000000000000000000000000,AAAAA,00 */
  161. andi r5, r5, 0x7c /* r5 = 0000000000000000000000000,BBBBB,00 */
  162. andi r6, r6, 0x7c /* r6 = 0000000000000000000000000,CCCCC,00 */
  163. /* Now
  164. * r2 = OP
  165. * r3 = 4*A
  166. * r4 = IMM16 (sign extended)
  167. * r5 = 4*B
  168. * r6 = 4*C
  169. */
  170. /*
  171. * Get the operands.
  172. *
  173. * It is necessary to check for muli because it uses an I-type
  174. * instruction format, while the other instructions are have an R-type
  175. * format.
  176. *
  177. * Prepare for either multiplication or division loop.
  178. * They both loop 32 times.
  179. */
  180. movi r14, 32
  181. add r3, r3, sp /* r3 = address of A-operand. */
  182. ldw r3, 0(r3) /* r3 = A-operand. */
  183. movi r7, 0x24 /* muli opcode (I-type instruction format) */
  184. beq r2, r7, mul_immed /* muli doesn't use the B register as a source */
  185. add r5, r5, sp /* r5 = address of B-operand. */
  186. ldw r5, 0(r5) /* r5 = B-operand. */
  187. /* r4 = SSSSSSSSSSSSSSSS,-----IMM16------ */
  188. /* IMM16 not needed, align OPX portion */
  189. /* r4 = SSSSSSSSSSSSSSSS,CCCCC,-OPX--,00000 */
  190. srli r4, r4, 5 /* r4 = 00000,SSSSSSSSSSSSSSSS,CCCCC,-OPX-- */
  191. andi r4, r4, 0x3f /* r4 = 00000000000000000000000000,-OPX-- */
  192. /* Now
  193. * r2 = OP
  194. * r3 = src1
  195. * r5 = src2
  196. * r4 = OPX (no longer can be muli)
  197. * r6 = 4*C
  198. */
  199. /*
  200. * Multiply or Divide?
  201. */
  202. andi r7, r4, 0x02 /* For R-type multiply instructions,
  203. OPX & 0x02 != 0 */
  204. bne r7, zero, multiply
  205. /* DIVISION
  206. *
  207. * Divide an unsigned dividend by an unsigned divisor using
  208. * a shift-and-subtract algorithm. The example below shows
  209. * 43 div 7 = 6 for 8-bit integers. This classic algorithm uses a
  210. * single register to store both the dividend and the quotient,
  211. * allowing both values to be shifted with a single instruction.
  212. *
  213. * remainder dividend:quotient
  214. * --------- -----------------
  215. * initialize 00000000 00101011:
  216. * shift 00000000 0101011:_
  217. * remainder >= divisor? no 00000000 0101011:0
  218. * shift 00000000 101011:0_
  219. * remainder >= divisor? no 00000000 101011:00
  220. * shift 00000001 01011:00_
  221. * remainder >= divisor? no 00000001 01011:000
  222. * shift 00000010 1011:000_
  223. * remainder >= divisor? no 00000010 1011:0000
  224. * shift 00000101 011:0000_
  225. * remainder >= divisor? no 00000101 011:00000
  226. * shift 00001010 11:00000_
  227. * remainder >= divisor? yes 00001010 11:000001
  228. * remainder -= divisor - 00000111
  229. * ----------
  230. * 00000011 11:000001
  231. * shift 00000111 1:000001_
  232. * remainder >= divisor? yes 00000111 1:0000011
  233. * remainder -= divisor - 00000111
  234. * ----------
  235. * 00000000 1:0000011
  236. * shift 00000001 :0000011_
  237. * remainder >= divisor? no 00000001 :00000110
  238. *
  239. * The quotient is 00000110.
  240. */
  241. divide:
  242. /*
  243. * Prepare for division by assuming the result
  244. * is unsigned, and storing its "sign" as 0.
  245. */
  246. movi r17, 0
  247. /* Which division opcode? */
  248. xori r7, r4, 0x25 /* OPX of div */
  249. bne r7, zero, unsigned_division
  250. /*
  251. * OPX is div. Determine and store the sign of the quotient.
  252. * Then take the absolute value of both operands.
  253. */
  254. xor r17, r3, r5 /* MSB contains sign of quotient */
  255. bge r3,zero,dividend_is_nonnegative
  256. sub r3, zero, r3 /* -r3 */
  257. dividend_is_nonnegative:
  258. bge r5, zero, divisor_is_nonnegative
  259. sub r5, zero, r5 /* -r5 */
  260. divisor_is_nonnegative:
  261. unsigned_division:
  262. /* Initialize the unsigned-division loop. */
  263. movi r13, 0 /* remainder = 0 */
  264. /* Now
  265. * r3 = dividend : quotient
  266. * r4 = 0x25 for div, 0x24 for divu
  267. * r5 = divisor
  268. * r13 = remainder
  269. * r14 = loop counter (already initialized to 32)
  270. * r17 = MSB contains sign of quotient
  271. */
  272. /*
  273. * for (count = 32; count > 0; --count)
  274. * {
  275. */
  276. divide_loop:
  277. /*
  278. * Division:
  279. *
  280. * (remainder:dividend:quotient) <<= 1;
  281. */
  282. slli r13, r13, 1
  283. cmplt r7, r3, zero /* r7 = MSB of r3 */
  284. or r13, r13, r7
  285. slli r3, r3, 1
  286. /*
  287. * if (remainder >= divisor)
  288. * {
  289. * set LSB of quotient
  290. * remainder -= divisor;
  291. * }
  292. */
  293. bltu r13, r5, div_skip
  294. ori r3, r3, 1
  295. sub r13, r13, r5
  296. div_skip:
  297. /*
  298. * }
  299. */
  300. subi r14, r14, 1
  301. bne r14, zero, divide_loop
  302. /* Now
  303. * r3 = quotient
  304. * r4 = 0x25 for div, 0x24 for divu
  305. * r6 = 4*C
  306. * r17 = MSB contains sign of quotient
  307. */
  308. /*
  309. * Conditionally negate signed quotient. If quotient is unsigned,
  310. * the sign already is initialized to 0.
  311. */
  312. bge r17, zero, quotient_is_nonnegative
  313. sub r3, zero, r3 /* -r3 */
  314. quotient_is_nonnegative:
  315. /*
  316. * Final quotient is in r3.
  317. */
  318. add r6, r6, sp
  319. stw r3, 0(r6) /* write quotient to stack */
  320. br restore_registers
  321. /* MULTIPLICATION
  322. *
  323. * A "product" is the number that one gets by summing a "multiplicand"
  324. * several times. The "multiplier" specifies the number of copies of the
  325. * multiplicand that are summed.
  326. *
  327. * Actual multiplication algorithms don't use repeated addition, however.
  328. * Shift-and-add algorithms get the same answer as repeated addition, and
  329. * they are faster. To compute the lower half of a product (pppp below)
  330. * one shifts the product left before adding in each of the partial
  331. * products (a * mmmm) through (d * mmmm).
  332. *
  333. * To compute the upper half of a product (PPPP below), one adds in the
  334. * partial products (d * mmmm) through (a * mmmm), each time following
  335. * the add by a right shift of the product.
  336. *
  337. * mmmm
  338. * * abcd
  339. * ------
  340. * #### = d * mmmm
  341. * #### = c * mmmm
  342. * #### = b * mmmm
  343. * #### = a * mmmm
  344. * --------
  345. * PPPPpppp
  346. *
  347. * The example above shows 4 partial products. Computing actual Nios II
  348. * products requires 32 partials.
  349. *
  350. * It is possible to compute the result of mulxsu from the result of
  351. * mulxuu because the only difference between the results of these two
  352. * opcodes is the value of the partial product associated with the sign
  353. * bit of rA.
  354. *
  355. * mulxsu = mulxuu - (rA < 0) ? rB : 0;
  356. *
  357. * It is possible to compute the result of mulxss from the result of
  358. * mulxsu because the only difference between the results of these two
  359. * opcodes is the value of the partial product associated with the sign
  360. * bit of rB.
  361. *
  362. * mulxss = mulxsu - (rB < 0) ? rA : 0;
  363. *
  364. */
  365. mul_immed:
  366. /* Opcode is muli. Change it into mul for remainder of algorithm. */
  367. mov r6, r5 /* Field B is dest register, not field C. */
  368. mov r5, r4 /* Field IMM16 is src2, not field B. */
  369. movi r4, 0x27 /* OPX of mul is 0x27 */
  370. multiply:
  371. /* Initialize the multiplication loop. */
  372. movi r9, 0 /* mul_product = 0 */
  373. movi r10, 0 /* mulxuu_product = 0 */
  374. mov r11, r5 /* save original multiplier for mulxsu and mulxss */
  375. mov r12, r5 /* mulxuu_multiplier (will be shifted) */
  376. movi r16, 1 /* used to create "rori B,A,1" from "ror B,A,r16" */
  377. /* Now
  378. * r3 = multiplicand
  379. * r5 = mul_multiplier
  380. * r6 = 4 * dest_register (used later as offset to sp)
  381. * r7 = temp
  382. * r9 = mul_product
  383. * r10 = mulxuu_product
  384. * r11 = original multiplier
  385. * r12 = mulxuu_multiplier
  386. * r14 = loop counter (already initialized)
  387. * r16 = 1
  388. */
  389. /*
  390. * for (count = 32; count > 0; --count)
  391. * {
  392. */
  393. multiply_loop:
  394. /*
  395. * mul_product <<= 1;
  396. * lsb = multiplier & 1;
  397. */
  398. slli r9, r9, 1
  399. andi r7, r12, 1
  400. /*
  401. * if (lsb == 1)
  402. * {
  403. * mulxuu_product += multiplicand;
  404. * }
  405. */
  406. beq r7, zero, mulx_skip
  407. add r10, r10, r3
  408. cmpltu r7, r10, r3 /* Save the carry from the MSB of mulxuu_product. */
  409. ror r7, r7, r16 /* r7 = 0x80000000 on carry, or else 0x00000000 */
  410. mulx_skip:
  411. /*
  412. * if (MSB of mul_multiplier == 1)
  413. * {
  414. * mul_product += multiplicand;
  415. * }
  416. */
  417. bge r5, zero, mul_skip
  418. add r9, r9, r3
  419. mul_skip:
  420. /*
  421. * mulxuu_product >>= 1; logical shift
  422. * mul_multiplier <<= 1; done with MSB
  423. * mulx_multiplier >>= 1; done with LSB
  424. */
  425. srli r10, r10, 1
  426. or r10, r10, r7 /* OR in the saved carry bit. */
  427. slli r5, r5, 1
  428. srli r12, r12, 1
  429. /*
  430. * }
  431. */
  432. subi r14, r14, 1
  433. bne r14, zero, multiply_loop
  434. /*
  435. * Multiply emulation loop done.
  436. */
  437. /* Now
  438. * r3 = multiplicand
  439. * r4 = OPX
  440. * r6 = 4 * dest_register (used later as offset to sp)
  441. * r7 = temp
  442. * r9 = mul_product
  443. * r10 = mulxuu_product
  444. * r11 = original multiplier
  445. */
  446. /* Calculate address for result from 4 * dest_register */
  447. add r6, r6, sp
  448. /*
  449. * Select/compute the result based on OPX.
  450. */
  451. /* OPX == mul? Then store. */
  452. xori r7, r4, 0x27
  453. beq r7, zero, store_product
  454. /* It's one of the mulx.. opcodes. Move over the result. */
  455. mov r9, r10
  456. /* OPX == mulxuu? Then store. */
  457. xori r7, r4, 0x07
  458. beq r7, zero, store_product
  459. /* Compute mulxsu
  460. *
  461. * mulxsu = mulxuu - (rA < 0) ? rB : 0;
  462. */
  463. bge r3, zero, mulxsu_skip
  464. sub r9, r9, r11
  465. mulxsu_skip:
  466. /* OPX == mulxsu? Then store. */
  467. xori r7, r4, 0x17
  468. beq r7, zero, store_product
  469. /* Compute mulxss
  470. *
  471. * mulxss = mulxsu - (rB < 0) ? rA : 0;
  472. */
  473. bge r11,zero,mulxss_skip
  474. sub r9, r9, r3
  475. mulxss_skip:
  476. /* At this point, assume that OPX is mulxss, so store*/
  477. store_product:
  478. stw r9, 0(r6)
  479. restore_registers:
  480. /* No need to restore r0. */
  481. ldw r5, 100(sp)
  482. wrctl estatus, r5
  483. ldw r1, 4(sp)
  484. ldw r2, 8(sp)
  485. ldw r3, 12(sp)
  486. ldw r4, 16(sp)
  487. ldw r5, 20(sp)
  488. ldw r6, 24(sp)
  489. ldw r7, 28(sp)
  490. ldw r8, 32(sp)
  491. ldw r9, 36(sp)
  492. ldw r10, 40(sp)
  493. ldw r11, 44(sp)
  494. ldw r12, 48(sp)
  495. ldw r13, 52(sp)
  496. ldw r14, 56(sp)
  497. ldw r15, 60(sp)
  498. ldw r16, 64(sp)
  499. ldw r17, 68(sp)
  500. ldw r18, 72(sp)
  501. ldw r19, 76(sp)
  502. ldw r20, 80(sp)
  503. ldw r21, 84(sp)
  504. ldw r22, 88(sp)
  505. ldw r23, 92(sp)
  506. /* Does not need to restore et */
  507. ldw gp, 104(sp)
  508. ldw fp, 112(sp)
  509. ldw ea, 116(sp)
  510. ldw ra, 120(sp)
  511. ldw sp, 108(sp) /* last restore sp */
  512. eret
  513. .set at
  514. .set break