bamboo.dts 7.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300
  1. /*
  2. * Device Tree Source for AMCC Bamboo
  3. *
  4. * Copyright (c) 2006, 2007 IBM Corp.
  5. * Josh Boyer <jwboyer@linux.vnet.ibm.com>
  6. *
  7. * FIXME: Draft only!
  8. *
  9. * This file is licensed under the terms of the GNU General Public
  10. * License version 2. This program is licensed "as is" without
  11. * any warranty of any kind, whether express or implied.
  12. */
  13. /dts-v1/;
  14. / {
  15. #address-cells = <2>;
  16. #size-cells = <1>;
  17. model = "amcc,bamboo";
  18. compatible = "amcc,bamboo";
  19. dcr-parent = <&{/cpus/cpu@0}>;
  20. aliases {
  21. ethernet0 = &EMAC0;
  22. ethernet1 = &EMAC1;
  23. serial0 = &UART0;
  24. serial1 = &UART1;
  25. serial2 = &UART2;
  26. serial3 = &UART3;
  27. };
  28. cpus {
  29. #address-cells = <1>;
  30. #size-cells = <0>;
  31. cpu@0 {
  32. device_type = "cpu";
  33. model = "PowerPC,440EP";
  34. reg = <0x00000000>;
  35. clock-frequency = <0>; /* Filled in by zImage */
  36. timebase-frequency = <0>; /* Filled in by zImage */
  37. i-cache-line-size = <32>;
  38. d-cache-line-size = <32>;
  39. i-cache-size = <32768>;
  40. d-cache-size = <32768>;
  41. dcr-controller;
  42. dcr-access-method = "native";
  43. };
  44. };
  45. memory {
  46. device_type = "memory";
  47. reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */
  48. };
  49. UIC0: interrupt-controller0 {
  50. compatible = "ibm,uic-440ep","ibm,uic";
  51. interrupt-controller;
  52. cell-index = <0>;
  53. dcr-reg = <0x0c0 0x009>;
  54. #address-cells = <0>;
  55. #size-cells = <0>;
  56. #interrupt-cells = <2>;
  57. };
  58. UIC1: interrupt-controller1 {
  59. compatible = "ibm,uic-440ep","ibm,uic";
  60. interrupt-controller;
  61. cell-index = <1>;
  62. dcr-reg = <0x0d0 0x009>;
  63. #address-cells = <0>;
  64. #size-cells = <0>;
  65. #interrupt-cells = <2>;
  66. interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
  67. interrupt-parent = <&UIC0>;
  68. };
  69. SDR0: sdr {
  70. compatible = "ibm,sdr-440ep";
  71. dcr-reg = <0x00e 0x002>;
  72. };
  73. CPR0: cpr {
  74. compatible = "ibm,cpr-440ep";
  75. dcr-reg = <0x00c 0x002>;
  76. };
  77. plb {
  78. compatible = "ibm,plb-440ep", "ibm,plb-440gp", "ibm,plb4";
  79. #address-cells = <2>;
  80. #size-cells = <1>;
  81. ranges;
  82. clock-frequency = <0>; /* Filled in by zImage */
  83. SDRAM0: sdram {
  84. compatible = "ibm,sdram-440ep", "ibm,sdram-405gp";
  85. dcr-reg = <0x010 0x002>;
  86. };
  87. DMA0: dma {
  88. compatible = "ibm,dma-440ep", "ibm,dma-440gp";
  89. dcr-reg = <0x100 0x027>;
  90. };
  91. MAL0: mcmal {
  92. compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal";
  93. dcr-reg = <0x180 0x062>;
  94. num-tx-chans = <4>;
  95. num-rx-chans = <2>;
  96. interrupt-parent = <&MAL0>;
  97. interrupts = <0x0 0x1 0x2 0x3 0x4>;
  98. #interrupt-cells = <1>;
  99. #address-cells = <0>;
  100. #size-cells = <0>;
  101. interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
  102. /*RXEOB*/ 0x1 &UIC0 0xb 0x4
  103. /*SERR*/ 0x2 &UIC1 0x0 0x4
  104. /*TXDE*/ 0x3 &UIC1 0x1 0x4
  105. /*RXDE*/ 0x4 &UIC1 0x2 0x4>;
  106. };
  107. POB0: opb {
  108. compatible = "ibm,opb-440ep", "ibm,opb-440gp", "ibm,opb";
  109. #address-cells = <1>;
  110. #size-cells = <1>;
  111. /* Bamboo is oddball in the 44x world and doesn't use the ERPN
  112. * bits.
  113. */
  114. ranges = <0x00000000 0x00000000 0x00000000 0x80000000
  115. 0x80000000 0x00000000 0x80000000 0x80000000>;
  116. interrupt-parent = <&UIC1>;
  117. interrupts = <0x7 0x4>;
  118. clock-frequency = <0>; /* Filled in by zImage */
  119. EBC0: ebc {
  120. compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc";
  121. dcr-reg = <0x012 0x002>;
  122. #address-cells = <2>;
  123. #size-cells = <1>;
  124. clock-frequency = <0>; /* Filled in by zImage */
  125. interrupts = <0x5 0x1>;
  126. interrupt-parent = <&UIC1>;
  127. };
  128. UART0: serial@ef600300 {
  129. device_type = "serial";
  130. compatible = "ns16550";
  131. reg = <0xef600300 0x00000008>;
  132. virtual-reg = <0xef600300>;
  133. clock-frequency = <0>; /* Filled in by zImage */
  134. current-speed = <115200>;
  135. interrupt-parent = <&UIC0>;
  136. interrupts = <0x0 0x4>;
  137. };
  138. UART1: serial@ef600400 {
  139. device_type = "serial";
  140. compatible = "ns16550";
  141. reg = <0xef600400 0x00000008>;
  142. virtual-reg = <0xef600400>;
  143. clock-frequency = <0>;
  144. current-speed = <0>;
  145. interrupt-parent = <&UIC0>;
  146. interrupts = <0x1 0x4>;
  147. };
  148. UART2: serial@ef600500 {
  149. device_type = "serial";
  150. compatible = "ns16550";
  151. reg = <0xef600500 0x00000008>;
  152. virtual-reg = <0xef600500>;
  153. clock-frequency = <0>;
  154. current-speed = <0>;
  155. interrupt-parent = <&UIC0>;
  156. interrupts = <0x3 0x4>;
  157. };
  158. UART3: serial@ef600600 {
  159. device_type = "serial";
  160. compatible = "ns16550";
  161. reg = <0xef600600 0x00000008>;
  162. virtual-reg = <0xef600600>;
  163. clock-frequency = <0>;
  164. current-speed = <0>;
  165. interrupt-parent = <&UIC0>;
  166. interrupts = <0x4 0x4>;
  167. };
  168. IIC0: i2c@ef600700 {
  169. compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
  170. reg = <0xef600700 0x00000014>;
  171. interrupt-parent = <&UIC0>;
  172. interrupts = <0x2 0x4>;
  173. };
  174. IIC1: i2c@ef600800 {
  175. compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
  176. reg = <0xef600800 0x00000014>;
  177. interrupt-parent = <&UIC0>;
  178. interrupts = <0x7 0x4>;
  179. };
  180. ZMII0: emac-zmii@ef600d00 {
  181. compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii";
  182. reg = <0xef600d00 0x0000000c>;
  183. };
  184. EMAC0: ethernet@ef600e00 {
  185. device_type = "network";
  186. compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
  187. interrupt-parent = <&UIC1>;
  188. interrupts = <0x1c 0x4 0x1d 0x4>;
  189. reg = <0xef600e00 0x00000070>;
  190. local-mac-address = [000000000000];
  191. mal-device = <&MAL0>;
  192. mal-tx-channel = <0 1>;
  193. mal-rx-channel = <0>;
  194. cell-index = <0>;
  195. max-frame-size = <1500>;
  196. rx-fifo-size = <4096>;
  197. tx-fifo-size = <2048>;
  198. phy-mode = "rmii";
  199. phy-map = <0x00000000>;
  200. zmii-device = <&ZMII0>;
  201. zmii-channel = <0>;
  202. };
  203. EMAC1: ethernet@ef600f00 {
  204. device_type = "network";
  205. compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
  206. interrupt-parent = <&UIC1>;
  207. interrupts = <0x1e 0x4 0x1f 0x4>;
  208. reg = <0xef600f00 0x00000070>;
  209. local-mac-address = [000000000000];
  210. mal-device = <&MAL0>;
  211. mal-tx-channel = <2 3>;
  212. mal-rx-channel = <1>;
  213. cell-index = <1>;
  214. max-frame-size = <1500>;
  215. rx-fifo-size = <4096>;
  216. tx-fifo-size = <2048>;
  217. phy-mode = "rmii";
  218. phy-map = <0x00000000>;
  219. zmii-device = <&ZMII0>;
  220. zmii-channel = <1>;
  221. };
  222. usb@ef601000 {
  223. compatible = "ohci-be";
  224. reg = <0xef601000 0x00000080>;
  225. interrupts = <0x8 0x1 0x9 0x1>;
  226. interrupt-parent = < &UIC1 >;
  227. };
  228. };
  229. PCI0: pci@ec000000 {
  230. device_type = "pci";
  231. #interrupt-cells = <1>;
  232. #size-cells = <2>;
  233. #address-cells = <3>;
  234. compatible = "ibm,plb440ep-pci", "ibm,plb-pci";
  235. primary;
  236. reg = <0x00000000 0xeec00000 0x00000008 /* Config space access */
  237. 0x00000000 0xeed00000 0x00000004 /* IACK */
  238. 0x00000000 0xeed00000 0x00000004 /* Special cycle */
  239. 0x00000000 0xef400000 0x00000040>; /* Internal registers */
  240. /* Outbound ranges, one memory and one IO,
  241. * later cannot be changed. Chip supports a second
  242. * IO range but we don't use it for now
  243. */
  244. ranges = <0x02000000 0x00000000 0xa0000000 0x00000000 0xa0000000 0x00000000 0x40000000
  245. 0x02000000 0x00000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00100000
  246. 0x01000000 0x00000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
  247. /* Inbound 2GB range starting at 0 */
  248. dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
  249. /* Bamboo has all 4 IRQ pins tied together per slot */
  250. interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
  251. interrupt-map = <
  252. /* IDSEL 1 */
  253. 0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8
  254. /* IDSEL 2 */
  255. 0x1000 0x0 0x0 0x0 &UIC0 0x1b 0x8
  256. /* IDSEL 3 */
  257. 0x1800 0x0 0x0 0x0 &UIC0 0x1a 0x8
  258. /* IDSEL 4 */
  259. 0x2000 0x0 0x0 0x0 &UIC0 0x19 0x8
  260. >;
  261. };
  262. };
  263. chosen {
  264. linux,stdout-path = "/plb/opb/serial@ef600300";
  265. };
  266. };