mpc7448hpc2.dts 4.4 KB

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  1. /*
  2. * MPC7448HPC2 (Taiga) board Device Tree Source
  3. *
  4. * Copyright 2006, 2008 Freescale Semiconductor Inc.
  5. * 2006 Roy Zang <Roy Zang at freescale.com>.
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the
  9. * Free Software Foundation; either version 2 of the License, or (at your
  10. * option) any later version.
  11. */
  12. /dts-v1/;
  13. / {
  14. model = "mpc7448hpc2";
  15. compatible = "mpc74xx";
  16. #address-cells = <1>;
  17. #size-cells = <1>;
  18. aliases {
  19. ethernet0 = &enet0;
  20. ethernet1 = &enet1;
  21. serial0 = &serial0;
  22. serial1 = &serial1;
  23. pci0 = &pci0;
  24. };
  25. cpus {
  26. #address-cells = <1>;
  27. #size-cells =<0>;
  28. PowerPC,7448@0 {
  29. device_type = "cpu";
  30. reg = <0x0>;
  31. d-cache-line-size = <32>; // 32 bytes
  32. i-cache-line-size = <32>; // 32 bytes
  33. d-cache-size = <0x8000>; // L1, 32K bytes
  34. i-cache-size = <0x8000>; // L1, 32K bytes
  35. timebase-frequency = <0>; // 33 MHz, from uboot
  36. clock-frequency = <0>; // From U-Boot
  37. bus-frequency = <0>; // From U-Boot
  38. };
  39. };
  40. memory {
  41. device_type = "memory";
  42. reg = <0x0 0x20000000 // DDR2 512M at 0
  43. >;
  44. };
  45. tsi108@c0000000 {
  46. #address-cells = <1>;
  47. #size-cells = <1>;
  48. device_type = "tsi-bridge";
  49. ranges = <0x0 0xc0000000 0x10000>;
  50. reg = <0xc0000000 0x10000>;
  51. bus-frequency = <0>;
  52. i2c@7000 {
  53. interrupt-parent = <&mpic>;
  54. interrupts = <14 0>;
  55. reg = <0x7000 0x400>;
  56. device_type = "i2c";
  57. compatible = "tsi108-i2c";
  58. };
  59. MDIO: mdio@6000 {
  60. compatible = "tsi108-mdio";
  61. reg = <0x6000 0x50>;
  62. #address-cells = <1>;
  63. #size-cells = <0>;
  64. phy8: ethernet-phy@8 {
  65. interrupt-parent = <&mpic>;
  66. interrupts = <2 1>;
  67. reg = <0x8>;
  68. };
  69. phy9: ethernet-phy@9 {
  70. interrupt-parent = <&mpic>;
  71. interrupts = <2 1>;
  72. reg = <0x9>;
  73. };
  74. };
  75. enet0: ethernet@6200 {
  76. linux,network-index = <0>;
  77. #size-cells = <0>;
  78. device_type = "network";
  79. compatible = "tsi108-ethernet";
  80. reg = <0x6000 0x200>;
  81. address = [ 00 06 D2 00 00 01 ];
  82. interrupts = <16 2>;
  83. interrupt-parent = <&mpic>;
  84. mdio-handle = <&MDIO>;
  85. phy-handle = <&phy8>;
  86. };
  87. enet1: ethernet@6600 {
  88. linux,network-index = <1>;
  89. #address-cells = <1>;
  90. #size-cells = <0>;
  91. device_type = "network";
  92. compatible = "tsi108-ethernet";
  93. reg = <0x6400 0x200>;
  94. address = [ 00 06 D2 00 00 02 ];
  95. interrupts = <17 2>;
  96. interrupt-parent = <&mpic>;
  97. mdio-handle = <&MDIO>;
  98. phy-handle = <&phy9>;
  99. };
  100. serial0: serial@7808 {
  101. device_type = "serial";
  102. compatible = "ns16550";
  103. reg = <0x7808 0x200>;
  104. clock-frequency = <1064000000>;
  105. interrupts = <12 0>;
  106. interrupt-parent = <&mpic>;
  107. };
  108. serial1: serial@7c08 {
  109. device_type = "serial";
  110. compatible = "ns16550";
  111. reg = <0x7c08 0x200>;
  112. clock-frequency = <1064000000>;
  113. interrupts = <13 0>;
  114. interrupt-parent = <&mpic>;
  115. };
  116. mpic: pic@7400 {
  117. interrupt-controller;
  118. #address-cells = <0>;
  119. #interrupt-cells = <2>;
  120. reg = <0x7400 0x400>;
  121. compatible = "chrp,open-pic";
  122. device_type = "open-pic";
  123. };
  124. pci0: pci@1000 {
  125. compatible = "tsi108-pci";
  126. device_type = "pci";
  127. #interrupt-cells = <1>;
  128. #size-cells = <2>;
  129. #address-cells = <3>;
  130. reg = <0x1000 0x1000>;
  131. bus-range = <0 0>;
  132. ranges = <0x2000000 0x0 0xe0000000 0xe0000000 0x0 0x1a000000
  133. 0x1000000 0x0 0x0 0xfa000000 0x0 0x10000>;
  134. clock-frequency = <133333332>;
  135. interrupt-parent = <&mpic>;
  136. interrupts = <23 2>;
  137. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  138. interrupt-map = <
  139. /* IDSEL 0x11 */
  140. 0x800 0x0 0x0 0x1 &RT0 0x24 0x0
  141. 0x800 0x0 0x0 0x2 &RT0 0x25 0x0
  142. 0x800 0x0 0x0 0x3 &RT0 0x26 0x0
  143. 0x800 0x0 0x0 0x4 &RT0 0x27 0x0
  144. /* IDSEL 0x12 */
  145. 0x1000 0x0 0x0 0x1 &RT0 0x25 0x0
  146. 0x1000 0x0 0x0 0x2 &RT0 0x26 0x0
  147. 0x1000 0x0 0x0 0x3 &RT0 0x27 0x0
  148. 0x1000 0x0 0x0 0x4 &RT0 0x24 0x0
  149. /* IDSEL 0x13 */
  150. 0x1800 0x0 0x0 0x1 &RT0 0x26 0x0
  151. 0x1800 0x0 0x0 0x2 &RT0 0x27 0x0
  152. 0x1800 0x0 0x0 0x3 &RT0 0x24 0x0
  153. 0x1800 0x0 0x0 0x4 &RT0 0x25 0x0
  154. /* IDSEL 0x14 */
  155. 0x2000 0x0 0x0 0x1 &RT0 0x27 0x0
  156. 0x2000 0x0 0x0 0x2 &RT0 0x24 0x0
  157. 0x2000 0x0 0x0 0x3 &RT0 0x25 0x0
  158. 0x2000 0x0 0x0 0x4 &RT0 0x26 0x0
  159. >;
  160. RT0: router@1180 {
  161. clock-frequency = <0>;
  162. interrupt-controller;
  163. device_type = "pic-router";
  164. #address-cells = <0>;
  165. #interrupt-cells = <2>;
  166. big-endian;
  167. interrupts = <23 2>;
  168. interrupt-parent = <&mpic>;
  169. };
  170. };
  171. };
  172. };