mpc8349emitx.dts 9.5 KB

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  1. /*
  2. * MPC8349E-mITX Device Tree Source
  3. *
  4. * Copyright 2006 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /dts-v1/;
  12. / {
  13. model = "MPC8349EMITX";
  14. compatible = "MPC8349EMITX", "MPC834xMITX", "MPC83xxMITX";
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. aliases {
  18. ethernet0 = &enet0;
  19. ethernet1 = &enet1;
  20. serial0 = &serial0;
  21. serial1 = &serial1;
  22. pci0 = &pci0;
  23. pci1 = &pci1;
  24. };
  25. cpus {
  26. #address-cells = <1>;
  27. #size-cells = <0>;
  28. PowerPC,8349@0 {
  29. device_type = "cpu";
  30. reg = <0x0>;
  31. d-cache-line-size = <32>;
  32. i-cache-line-size = <32>;
  33. d-cache-size = <32768>;
  34. i-cache-size = <32768>;
  35. timebase-frequency = <0>; // from bootloader
  36. bus-frequency = <0>; // from bootloader
  37. clock-frequency = <0>; // from bootloader
  38. };
  39. };
  40. memory {
  41. device_type = "memory";
  42. reg = <0x00000000 0x10000000>;
  43. };
  44. soc8349@e0000000 {
  45. #address-cells = <1>;
  46. #size-cells = <1>;
  47. device_type = "soc";
  48. compatible = "simple-bus";
  49. ranges = <0x0 0xe0000000 0x00100000>;
  50. reg = <0xe0000000 0x00000200>;
  51. bus-frequency = <0>; // from bootloader
  52. wdt@200 {
  53. device_type = "watchdog";
  54. compatible = "mpc83xx_wdt";
  55. reg = <0x200 0x100>;
  56. };
  57. gpio1: gpio-controller@c00 {
  58. #gpio-cells = <2>;
  59. compatible = "fsl,mpc8349-gpio";
  60. reg = <0xc00 0x100>;
  61. interrupts = <74 0x8>;
  62. interrupt-parent = <&ipic>;
  63. gpio-controller;
  64. };
  65. gpio2: gpio-controller@d00 {
  66. #gpio-cells = <2>;
  67. compatible = "fsl,mpc8349-gpio";
  68. reg = <0xd00 0x100>;
  69. interrupts = <75 0x8>;
  70. interrupt-parent = <&ipic>;
  71. gpio-controller;
  72. };
  73. i2c@3000 {
  74. #address-cells = <1>;
  75. #size-cells = <0>;
  76. cell-index = <0>;
  77. compatible = "fsl-i2c";
  78. reg = <0x3000 0x100>;
  79. interrupts = <14 0x8>;
  80. interrupt-parent = <&ipic>;
  81. dfsrr;
  82. eeprom: at24@50 {
  83. compatible = "st-micro,24c256";
  84. reg = <0x50>;
  85. };
  86. };
  87. i2c@3100 {
  88. #address-cells = <1>;
  89. #size-cells = <0>;
  90. cell-index = <1>;
  91. compatible = "fsl-i2c";
  92. reg = <0x3100 0x100>;
  93. interrupts = <15 0x8>;
  94. interrupt-parent = <&ipic>;
  95. dfsrr;
  96. rtc@68 {
  97. compatible = "dallas,ds1339";
  98. reg = <0x68>;
  99. interrupts = <18 0x8>;
  100. interrupt-parent = <&ipic>;
  101. };
  102. pcf1: iexp@38 {
  103. #gpio-cells = <2>;
  104. compatible = "ti,pcf8574a";
  105. reg = <0x38>;
  106. gpio-controller;
  107. };
  108. pcf2: iexp@39 {
  109. #gpio-cells = <2>;
  110. compatible = "ti,pcf8574a";
  111. reg = <0x39>;
  112. gpio-controller;
  113. };
  114. spd: at24@51 {
  115. compatible = "at24,spd";
  116. reg = <0x51>;
  117. };
  118. mcu_pio: mcu@a {
  119. #gpio-cells = <2>;
  120. compatible = "fsl,mc9s08qg8-mpc8349emitx",
  121. "fsl,mcu-mpc8349emitx";
  122. reg = <0x0a>;
  123. gpio-controller;
  124. };
  125. };
  126. spi@7000 {
  127. cell-index = <0>;
  128. compatible = "fsl,spi";
  129. reg = <0x7000 0x1000>;
  130. interrupts = <16 0x8>;
  131. interrupt-parent = <&ipic>;
  132. mode = "cpu";
  133. };
  134. dma@82a8 {
  135. #address-cells = <1>;
  136. #size-cells = <1>;
  137. compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
  138. reg = <0x82a8 4>;
  139. ranges = <0 0x8100 0x1a8>;
  140. interrupt-parent = <&ipic>;
  141. interrupts = <71 8>;
  142. cell-index = <0>;
  143. dma-channel@0 {
  144. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  145. reg = <0 0x80>;
  146. cell-index = <0>;
  147. interrupt-parent = <&ipic>;
  148. interrupts = <71 8>;
  149. };
  150. dma-channel@80 {
  151. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  152. reg = <0x80 0x80>;
  153. cell-index = <1>;
  154. interrupt-parent = <&ipic>;
  155. interrupts = <71 8>;
  156. };
  157. dma-channel@100 {
  158. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  159. reg = <0x100 0x80>;
  160. cell-index = <2>;
  161. interrupt-parent = <&ipic>;
  162. interrupts = <71 8>;
  163. };
  164. dma-channel@180 {
  165. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  166. reg = <0x180 0x28>;
  167. cell-index = <3>;
  168. interrupt-parent = <&ipic>;
  169. interrupts = <71 8>;
  170. };
  171. };
  172. usb@22000 {
  173. compatible = "fsl-usb2-mph";
  174. reg = <0x22000 0x1000>;
  175. #address-cells = <1>;
  176. #size-cells = <0>;
  177. interrupt-parent = <&ipic>;
  178. interrupts = <39 0x8>;
  179. phy_type = "ulpi";
  180. port0;
  181. };
  182. usb@23000 {
  183. compatible = "fsl-usb2-dr";
  184. reg = <0x23000 0x1000>;
  185. #address-cells = <1>;
  186. #size-cells = <0>;
  187. interrupt-parent = <&ipic>;
  188. interrupts = <38 0x8>;
  189. dr_mode = "peripheral";
  190. phy_type = "ulpi";
  191. };
  192. enet0: ethernet@24000 {
  193. #address-cells = <1>;
  194. #size-cells = <1>;
  195. cell-index = <0>;
  196. device_type = "network";
  197. model = "TSEC";
  198. compatible = "gianfar";
  199. reg = <0x24000 0x1000>;
  200. ranges = <0x0 0x24000 0x1000>;
  201. local-mac-address = [ 00 00 00 00 00 00 ];
  202. interrupts = <32 0x8 33 0x8 34 0x8>;
  203. interrupt-parent = <&ipic>;
  204. tbi-handle = <&tbi0>;
  205. phy-handle = <&phy1c>;
  206. linux,network-index = <0>;
  207. mdio@520 {
  208. #address-cells = <1>;
  209. #size-cells = <0>;
  210. compatible = "fsl,gianfar-mdio";
  211. reg = <0x520 0x20>;
  212. /* Vitesse 8201 */
  213. phy1c: ethernet-phy@1c {
  214. interrupt-parent = <&ipic>;
  215. interrupts = <18 0x8>;
  216. reg = <0x1c>;
  217. };
  218. tbi0: tbi-phy@11 {
  219. reg = <0x11>;
  220. device_type = "tbi-phy";
  221. };
  222. };
  223. };
  224. enet1: ethernet@25000 {
  225. #address-cells = <1>;
  226. #size-cells = <1>;
  227. cell-index = <1>;
  228. device_type = "network";
  229. model = "TSEC";
  230. compatible = "gianfar";
  231. reg = <0x25000 0x1000>;
  232. ranges = <0x0 0x25000 0x1000>;
  233. local-mac-address = [ 00 00 00 00 00 00 ];
  234. interrupts = <35 0x8 36 0x8 37 0x8>;
  235. interrupt-parent = <&ipic>;
  236. /* Vitesse 7385 isn't on the MDIO bus */
  237. fixed-link = <1 1 1000 0 0>;
  238. linux,network-index = <1>;
  239. tbi-handle = <&tbi1>;
  240. mdio@520 {
  241. #address-cells = <1>;
  242. #size-cells = <0>;
  243. compatible = "fsl,gianfar-tbi";
  244. reg = <0x520 0x20>;
  245. tbi1: tbi-phy@11 {
  246. reg = <0x11>;
  247. device_type = "tbi-phy";
  248. };
  249. };
  250. };
  251. serial0: serial@4500 {
  252. cell-index = <0>;
  253. device_type = "serial";
  254. compatible = "fsl,ns16550", "ns16550";
  255. reg = <0x4500 0x100>;
  256. clock-frequency = <0>; // from bootloader
  257. interrupts = <9 0x8>;
  258. interrupt-parent = <&ipic>;
  259. };
  260. serial1: serial@4600 {
  261. cell-index = <1>;
  262. device_type = "serial";
  263. compatible = "fsl,ns16550", "ns16550";
  264. reg = <0x4600 0x100>;
  265. clock-frequency = <0>; // from bootloader
  266. interrupts = <10 0x8>;
  267. interrupt-parent = <&ipic>;
  268. };
  269. crypto@30000 {
  270. compatible = "fsl,sec2.0";
  271. reg = <0x30000 0x10000>;
  272. interrupts = <11 0x8>;
  273. interrupt-parent = <&ipic>;
  274. fsl,num-channels = <4>;
  275. fsl,channel-fifo-len = <24>;
  276. fsl,exec-units-mask = <0x7e>;
  277. fsl,descriptor-types-mask = <0x01010ebf>;
  278. };
  279. ipic: pic@700 {
  280. interrupt-controller;
  281. #address-cells = <0>;
  282. #interrupt-cells = <2>;
  283. reg = <0x700 0x100>;
  284. device_type = "ipic";
  285. };
  286. gpio-leds {
  287. compatible = "gpio-leds";
  288. green {
  289. label = "Green";
  290. gpios = <&pcf1 0 1>;
  291. linux,default-trigger = "heartbeat";
  292. };
  293. yellow {
  294. label = "Yellow";
  295. gpios = <&pcf1 1 1>;
  296. /* linux,default-trigger = "heartbeat"; */
  297. default-state = "on";
  298. };
  299. };
  300. };
  301. pci0: pci@e0008500 {
  302. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  303. interrupt-map = <
  304. /* IDSEL 0x10 - SATA */
  305. 0x8000 0x0 0x0 0x1 &ipic 22 0x8 /* SATA_INTA */
  306. >;
  307. interrupt-parent = <&ipic>;
  308. interrupts = <66 0x8>;
  309. bus-range = <0x0 0x0>;
  310. ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
  311. 0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
  312. 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x01000000>;
  313. clock-frequency = <66666666>;
  314. #interrupt-cells = <1>;
  315. #size-cells = <2>;
  316. #address-cells = <3>;
  317. reg = <0xe0008500 0x100 /* internal registers */
  318. 0xe0008300 0x8>; /* config space access registers */
  319. compatible = "fsl,mpc8349-pci";
  320. device_type = "pci";
  321. };
  322. pci1: pci@e0008600 {
  323. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  324. interrupt-map = <
  325. /* IDSEL 0x0E - MiniPCI Slot */
  326. 0x7000 0x0 0x0 0x1 &ipic 21 0x8 /* PCI_INTA */
  327. /* IDSEL 0x0F - PCI Slot */
  328. 0x7800 0x0 0x0 0x1 &ipic 20 0x8 /* PCI_INTA */
  329. 0x7800 0x0 0x0 0x2 &ipic 21 0x8 /* PCI_INTB */
  330. >;
  331. interrupt-parent = <&ipic>;
  332. interrupts = <67 0x8>;
  333. bus-range = <0x0 0x0>;
  334. ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
  335. 0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
  336. 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x01000000>;
  337. clock-frequency = <66666666>;
  338. #interrupt-cells = <1>;
  339. #size-cells = <2>;
  340. #address-cells = <3>;
  341. reg = <0xe0008600 0x100 /* internal registers */
  342. 0xe0008380 0x8>; /* config space access registers */
  343. compatible = "fsl,mpc8349-pci";
  344. device_type = "pci";
  345. };
  346. localbus@e0005000 {
  347. #address-cells = <2>;
  348. #size-cells = <1>;
  349. compatible = "fsl,mpc8349e-localbus",
  350. "fsl,pq2pro-localbus",
  351. "simple-bus";
  352. reg = <0xe0005000 0xd8>;
  353. ranges = <0x0 0x0 0xfe000000 0x1000000 /* flash */
  354. 0x1 0x0 0xf8000000 0x20000 /* VSC 7385 */
  355. 0x2 0x0 0xf9000000 0x200000 /* exp slot */
  356. 0x3 0x0 0xf0000000 0x210>; /* CF slot */
  357. flash@0,0 {
  358. compatible = "cfi-flash";
  359. reg = <0x0 0x0 0x800000>;
  360. bank-width = <2>;
  361. device-width = <1>;
  362. };
  363. flash@0,800000 {
  364. #address-cells = <1>;
  365. #size-cells = <1>;
  366. compatible = "cfi-flash";
  367. reg = <0x0 0x800000 0x800000>;
  368. bank-width = <2>;
  369. device-width = <1>;
  370. };
  371. pata@3,0 {
  372. compatible = "fsl,mpc8349emitx-pata", "ata-generic";
  373. reg = <0x3 0x0 0x10 0x3 0x20c 0x4>;
  374. reg-shift = <1>;
  375. pio-mode = <6>;
  376. interrupts = <23 0x8>;
  377. interrupt-parent = <&ipic>;
  378. };
  379. };
  380. };