rainier.dts 8.8 KB

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  1. /*
  2. * Device Tree Source for AMCC Rainier
  3. *
  4. * Based on Sequoia code
  5. * Copyright (c) 2007 MontaVista Software, Inc.
  6. *
  7. * FIXME: Draft only!
  8. *
  9. * This file is licensed under the terms of the GNU General Public
  10. * License version 2. This program is licensed "as is" without
  11. * any warranty of any kind, whether express or implied.
  12. *
  13. */
  14. /dts-v1/;
  15. / {
  16. #address-cells = <2>;
  17. #size-cells = <1>;
  18. model = "amcc,rainier";
  19. compatible = "amcc,rainier";
  20. dcr-parent = <&{/cpus/cpu@0}>;
  21. aliases {
  22. ethernet0 = &EMAC0;
  23. ethernet1 = &EMAC1;
  24. serial0 = &UART0;
  25. serial1 = &UART1;
  26. serial2 = &UART2;
  27. serial3 = &UART3;
  28. };
  29. cpus {
  30. #address-cells = <1>;
  31. #size-cells = <0>;
  32. cpu@0 {
  33. device_type = "cpu";
  34. model = "PowerPC,440GRx";
  35. reg = <0x00000000>;
  36. clock-frequency = <0>; /* Filled in by zImage */
  37. timebase-frequency = <0>; /* Filled in by zImage */
  38. i-cache-line-size = <32>;
  39. d-cache-line-size = <32>;
  40. i-cache-size = <32768>;
  41. d-cache-size = <32768>;
  42. dcr-controller;
  43. dcr-access-method = "native";
  44. };
  45. };
  46. memory {
  47. device_type = "memory";
  48. reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */
  49. };
  50. UIC0: interrupt-controller0 {
  51. compatible = "ibm,uic-440grx","ibm,uic";
  52. interrupt-controller;
  53. cell-index = <0>;
  54. dcr-reg = <0x0c0 0x009>;
  55. #address-cells = <0>;
  56. #size-cells = <0>;
  57. #interrupt-cells = <2>;
  58. };
  59. UIC1: interrupt-controller1 {
  60. compatible = "ibm,uic-440grx","ibm,uic";
  61. interrupt-controller;
  62. cell-index = <1>;
  63. dcr-reg = <0x0d0 0x009>;
  64. #address-cells = <0>;
  65. #size-cells = <0>;
  66. #interrupt-cells = <2>;
  67. interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
  68. interrupt-parent = <&UIC0>;
  69. };
  70. UIC2: interrupt-controller2 {
  71. compatible = "ibm,uic-440grx","ibm,uic";
  72. interrupt-controller;
  73. cell-index = <2>;
  74. dcr-reg = <0x0e0 0x009>;
  75. #address-cells = <0>;
  76. #size-cells = <0>;
  77. #interrupt-cells = <2>;
  78. interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
  79. interrupt-parent = <&UIC0>;
  80. };
  81. SDR0: sdr {
  82. compatible = "ibm,sdr-440grx", "ibm,sdr-440ep";
  83. dcr-reg = <0x00e 0x002>;
  84. };
  85. CPR0: cpr {
  86. compatible = "ibm,cpr-440grx", "ibm,cpr-440ep";
  87. dcr-reg = <0x00c 0x002>;
  88. };
  89. plb {
  90. compatible = "ibm,plb-440grx", "ibm,plb4";
  91. #address-cells = <2>;
  92. #size-cells = <1>;
  93. ranges;
  94. clock-frequency = <0>; /* Filled in by zImage */
  95. SDRAM0: sdram {
  96. compatible = "ibm,sdram-440grx", "ibm,sdram-44x-ddr2denali";
  97. dcr-reg = <0x010 0x002>;
  98. };
  99. DMA0: dma {
  100. compatible = "ibm,dma-440grx", "ibm,dma-4xx";
  101. dcr-reg = <0x100 0x027>;
  102. };
  103. MAL0: mcmal {
  104. compatible = "ibm,mcmal-440grx", "ibm,mcmal2";
  105. dcr-reg = <0x180 0x062>;
  106. num-tx-chans = <2>;
  107. num-rx-chans = <2>;
  108. interrupt-parent = <&MAL0>;
  109. interrupts = <0x0 0x1 0x2 0x3 0x4>;
  110. #interrupt-cells = <1>;
  111. #address-cells = <0>;
  112. #size-cells = <0>;
  113. interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
  114. /*RXEOB*/ 0x1 &UIC0 0xb 0x4
  115. /*SERR*/ 0x2 &UIC1 0x0 0x4
  116. /*TXDE*/ 0x3 &UIC1 0x1 0x4
  117. /*RXDE*/ 0x4 &UIC1 0x2 0x4>;
  118. interrupt-map-mask = <0xffffffff>;
  119. };
  120. POB0: opb {
  121. compatible = "ibm,opb-440grx", "ibm,opb";
  122. #address-cells = <1>;
  123. #size-cells = <1>;
  124. ranges = <0x00000000 0x00000001 0x00000000 0x80000000
  125. 0x80000000 0x00000001 0x80000000 0x80000000>;
  126. interrupt-parent = <&UIC1>;
  127. interrupts = <0x7 0x4>;
  128. clock-frequency = <0>; /* Filled in by zImage */
  129. EBC0: ebc {
  130. compatible = "ibm,ebc-440grx", "ibm,ebc";
  131. dcr-reg = <0x012 0x002>;
  132. #address-cells = <2>;
  133. #size-cells = <1>;
  134. clock-frequency = <0>; /* Filled in by zImage */
  135. interrupts = <0x5 0x1>;
  136. interrupt-parent = <&UIC1>;
  137. nor_flash@0,0 {
  138. compatible = "amd,s29gl256n", "cfi-flash";
  139. bank-width = <2>;
  140. reg = <0x00000000 0x00000000 0x04000000>;
  141. #address-cells = <1>;
  142. #size-cells = <1>;
  143. partition@0 {
  144. label = "Kernel";
  145. reg = <0x00000000 0x00180000>;
  146. };
  147. partition@180000 {
  148. label = "ramdisk";
  149. reg = <0x00180000 0x00200000>;
  150. };
  151. partition@380000 {
  152. label = "file system";
  153. reg = <0x00380000 0x03aa0000>;
  154. };
  155. partition@3e20000 {
  156. label = "kozio";
  157. reg = <0x03e20000 0x00140000>;
  158. };
  159. partition@3f60000 {
  160. label = "env";
  161. reg = <0x03f60000 0x00040000>;
  162. };
  163. partition@3fa0000 {
  164. label = "u-boot";
  165. reg = <0x03fa0000 0x00060000>;
  166. };
  167. };
  168. };
  169. UART0: serial@ef600300 {
  170. device_type = "serial";
  171. compatible = "ns16550";
  172. reg = <0xef600300 0x00000008>;
  173. virtual-reg = <0xef600300>;
  174. clock-frequency = <0>; /* Filled in by zImage */
  175. current-speed = <115200>;
  176. interrupt-parent = <&UIC0>;
  177. interrupts = <0x0 0x4>;
  178. };
  179. UART1: serial@ef600400 {
  180. device_type = "serial";
  181. compatible = "ns16550";
  182. reg = <0xef600400 0x00000008>;
  183. virtual-reg = <0xef600400>;
  184. clock-frequency = <0>;
  185. current-speed = <0>;
  186. interrupt-parent = <&UIC0>;
  187. interrupts = <0x1 0x4>;
  188. };
  189. UART2: serial@ef600500 {
  190. device_type = "serial";
  191. compatible = "ns16550";
  192. reg = <0xef600500 0x00000008>;
  193. virtual-reg = <0xef600500>;
  194. clock-frequency = <0>;
  195. current-speed = <0>;
  196. interrupt-parent = <&UIC1>;
  197. interrupts = <0x3 0x4>;
  198. };
  199. UART3: serial@ef600600 {
  200. device_type = "serial";
  201. compatible = "ns16550";
  202. reg = <0xef600600 0x00000008>;
  203. virtual-reg = <0xef600600>;
  204. clock-frequency = <0>;
  205. current-speed = <0>;
  206. interrupt-parent = <&UIC1>;
  207. interrupts = <0x4 0x4>;
  208. };
  209. IIC0: i2c@ef600700 {
  210. compatible = "ibm,iic-440grx", "ibm,iic";
  211. reg = <0xef600700 0x00000014>;
  212. interrupt-parent = <&UIC0>;
  213. interrupts = <0x2 0x4>;
  214. };
  215. IIC1: i2c@ef600800 {
  216. compatible = "ibm,iic-440grx", "ibm,iic";
  217. reg = <0xef600800 0x00000014>;
  218. interrupt-parent = <&UIC0>;
  219. interrupts = <0x7 0x4>;
  220. };
  221. ZMII0: emac-zmii@ef600d00 {
  222. compatible = "ibm,zmii-440grx", "ibm,zmii";
  223. reg = <0xef600d00 0x0000000c>;
  224. };
  225. RGMII0: emac-rgmii@ef601000 {
  226. compatible = "ibm,rgmii-440grx", "ibm,rgmii";
  227. reg = <0xef601000 0x00000008>;
  228. has-mdio;
  229. };
  230. EMAC0: ethernet@ef600e00 {
  231. device_type = "network";
  232. compatible = "ibm,emac-440grx", "ibm,emac-440epx", "ibm,emac4";
  233. interrupt-parent = <&EMAC0>;
  234. interrupts = <0x0 0x1>;
  235. #interrupt-cells = <1>;
  236. #address-cells = <0>;
  237. #size-cells = <0>;
  238. interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4
  239. /*Wake*/ 0x1 &UIC1 0x1d 0x4>;
  240. reg = <0xef600e00 0x00000074>;
  241. local-mac-address = [000000000000];
  242. mal-device = <&MAL0>;
  243. mal-tx-channel = <0>;
  244. mal-rx-channel = <0>;
  245. cell-index = <0>;
  246. max-frame-size = <9000>;
  247. rx-fifo-size = <4096>;
  248. tx-fifo-size = <2048>;
  249. phy-mode = "rgmii";
  250. phy-map = <0x00000000>;
  251. zmii-device = <&ZMII0>;
  252. zmii-channel = <0>;
  253. rgmii-device = <&RGMII0>;
  254. rgmii-channel = <0>;
  255. has-inverted-stacr-oc;
  256. has-new-stacr-staopc;
  257. };
  258. EMAC1: ethernet@ef600f00 {
  259. device_type = "network";
  260. compatible = "ibm,emac-440grx", "ibm,emac-440epx", "ibm,emac4";
  261. interrupt-parent = <&EMAC1>;
  262. interrupts = <0x0 0x1>;
  263. #interrupt-cells = <1>;
  264. #address-cells = <0>;
  265. #size-cells = <0>;
  266. interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4
  267. /*Wake*/ 0x1 &UIC1 0x1f 0x4>;
  268. reg = <0xef600f00 0x00000074>;
  269. local-mac-address = [000000000000];
  270. mal-device = <&MAL0>;
  271. mal-tx-channel = <1>;
  272. mal-rx-channel = <1>;
  273. cell-index = <1>;
  274. max-frame-size = <9000>;
  275. rx-fifo-size = <4096>;
  276. tx-fifo-size = <2048>;
  277. phy-mode = "rgmii";
  278. phy-map = <0x00000000>;
  279. zmii-device = <&ZMII0>;
  280. zmii-channel = <1>;
  281. rgmii-device = <&RGMII0>;
  282. rgmii-channel = <1>;
  283. has-inverted-stacr-oc;
  284. has-new-stacr-staopc;
  285. };
  286. };
  287. PCI0: pci@1ec000000 {
  288. device_type = "pci";
  289. #interrupt-cells = <1>;
  290. #size-cells = <2>;
  291. #address-cells = <3>;
  292. compatible = "ibm,plb440grx-pci", "ibm,plb-pci";
  293. primary;
  294. reg = <0x00000001 0xeec00000 0x00000008 /* Config space access */
  295. 0x00000001 0xeed00000 0x00000004 /* IACK */
  296. 0x00000001 0xeed00000 0x00000004 /* Special cycle */
  297. 0x00000001 0xef400000 0x00000040>; /* Internal registers */
  298. /* Outbound ranges, one memory and one IO,
  299. * later cannot be changed. Chip supports a second
  300. * IO range but we don't use it for now
  301. */
  302. ranges = <0x02000000 0x0 0x80000000 0x1 0x80000000 0x0 0x40000000
  303. 0x01000000 0x0 0x00000000 0x1 0xe8000000 0x0 0x00010000
  304. 0x01000000 0x0 0x00000000 0x1 0xe8800000 0x0 0x03800000>;
  305. /* Inbound 2GB range starting at 0 */
  306. dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
  307. /* All PCI interrupts are routed to IRQ 67 */
  308. interrupt-map-mask = <0x0 0x0 0x0 0x0>;
  309. interrupt-map = < 0x0 0x0 0x0 0x0 &UIC2 0x3 0x8 >;
  310. };
  311. };
  312. chosen {
  313. linux,stdout-path = "/plb/opb/serial@ef600300";
  314. bootargs = "console=ttyS0,115200";
  315. };
  316. };