wii-head.S 3.1 KB

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  1. /*
  2. * arch/powerpc/boot/wii-head.S
  3. *
  4. * Nintendo Wii bootwrapper entry.
  5. * Copyright (C) 2008-2009 The GameCube Linux Team
  6. * Copyright (C) 2008,2009 Albert Herranz
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License
  10. * as published by the Free Software Foundation; either version 2
  11. * of the License, or (at your option) any later version.
  12. *
  13. */
  14. #include "ppc_asm.h"
  15. /*
  16. * The entry code does no assumptions regarding:
  17. * - if the data and instruction caches are enabled or not
  18. * - if the MMU is enabled or not
  19. * - if the high BATs are enabled or not
  20. *
  21. * We enable the high BATs, enable the caches if not already enabled,
  22. * enable the MMU with an identity mapping scheme and jump to the start code.
  23. */
  24. .text
  25. .globl _zimage_start
  26. _zimage_start:
  27. /* turn the MMU off */
  28. mfmsr 9
  29. rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
  30. bcl 20, 31, 1f
  31. 1:
  32. mflr 8
  33. clrlwi 8, 8, 3 /* convert to a real address */
  34. addi 8, 8, _mmu_off - 1b
  35. mtsrr0 8
  36. mtsrr1 9
  37. rfi
  38. _mmu_off:
  39. /* MMU disabled */
  40. /* setup BATs */
  41. isync
  42. li 8, 0
  43. mtspr 0x210, 8 /* IBAT0U */
  44. mtspr 0x212, 8 /* IBAT1U */
  45. mtspr 0x214, 8 /* IBAT2U */
  46. mtspr 0x216, 8 /* IBAT3U */
  47. mtspr 0x218, 8 /* DBAT0U */
  48. mtspr 0x21a, 8 /* DBAT1U */
  49. mtspr 0x21c, 8 /* DBAT2U */
  50. mtspr 0x21e, 8 /* DBAT3U */
  51. mtspr 0x230, 8 /* IBAT4U */
  52. mtspr 0x232, 8 /* IBAT5U */
  53. mtspr 0x234, 8 /* IBAT6U */
  54. mtspr 0x236, 8 /* IBAT7U */
  55. mtspr 0x238, 8 /* DBAT4U */
  56. mtspr 0x23a, 8 /* DBAT5U */
  57. mtspr 0x23c, 8 /* DBAT6U */
  58. mtspr 0x23e, 8 /* DBAT7U */
  59. li 8, 0x01ff /* first 16MiB */
  60. li 9, 0x0002 /* rw */
  61. mtspr 0x211, 9 /* IBAT0L */
  62. mtspr 0x210, 8 /* IBAT0U */
  63. mtspr 0x219, 9 /* DBAT0L */
  64. mtspr 0x218, 8 /* DBAT0U */
  65. lis 8, 0x0c00 /* I/O mem */
  66. ori 8, 8, 0x3ff /* 32MiB */
  67. lis 9, 0x0c00
  68. ori 9, 9, 0x002a /* uncached, guarded, rw */
  69. mtspr 0x21b, 9 /* DBAT1L */
  70. mtspr 0x21a, 8 /* DBAT1U */
  71. lis 8, 0x0100 /* next 8MiB */
  72. ori 8, 8, 0x00ff /* 8MiB */
  73. lis 9, 0x0100
  74. ori 9, 9, 0x0002 /* rw */
  75. mtspr 0x215, 9 /* IBAT2L */
  76. mtspr 0x214, 8 /* IBAT2U */
  77. mtspr 0x21d, 9 /* DBAT2L */
  78. mtspr 0x21c, 8 /* DBAT2U */
  79. lis 8, 0x1000 /* MEM2 */
  80. ori 8, 8, 0x07ff /* 64MiB */
  81. lis 9, 0x1000
  82. ori 9, 9, 0x0002 /* rw */
  83. mtspr 0x216, 8 /* IBAT3U */
  84. mtspr 0x217, 9 /* IBAT3L */
  85. mtspr 0x21e, 8 /* DBAT3U */
  86. mtspr 0x21f, 9 /* DBAT3L */
  87. /* enable the high BATs */
  88. mfspr 8, 0x3f3 /* HID4 */
  89. oris 8, 8, 0x0200
  90. mtspr 0x3f3, 8 /* HID4 */
  91. /* enable and invalidate the caches if not already enabled */
  92. mfspr 8, 0x3f0 /* HID0 */
  93. andi. 0, 8, (1<<15) /* HID0_ICE */
  94. bne 1f
  95. ori 8, 8, (1<<15)|(1<<11) /* HID0_ICE|HID0_ICFI*/
  96. 1:
  97. andi. 0, 8, (1<<14) /* HID0_DCE */
  98. bne 1f
  99. ori 8, 8, (1<<14)|(1<<10) /* HID0_DCE|HID0_DCFI*/
  100. 1:
  101. mtspr 0x3f0, 8 /* HID0 */
  102. isync
  103. /* initialize arguments */
  104. li 3, 0
  105. li 4, 0
  106. li 5, 0
  107. /* turn the MMU on */
  108. bcl 20, 31, 1f
  109. 1:
  110. mflr 8
  111. addi 8, 8, _mmu_on - 1b
  112. mfmsr 9
  113. ori 9, 9, (1<<4)|(1<<5) /* MSR_DR|MSR_IR */
  114. mtsrr0 8
  115. mtsrr1 9
  116. sync
  117. rfi
  118. _mmu_on:
  119. /* turn on the front blue led (aka: yay! we got here!) */
  120. lis 8, 0x0d00
  121. ori 8, 8, 0x00c0
  122. lwz 9, 0(8)
  123. ori 9, 9, 0x20
  124. stw 9, 0(8)
  125. b _zimage_start_lib