sstep.h 2.1 KB

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  1. /*
  2. * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * as published by the Free Software Foundation; either version
  7. * 2 of the License, or (at your option) any later version.
  8. */
  9. struct pt_regs;
  10. /*
  11. * We don't allow single-stepping an mtmsrd that would clear
  12. * MSR_RI, since that would make the exception unrecoverable.
  13. * Since we need to single-step to proceed from a breakpoint,
  14. * we don't allow putting a breakpoint on an mtmsrd instruction.
  15. * Similarly we don't allow breakpoints on rfid instructions.
  16. * These macros tell us if an instruction is a mtmsrd or rfid.
  17. * Note that IS_MTMSRD returns true for both an mtmsr (32-bit)
  18. * and an mtmsrd (64-bit).
  19. */
  20. #define IS_MTMSRD(instr) (((instr) & 0xfc0007be) == 0x7c000124)
  21. #define IS_RFID(instr) (((instr) & 0xfc0007fe) == 0x4c000024)
  22. #define IS_RFI(instr) (((instr) & 0xfc0007fe) == 0x4c000064)
  23. /* Emulate instructions that cause a transfer of control. */
  24. extern int emulate_step(struct pt_regs *regs, unsigned int instr);
  25. enum instruction_type {
  26. COMPUTE, /* arith/logical/CR op, etc. */
  27. LOAD,
  28. LOAD_MULTI,
  29. LOAD_FP,
  30. LOAD_VMX,
  31. LOAD_VSX,
  32. STORE,
  33. STORE_MULTI,
  34. STORE_FP,
  35. STORE_VMX,
  36. STORE_VSX,
  37. LARX,
  38. STCX,
  39. BRANCH,
  40. MFSPR,
  41. MTSPR,
  42. CACHEOP,
  43. BARRIER,
  44. SYSCALL,
  45. MFMSR,
  46. MTMSR,
  47. RFI,
  48. INTERRUPT,
  49. UNKNOWN
  50. };
  51. #define INSTR_TYPE_MASK 0x1f
  52. /* Load/store flags, ORed in with type */
  53. #define SIGNEXT 0x20
  54. #define UPDATE 0x40 /* matches bit in opcode 31 instructions */
  55. #define BYTEREV 0x80
  56. /* Cacheop values, ORed in with type */
  57. #define CACHEOP_MASK 0x700
  58. #define DCBST 0
  59. #define DCBF 0x100
  60. #define DCBTST 0x200
  61. #define DCBT 0x300
  62. #define ICBI 0x400
  63. /* Size field in type word */
  64. #define SIZE(n) ((n) << 8)
  65. #define GETSIZE(w) ((w) >> 8)
  66. #define MKOP(t, f, s) ((t) | (f) | SIZE(s))
  67. struct instruction_op {
  68. int type;
  69. int reg;
  70. unsigned long val;
  71. /* For LOAD/STORE/LARX/STCX */
  72. unsigned long ea;
  73. int update_reg;
  74. /* For MFSPR */
  75. int spr;
  76. };
  77. extern int analyse_instr(struct instruction_op *op, struct pt_regs *regs,
  78. unsigned int instr);