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cacheflush.S

cacheflush.S 1.9 KB
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  1. /*
    2. 

  2.  * vDSO provided cache flush routines
    3. 

  3.  *
    4. 

  4.  * Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org),
    5. 

  5.  *                    IBM Corp.
    6. 

  6.  *
    7. 

  7.  * This program is free software; you can redistribute it and/or
    8. 

  8.  * modify it under the terms of the GNU General Public License
    9. 

  9.  * as published by the Free Software Foundation; either version
    10. 

  10.  * 2 of the License, or (at your option) any later version.
    11. 

  11.  */
    12. 

  12. #include <asm/processor.h>
    13. 

  13. #include <asm/ppc_asm.h>
    14. 

  14. #include <asm/vdso.h>
    15. 

  15. #include <asm/asm-offsets.h>
    16. 

  16. 

  17. 	.text
    18. 

  18. 

  19. /*
    20. 

  20.  * Default "generic" version of __kernel_sync_dicache.
    21. 

  21.  *
    22. 

  22.  * void __kernel_sync_dicache(unsigned long start, unsigned long end)
    23. 

  23.  *
    24. 

  24.  * Flushes the data cache & invalidate the instruction cache for the
    25. 

  25.  * provided range [start, end[
    26. 

  26.  */
    27. 

  27. V_FUNCTION_BEGIN(__kernel_sync_dicache)
    28. 

  28.   .cfi_startproc
    29. 

  29. 	mflr	r12
    30. 

  30.   .cfi_register lr,r12
    31. 

  31. 	mr	r11,r3
    32. 

  32. 	bl	V_LOCAL_FUNC(__get_datapage)
    33. 

  33. 	mtlr	r12
    34. 

  34. 	mr	r10,r3
    35. 

  35. 

  36. 	lwz	r7,CFG_DCACHE_BLOCKSZ(r10)
    37. 

  37. 	addi	r5,r7,-1
    38. 

  38. 	andc	r6,r11,r5		/* round low to line bdy */
    39. 

  39. 	subf	r8,r6,r4		/* compute length */
    40. 

  40. 	add	r8,r8,r5		/* ensure we get enough */
    41. 

  41. 	lwz	r9,CFG_DCACHE_LOGBLOCKSZ(r10)
    42. 

  42. 	srw.	r8,r8,r9		/* compute line count */
    43. 

  43. 	crclr	cr0*4+so
    44. 

  44. 	beqlr				/* nothing to do? */
    45. 

  45. 	mtctr	r8
    46. 

  46. 1:	dcbst	0,r6
    47. 

  47. 	add	r6,r6,r7
    48. 

  48. 	bdnz	1b
    49. 

  49. 	sync
    50. 

  50. 

  51. /* Now invalidate the instruction cache */
    52. 

  52. 

  53. 	lwz	r7,CFG_ICACHE_BLOCKSZ(r10)
    54. 

  54. 	addi	r5,r7,-1
    55. 

  55. 	andc	r6,r11,r5		/* round low to line bdy */
    56. 

  56. 	subf	r8,r6,r4		/* compute length */
    57. 

  57. 	add	r8,r8,r5
    58. 

  58. 	lwz	r9,CFG_ICACHE_LOGBLOCKSZ(r10)
    59. 

  59. 	srw.	r8,r8,r9		/* compute line count */
    60. 

  60. 	crclr	cr0*4+so
    61. 

  61. 	beqlr				/* nothing to do? */
    62. 

  62. 	mtctr	r8
    63. 

  63. 2:	icbi	0,r6
    64. 

  64. 	add	r6,r6,r7
    65. 

  65. 	bdnz	2b
    66. 

  66. 	isync
    67. 

  67. 	li	r3,0
    68. 

  68. 	blr
    69. 

  69.   .cfi_endproc
    70. 

  70. V_FUNCTION_END(__kernel_sync_dicache)
    71. 

  71. 

  72. 

  73. /*
    74. 

  74.  * POWER5 version of __kernel_sync_dicache
    75. 

  75.  */
    76. 

  76. V_FUNCTION_BEGIN(__kernel_sync_dicache_p5)
    77. 

  77.   .cfi_startproc
    78. 

  78. 	crclr	cr0*4+so
    79. 

  79. 	sync
    80. 

  80. 	isync
    81. 

  81. 	li	r3,0
    82. 

  82. 	blr
    83. 

  83.   .cfi_endproc
    84. 

  84. V_FUNCTION_END(__kernel_sync_dicache_p5)
    85.