book3s_hv_ras.c 4.2 KB

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  1. /*
  2. * This program is free software; you can redistribute it and/or modify
  3. * it under the terms of the GNU General Public License, version 2, as
  4. * published by the Free Software Foundation.
  5. *
  6. * Copyright 2012 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
  7. */
  8. #include <linux/types.h>
  9. #include <linux/string.h>
  10. #include <linux/kvm.h>
  11. #include <linux/kvm_host.h>
  12. #include <linux/kernel.h>
  13. #include <asm/opal.h>
  14. #include <asm/mce.h>
  15. /* SRR1 bits for machine check on POWER7 */
  16. #define SRR1_MC_LDSTERR (1ul << (63-42))
  17. #define SRR1_MC_IFETCH_SH (63-45)
  18. #define SRR1_MC_IFETCH_MASK 0x7
  19. #define SRR1_MC_IFETCH_SLBPAR 2 /* SLB parity error */
  20. #define SRR1_MC_IFETCH_SLBMULTI 3 /* SLB multi-hit */
  21. #define SRR1_MC_IFETCH_SLBPARMULTI 4 /* SLB parity + multi-hit */
  22. #define SRR1_MC_IFETCH_TLBMULTI 5 /* I-TLB multi-hit */
  23. /* DSISR bits for machine check on POWER7 */
  24. #define DSISR_MC_DERAT_MULTI 0x800 /* D-ERAT multi-hit */
  25. #define DSISR_MC_TLB_MULTI 0x400 /* D-TLB multi-hit */
  26. #define DSISR_MC_SLB_PARITY 0x100 /* SLB parity error */
  27. #define DSISR_MC_SLB_MULTI 0x080 /* SLB multi-hit */
  28. #define DSISR_MC_SLB_PARMULTI 0x040 /* SLB parity + multi-hit */
  29. /* POWER7 SLB flush and reload */
  30. static void reload_slb(struct kvm_vcpu *vcpu)
  31. {
  32. struct slb_shadow *slb;
  33. unsigned long i, n;
  34. /* First clear out SLB */
  35. asm volatile("slbmte %0,%0; slbia" : : "r" (0));
  36. /* Do they have an SLB shadow buffer registered? */
  37. slb = vcpu->arch.slb_shadow.pinned_addr;
  38. if (!slb)
  39. return;
  40. /* Sanity check */
  41. n = min_t(u32, be32_to_cpu(slb->persistent), SLB_MIN_SIZE);
  42. if ((void *) &slb->save_area[n] > vcpu->arch.slb_shadow.pinned_end)
  43. return;
  44. /* Load up the SLB from that */
  45. for (i = 0; i < n; ++i) {
  46. unsigned long rb = be64_to_cpu(slb->save_area[i].esid);
  47. unsigned long rs = be64_to_cpu(slb->save_area[i].vsid);
  48. rb = (rb & ~0xFFFul) | i; /* insert entry number */
  49. asm volatile("slbmte %0,%1" : : "r" (rs), "r" (rb));
  50. }
  51. }
  52. /*
  53. * On POWER7, see if we can handle a machine check that occurred inside
  54. * the guest in real mode, without switching to the host partition.
  55. *
  56. * Returns: 0 => exit guest, 1 => deliver machine check to guest
  57. */
  58. static long kvmppc_realmode_mc_power7(struct kvm_vcpu *vcpu)
  59. {
  60. unsigned long srr1 = vcpu->arch.shregs.msr;
  61. struct machine_check_event mce_evt;
  62. long handled = 1;
  63. if (srr1 & SRR1_MC_LDSTERR) {
  64. /* error on load/store */
  65. unsigned long dsisr = vcpu->arch.shregs.dsisr;
  66. if (dsisr & (DSISR_MC_SLB_PARMULTI | DSISR_MC_SLB_MULTI |
  67. DSISR_MC_SLB_PARITY | DSISR_MC_DERAT_MULTI)) {
  68. /* flush and reload SLB; flushes D-ERAT too */
  69. reload_slb(vcpu);
  70. dsisr &= ~(DSISR_MC_SLB_PARMULTI | DSISR_MC_SLB_MULTI |
  71. DSISR_MC_SLB_PARITY | DSISR_MC_DERAT_MULTI);
  72. }
  73. if (dsisr & DSISR_MC_TLB_MULTI) {
  74. if (cur_cpu_spec && cur_cpu_spec->flush_tlb)
  75. cur_cpu_spec->flush_tlb(TLB_INVAL_SCOPE_LPID);
  76. dsisr &= ~DSISR_MC_TLB_MULTI;
  77. }
  78. /* Any other errors we don't understand? */
  79. if (dsisr & 0xffffffffUL)
  80. handled = 0;
  81. }
  82. switch ((srr1 >> SRR1_MC_IFETCH_SH) & SRR1_MC_IFETCH_MASK) {
  83. case 0:
  84. break;
  85. case SRR1_MC_IFETCH_SLBPAR:
  86. case SRR1_MC_IFETCH_SLBMULTI:
  87. case SRR1_MC_IFETCH_SLBPARMULTI:
  88. reload_slb(vcpu);
  89. break;
  90. case SRR1_MC_IFETCH_TLBMULTI:
  91. if (cur_cpu_spec && cur_cpu_spec->flush_tlb)
  92. cur_cpu_spec->flush_tlb(TLB_INVAL_SCOPE_LPID);
  93. break;
  94. default:
  95. handled = 0;
  96. }
  97. /*
  98. * See if we have already handled the condition in the linux host.
  99. * We assume that if the condition is recovered then linux host
  100. * will have generated an error log event that we will pick
  101. * up and log later.
  102. * Don't release mce event now. We will queue up the event so that
  103. * we can log the MCE event info on host console.
  104. */
  105. if (!get_mce_event(&mce_evt, MCE_EVENT_DONTRELEASE))
  106. goto out;
  107. if (mce_evt.version == MCE_V1 &&
  108. (mce_evt.severity == MCE_SEV_NO_ERROR ||
  109. mce_evt.disposition == MCE_DISPOSITION_RECOVERED))
  110. handled = 1;
  111. out:
  112. /*
  113. * We are now going enter guest either through machine check
  114. * interrupt (for unhandled errors) or will continue from
  115. * current HSRR0 (for handled errors) in guest. Hence
  116. * queue up the event so that we can log it from host console later.
  117. */
  118. machine_check_queue_event();
  119. return handled;
  120. }
  121. long kvmppc_realmode_machine_check(struct kvm_vcpu *vcpu)
  122. {
  123. return kvmppc_realmode_mc_power7(vcpu);
  124. }