math_efp.c 20 KB

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  1. /*
  2. * arch/powerpc/math-emu/math_efp.c
  3. *
  4. * Copyright (C) 2006-2008, 2010 Freescale Semiconductor, Inc.
  5. *
  6. * Author: Ebony Zhu, <ebony.zhu@freescale.com>
  7. * Yu Liu, <yu.liu@freescale.com>
  8. *
  9. * Derived from arch/alpha/math-emu/math.c
  10. * arch/powerpc/math-emu/math.c
  11. *
  12. * Description:
  13. * This file is the exception handler to make E500 SPE instructions
  14. * fully comply with IEEE-754 floating point standard.
  15. *
  16. * This program is free software; you can redistribute it and/or
  17. * modify it under the terms of the GNU General Public License
  18. * as published by the Free Software Foundation; either version
  19. * 2 of the License, or (at your option) any later version.
  20. */
  21. #include <linux/types.h>
  22. #include <linux/prctl.h>
  23. #include <asm/uaccess.h>
  24. #include <asm/reg.h>
  25. #define FP_EX_BOOKE_E500_SPE
  26. #include <asm/sfp-machine.h>
  27. #include <math-emu/soft-fp.h>
  28. #include <math-emu/single.h>
  29. #include <math-emu/double.h>
  30. #define EFAPU 0x4
  31. #define VCT 0x4
  32. #define SPFP 0x6
  33. #define DPFP 0x7
  34. #define EFSADD 0x2c0
  35. #define EFSSUB 0x2c1
  36. #define EFSABS 0x2c4
  37. #define EFSNABS 0x2c5
  38. #define EFSNEG 0x2c6
  39. #define EFSMUL 0x2c8
  40. #define EFSDIV 0x2c9
  41. #define EFSCMPGT 0x2cc
  42. #define EFSCMPLT 0x2cd
  43. #define EFSCMPEQ 0x2ce
  44. #define EFSCFD 0x2cf
  45. #define EFSCFSI 0x2d1
  46. #define EFSCTUI 0x2d4
  47. #define EFSCTSI 0x2d5
  48. #define EFSCTUF 0x2d6
  49. #define EFSCTSF 0x2d7
  50. #define EFSCTUIZ 0x2d8
  51. #define EFSCTSIZ 0x2da
  52. #define EVFSADD 0x280
  53. #define EVFSSUB 0x281
  54. #define EVFSABS 0x284
  55. #define EVFSNABS 0x285
  56. #define EVFSNEG 0x286
  57. #define EVFSMUL 0x288
  58. #define EVFSDIV 0x289
  59. #define EVFSCMPGT 0x28c
  60. #define EVFSCMPLT 0x28d
  61. #define EVFSCMPEQ 0x28e
  62. #define EVFSCTUI 0x294
  63. #define EVFSCTSI 0x295
  64. #define EVFSCTUF 0x296
  65. #define EVFSCTSF 0x297
  66. #define EVFSCTUIZ 0x298
  67. #define EVFSCTSIZ 0x29a
  68. #define EFDADD 0x2e0
  69. #define EFDSUB 0x2e1
  70. #define EFDABS 0x2e4
  71. #define EFDNABS 0x2e5
  72. #define EFDNEG 0x2e6
  73. #define EFDMUL 0x2e8
  74. #define EFDDIV 0x2e9
  75. #define EFDCTUIDZ 0x2ea
  76. #define EFDCTSIDZ 0x2eb
  77. #define EFDCMPGT 0x2ec
  78. #define EFDCMPLT 0x2ed
  79. #define EFDCMPEQ 0x2ee
  80. #define EFDCFS 0x2ef
  81. #define EFDCTUI 0x2f4
  82. #define EFDCTSI 0x2f5
  83. #define EFDCTUF 0x2f6
  84. #define EFDCTSF 0x2f7
  85. #define EFDCTUIZ 0x2f8
  86. #define EFDCTSIZ 0x2fa
  87. #define AB 2
  88. #define XA 3
  89. #define XB 4
  90. #define XCR 5
  91. #define NOTYPE 0
  92. #define SIGN_BIT_S (1UL << 31)
  93. #define SIGN_BIT_D (1ULL << 63)
  94. #define FP_EX_MASK (FP_EX_INEXACT | FP_EX_INVALID | FP_EX_DIVZERO | \
  95. FP_EX_UNDERFLOW | FP_EX_OVERFLOW)
  96. static int have_e500_cpu_a005_erratum;
  97. union dw_union {
  98. u64 dp[1];
  99. u32 wp[2];
  100. };
  101. static unsigned long insn_type(unsigned long speinsn)
  102. {
  103. unsigned long ret = NOTYPE;
  104. switch (speinsn & 0x7ff) {
  105. case EFSABS: ret = XA; break;
  106. case EFSADD: ret = AB; break;
  107. case EFSCFD: ret = XB; break;
  108. case EFSCMPEQ: ret = XCR; break;
  109. case EFSCMPGT: ret = XCR; break;
  110. case EFSCMPLT: ret = XCR; break;
  111. case EFSCTSF: ret = XB; break;
  112. case EFSCTSI: ret = XB; break;
  113. case EFSCTSIZ: ret = XB; break;
  114. case EFSCTUF: ret = XB; break;
  115. case EFSCTUI: ret = XB; break;
  116. case EFSCTUIZ: ret = XB; break;
  117. case EFSDIV: ret = AB; break;
  118. case EFSMUL: ret = AB; break;
  119. case EFSNABS: ret = XA; break;
  120. case EFSNEG: ret = XA; break;
  121. case EFSSUB: ret = AB; break;
  122. case EFSCFSI: ret = XB; break;
  123. case EVFSABS: ret = XA; break;
  124. case EVFSADD: ret = AB; break;
  125. case EVFSCMPEQ: ret = XCR; break;
  126. case EVFSCMPGT: ret = XCR; break;
  127. case EVFSCMPLT: ret = XCR; break;
  128. case EVFSCTSF: ret = XB; break;
  129. case EVFSCTSI: ret = XB; break;
  130. case EVFSCTSIZ: ret = XB; break;
  131. case EVFSCTUF: ret = XB; break;
  132. case EVFSCTUI: ret = XB; break;
  133. case EVFSCTUIZ: ret = XB; break;
  134. case EVFSDIV: ret = AB; break;
  135. case EVFSMUL: ret = AB; break;
  136. case EVFSNABS: ret = XA; break;
  137. case EVFSNEG: ret = XA; break;
  138. case EVFSSUB: ret = AB; break;
  139. case EFDABS: ret = XA; break;
  140. case EFDADD: ret = AB; break;
  141. case EFDCFS: ret = XB; break;
  142. case EFDCMPEQ: ret = XCR; break;
  143. case EFDCMPGT: ret = XCR; break;
  144. case EFDCMPLT: ret = XCR; break;
  145. case EFDCTSF: ret = XB; break;
  146. case EFDCTSI: ret = XB; break;
  147. case EFDCTSIDZ: ret = XB; break;
  148. case EFDCTSIZ: ret = XB; break;
  149. case EFDCTUF: ret = XB; break;
  150. case EFDCTUI: ret = XB; break;
  151. case EFDCTUIDZ: ret = XB; break;
  152. case EFDCTUIZ: ret = XB; break;
  153. case EFDDIV: ret = AB; break;
  154. case EFDMUL: ret = AB; break;
  155. case EFDNABS: ret = XA; break;
  156. case EFDNEG: ret = XA; break;
  157. case EFDSUB: ret = AB; break;
  158. }
  159. return ret;
  160. }
  161. int do_spe_mathemu(struct pt_regs *regs)
  162. {
  163. FP_DECL_EX;
  164. int IR, cmp;
  165. unsigned long type, func, fc, fa, fb, src, speinsn;
  166. union dw_union vc, va, vb;
  167. if (get_user(speinsn, (unsigned int __user *) regs->nip))
  168. return -EFAULT;
  169. if ((speinsn >> 26) != EFAPU)
  170. return -EINVAL; /* not an spe instruction */
  171. type = insn_type(speinsn);
  172. if (type == NOTYPE)
  173. goto illegal;
  174. func = speinsn & 0x7ff;
  175. fc = (speinsn >> 21) & 0x1f;
  176. fa = (speinsn >> 16) & 0x1f;
  177. fb = (speinsn >> 11) & 0x1f;
  178. src = (speinsn >> 5) & 0x7;
  179. vc.wp[0] = current->thread.evr[fc];
  180. vc.wp[1] = regs->gpr[fc];
  181. va.wp[0] = current->thread.evr[fa];
  182. va.wp[1] = regs->gpr[fa];
  183. vb.wp[0] = current->thread.evr[fb];
  184. vb.wp[1] = regs->gpr[fb];
  185. __FPU_FPSCR = mfspr(SPRN_SPEFSCR);
  186. pr_debug("speinsn:%08lx spefscr:%08lx\n", speinsn, __FPU_FPSCR);
  187. pr_debug("vc: %08x %08x\n", vc.wp[0], vc.wp[1]);
  188. pr_debug("va: %08x %08x\n", va.wp[0], va.wp[1]);
  189. pr_debug("vb: %08x %08x\n", vb.wp[0], vb.wp[1]);
  190. switch (src) {
  191. case SPFP: {
  192. FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);
  193. switch (type) {
  194. case AB:
  195. case XCR:
  196. FP_UNPACK_SP(SA, va.wp + 1);
  197. case XB:
  198. FP_UNPACK_SP(SB, vb.wp + 1);
  199. break;
  200. case XA:
  201. FP_UNPACK_SP(SA, va.wp + 1);
  202. break;
  203. }
  204. pr_debug("SA: %ld %08lx %ld (%ld)\n", SA_s, SA_f, SA_e, SA_c);
  205. pr_debug("SB: %ld %08lx %ld (%ld)\n", SB_s, SB_f, SB_e, SB_c);
  206. switch (func) {
  207. case EFSABS:
  208. vc.wp[1] = va.wp[1] & ~SIGN_BIT_S;
  209. goto update_regs;
  210. case EFSNABS:
  211. vc.wp[1] = va.wp[1] | SIGN_BIT_S;
  212. goto update_regs;
  213. case EFSNEG:
  214. vc.wp[1] = va.wp[1] ^ SIGN_BIT_S;
  215. goto update_regs;
  216. case EFSADD:
  217. FP_ADD_S(SR, SA, SB);
  218. goto pack_s;
  219. case EFSSUB:
  220. FP_SUB_S(SR, SA, SB);
  221. goto pack_s;
  222. case EFSMUL:
  223. FP_MUL_S(SR, SA, SB);
  224. goto pack_s;
  225. case EFSDIV:
  226. FP_DIV_S(SR, SA, SB);
  227. goto pack_s;
  228. case EFSCMPEQ:
  229. cmp = 0;
  230. goto cmp_s;
  231. case EFSCMPGT:
  232. cmp = 1;
  233. goto cmp_s;
  234. case EFSCMPLT:
  235. cmp = -1;
  236. goto cmp_s;
  237. case EFSCTSF:
  238. case EFSCTUF:
  239. if (SB_c == FP_CLS_NAN) {
  240. vc.wp[1] = 0;
  241. FP_SET_EXCEPTION(FP_EX_INVALID);
  242. } else {
  243. SB_e += (func == EFSCTSF ? 31 : 32);
  244. FP_TO_INT_ROUND_S(vc.wp[1], SB, 32,
  245. (func == EFSCTSF));
  246. }
  247. goto update_regs;
  248. case EFSCFD: {
  249. FP_DECL_D(DB);
  250. FP_CLEAR_EXCEPTIONS;
  251. FP_UNPACK_DP(DB, vb.dp);
  252. pr_debug("DB: %ld %08lx %08lx %ld (%ld)\n",
  253. DB_s, DB_f1, DB_f0, DB_e, DB_c);
  254. FP_CONV(S, D, 1, 2, SR, DB);
  255. goto pack_s;
  256. }
  257. case EFSCTSI:
  258. case EFSCTUI:
  259. if (SB_c == FP_CLS_NAN) {
  260. vc.wp[1] = 0;
  261. FP_SET_EXCEPTION(FP_EX_INVALID);
  262. } else {
  263. FP_TO_INT_ROUND_S(vc.wp[1], SB, 32,
  264. ((func & 0x3) != 0));
  265. }
  266. goto update_regs;
  267. case EFSCTSIZ:
  268. case EFSCTUIZ:
  269. if (SB_c == FP_CLS_NAN) {
  270. vc.wp[1] = 0;
  271. FP_SET_EXCEPTION(FP_EX_INVALID);
  272. } else {
  273. FP_TO_INT_S(vc.wp[1], SB, 32,
  274. ((func & 0x3) != 0));
  275. }
  276. goto update_regs;
  277. default:
  278. goto illegal;
  279. }
  280. break;
  281. pack_s:
  282. pr_debug("SR: %ld %08lx %ld (%ld)\n", SR_s, SR_f, SR_e, SR_c);
  283. FP_PACK_SP(vc.wp + 1, SR);
  284. goto update_regs;
  285. cmp_s:
  286. FP_CMP_S(IR, SA, SB, 3);
  287. if (IR == 3 && (FP_ISSIGNAN_S(SA) || FP_ISSIGNAN_S(SB)))
  288. FP_SET_EXCEPTION(FP_EX_INVALID);
  289. if (IR == cmp) {
  290. IR = 0x4;
  291. } else {
  292. IR = 0;
  293. }
  294. goto update_ccr;
  295. }
  296. case DPFP: {
  297. FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
  298. switch (type) {
  299. case AB:
  300. case XCR:
  301. FP_UNPACK_DP(DA, va.dp);
  302. case XB:
  303. FP_UNPACK_DP(DB, vb.dp);
  304. break;
  305. case XA:
  306. FP_UNPACK_DP(DA, va.dp);
  307. break;
  308. }
  309. pr_debug("DA: %ld %08lx %08lx %ld (%ld)\n",
  310. DA_s, DA_f1, DA_f0, DA_e, DA_c);
  311. pr_debug("DB: %ld %08lx %08lx %ld (%ld)\n",
  312. DB_s, DB_f1, DB_f0, DB_e, DB_c);
  313. switch (func) {
  314. case EFDABS:
  315. vc.dp[0] = va.dp[0] & ~SIGN_BIT_D;
  316. goto update_regs;
  317. case EFDNABS:
  318. vc.dp[0] = va.dp[0] | SIGN_BIT_D;
  319. goto update_regs;
  320. case EFDNEG:
  321. vc.dp[0] = va.dp[0] ^ SIGN_BIT_D;
  322. goto update_regs;
  323. case EFDADD:
  324. FP_ADD_D(DR, DA, DB);
  325. goto pack_d;
  326. case EFDSUB:
  327. FP_SUB_D(DR, DA, DB);
  328. goto pack_d;
  329. case EFDMUL:
  330. FP_MUL_D(DR, DA, DB);
  331. goto pack_d;
  332. case EFDDIV:
  333. FP_DIV_D(DR, DA, DB);
  334. goto pack_d;
  335. case EFDCMPEQ:
  336. cmp = 0;
  337. goto cmp_d;
  338. case EFDCMPGT:
  339. cmp = 1;
  340. goto cmp_d;
  341. case EFDCMPLT:
  342. cmp = -1;
  343. goto cmp_d;
  344. case EFDCTSF:
  345. case EFDCTUF:
  346. if (DB_c == FP_CLS_NAN) {
  347. vc.wp[1] = 0;
  348. FP_SET_EXCEPTION(FP_EX_INVALID);
  349. } else {
  350. DB_e += (func == EFDCTSF ? 31 : 32);
  351. FP_TO_INT_ROUND_D(vc.wp[1], DB, 32,
  352. (func == EFDCTSF));
  353. }
  354. goto update_regs;
  355. case EFDCFS: {
  356. FP_DECL_S(SB);
  357. FP_CLEAR_EXCEPTIONS;
  358. FP_UNPACK_SP(SB, vb.wp + 1);
  359. pr_debug("SB: %ld %08lx %ld (%ld)\n",
  360. SB_s, SB_f, SB_e, SB_c);
  361. FP_CONV(D, S, 2, 1, DR, SB);
  362. goto pack_d;
  363. }
  364. case EFDCTUIDZ:
  365. case EFDCTSIDZ:
  366. if (DB_c == FP_CLS_NAN) {
  367. vc.dp[0] = 0;
  368. FP_SET_EXCEPTION(FP_EX_INVALID);
  369. } else {
  370. FP_TO_INT_D(vc.dp[0], DB, 64,
  371. ((func & 0x1) == 0));
  372. }
  373. goto update_regs;
  374. case EFDCTUI:
  375. case EFDCTSI:
  376. if (DB_c == FP_CLS_NAN) {
  377. vc.wp[1] = 0;
  378. FP_SET_EXCEPTION(FP_EX_INVALID);
  379. } else {
  380. FP_TO_INT_ROUND_D(vc.wp[1], DB, 32,
  381. ((func & 0x3) != 0));
  382. }
  383. goto update_regs;
  384. case EFDCTUIZ:
  385. case EFDCTSIZ:
  386. if (DB_c == FP_CLS_NAN) {
  387. vc.wp[1] = 0;
  388. FP_SET_EXCEPTION(FP_EX_INVALID);
  389. } else {
  390. FP_TO_INT_D(vc.wp[1], DB, 32,
  391. ((func & 0x3) != 0));
  392. }
  393. goto update_regs;
  394. default:
  395. goto illegal;
  396. }
  397. break;
  398. pack_d:
  399. pr_debug("DR: %ld %08lx %08lx %ld (%ld)\n",
  400. DR_s, DR_f1, DR_f0, DR_e, DR_c);
  401. FP_PACK_DP(vc.dp, DR);
  402. goto update_regs;
  403. cmp_d:
  404. FP_CMP_D(IR, DA, DB, 3);
  405. if (IR == 3 && (FP_ISSIGNAN_D(DA) || FP_ISSIGNAN_D(DB)))
  406. FP_SET_EXCEPTION(FP_EX_INVALID);
  407. if (IR == cmp) {
  408. IR = 0x4;
  409. } else {
  410. IR = 0;
  411. }
  412. goto update_ccr;
  413. }
  414. case VCT: {
  415. FP_DECL_S(SA0); FP_DECL_S(SB0); FP_DECL_S(SR0);
  416. FP_DECL_S(SA1); FP_DECL_S(SB1); FP_DECL_S(SR1);
  417. int IR0, IR1;
  418. switch (type) {
  419. case AB:
  420. case XCR:
  421. FP_UNPACK_SP(SA0, va.wp);
  422. FP_UNPACK_SP(SA1, va.wp + 1);
  423. case XB:
  424. FP_UNPACK_SP(SB0, vb.wp);
  425. FP_UNPACK_SP(SB1, vb.wp + 1);
  426. break;
  427. case XA:
  428. FP_UNPACK_SP(SA0, va.wp);
  429. FP_UNPACK_SP(SA1, va.wp + 1);
  430. break;
  431. }
  432. pr_debug("SA0: %ld %08lx %ld (%ld)\n",
  433. SA0_s, SA0_f, SA0_e, SA0_c);
  434. pr_debug("SA1: %ld %08lx %ld (%ld)\n",
  435. SA1_s, SA1_f, SA1_e, SA1_c);
  436. pr_debug("SB0: %ld %08lx %ld (%ld)\n",
  437. SB0_s, SB0_f, SB0_e, SB0_c);
  438. pr_debug("SB1: %ld %08lx %ld (%ld)\n",
  439. SB1_s, SB1_f, SB1_e, SB1_c);
  440. switch (func) {
  441. case EVFSABS:
  442. vc.wp[0] = va.wp[0] & ~SIGN_BIT_S;
  443. vc.wp[1] = va.wp[1] & ~SIGN_BIT_S;
  444. goto update_regs;
  445. case EVFSNABS:
  446. vc.wp[0] = va.wp[0] | SIGN_BIT_S;
  447. vc.wp[1] = va.wp[1] | SIGN_BIT_S;
  448. goto update_regs;
  449. case EVFSNEG:
  450. vc.wp[0] = va.wp[0] ^ SIGN_BIT_S;
  451. vc.wp[1] = va.wp[1] ^ SIGN_BIT_S;
  452. goto update_regs;
  453. case EVFSADD:
  454. FP_ADD_S(SR0, SA0, SB0);
  455. FP_ADD_S(SR1, SA1, SB1);
  456. goto pack_vs;
  457. case EVFSSUB:
  458. FP_SUB_S(SR0, SA0, SB0);
  459. FP_SUB_S(SR1, SA1, SB1);
  460. goto pack_vs;
  461. case EVFSMUL:
  462. FP_MUL_S(SR0, SA0, SB0);
  463. FP_MUL_S(SR1, SA1, SB1);
  464. goto pack_vs;
  465. case EVFSDIV:
  466. FP_DIV_S(SR0, SA0, SB0);
  467. FP_DIV_S(SR1, SA1, SB1);
  468. goto pack_vs;
  469. case EVFSCMPEQ:
  470. cmp = 0;
  471. goto cmp_vs;
  472. case EVFSCMPGT:
  473. cmp = 1;
  474. goto cmp_vs;
  475. case EVFSCMPLT:
  476. cmp = -1;
  477. goto cmp_vs;
  478. case EVFSCTUF:
  479. case EVFSCTSF:
  480. if (SB0_c == FP_CLS_NAN) {
  481. vc.wp[0] = 0;
  482. FP_SET_EXCEPTION(FP_EX_INVALID);
  483. } else {
  484. SB0_e += (func == EVFSCTSF ? 31 : 32);
  485. FP_TO_INT_ROUND_S(vc.wp[0], SB0, 32,
  486. (func == EVFSCTSF));
  487. }
  488. if (SB1_c == FP_CLS_NAN) {
  489. vc.wp[1] = 0;
  490. FP_SET_EXCEPTION(FP_EX_INVALID);
  491. } else {
  492. SB1_e += (func == EVFSCTSF ? 31 : 32);
  493. FP_TO_INT_ROUND_S(vc.wp[1], SB1, 32,
  494. (func == EVFSCTSF));
  495. }
  496. goto update_regs;
  497. case EVFSCTUI:
  498. case EVFSCTSI:
  499. if (SB0_c == FP_CLS_NAN) {
  500. vc.wp[0] = 0;
  501. FP_SET_EXCEPTION(FP_EX_INVALID);
  502. } else {
  503. FP_TO_INT_ROUND_S(vc.wp[0], SB0, 32,
  504. ((func & 0x3) != 0));
  505. }
  506. if (SB1_c == FP_CLS_NAN) {
  507. vc.wp[1] = 0;
  508. FP_SET_EXCEPTION(FP_EX_INVALID);
  509. } else {
  510. FP_TO_INT_ROUND_S(vc.wp[1], SB1, 32,
  511. ((func & 0x3) != 0));
  512. }
  513. goto update_regs;
  514. case EVFSCTUIZ:
  515. case EVFSCTSIZ:
  516. if (SB0_c == FP_CLS_NAN) {
  517. vc.wp[0] = 0;
  518. FP_SET_EXCEPTION(FP_EX_INVALID);
  519. } else {
  520. FP_TO_INT_S(vc.wp[0], SB0, 32,
  521. ((func & 0x3) != 0));
  522. }
  523. if (SB1_c == FP_CLS_NAN) {
  524. vc.wp[1] = 0;
  525. FP_SET_EXCEPTION(FP_EX_INVALID);
  526. } else {
  527. FP_TO_INT_S(vc.wp[1], SB1, 32,
  528. ((func & 0x3) != 0));
  529. }
  530. goto update_regs;
  531. default:
  532. goto illegal;
  533. }
  534. break;
  535. pack_vs:
  536. pr_debug("SR0: %ld %08lx %ld (%ld)\n",
  537. SR0_s, SR0_f, SR0_e, SR0_c);
  538. pr_debug("SR1: %ld %08lx %ld (%ld)\n",
  539. SR1_s, SR1_f, SR1_e, SR1_c);
  540. FP_PACK_SP(vc.wp, SR0);
  541. FP_PACK_SP(vc.wp + 1, SR1);
  542. goto update_regs;
  543. cmp_vs:
  544. {
  545. int ch, cl;
  546. FP_CMP_S(IR0, SA0, SB0, 3);
  547. FP_CMP_S(IR1, SA1, SB1, 3);
  548. if (IR0 == 3 && (FP_ISSIGNAN_S(SA0) || FP_ISSIGNAN_S(SB0)))
  549. FP_SET_EXCEPTION(FP_EX_INVALID);
  550. if (IR1 == 3 && (FP_ISSIGNAN_S(SA1) || FP_ISSIGNAN_S(SB1)))
  551. FP_SET_EXCEPTION(FP_EX_INVALID);
  552. ch = (IR0 == cmp) ? 1 : 0;
  553. cl = (IR1 == cmp) ? 1 : 0;
  554. IR = (ch << 3) | (cl << 2) | ((ch | cl) << 1) |
  555. ((ch & cl) << 0);
  556. goto update_ccr;
  557. }
  558. }
  559. default:
  560. return -EINVAL;
  561. }
  562. update_ccr:
  563. regs->ccr &= ~(15 << ((7 - ((speinsn >> 23) & 0x7)) << 2));
  564. regs->ccr |= (IR << ((7 - ((speinsn >> 23) & 0x7)) << 2));
  565. update_regs:
  566. /*
  567. * If the "invalid" exception sticky bit was set by the
  568. * processor for non-finite input, but was not set before the
  569. * instruction being emulated, clear it. Likewise for the
  570. * "underflow" bit, which may have been set by the processor
  571. * for exact underflow, not just inexact underflow when the
  572. * flag should be set for IEEE 754 semantics. Other sticky
  573. * exceptions will only be set by the processor when they are
  574. * correct according to IEEE 754 semantics, and we must not
  575. * clear sticky bits that were already set before the emulated
  576. * instruction as they represent the user-visible sticky
  577. * exception status. "inexact" traps to kernel are not
  578. * required for IEEE semantics and are not enabled by default,
  579. * so the "inexact" sticky bit may have been set by a previous
  580. * instruction without the kernel being aware of it.
  581. */
  582. __FPU_FPSCR
  583. &= ~(FP_EX_INVALID | FP_EX_UNDERFLOW) | current->thread.spefscr_last;
  584. __FPU_FPSCR |= (FP_CUR_EXCEPTIONS & FP_EX_MASK);
  585. mtspr(SPRN_SPEFSCR, __FPU_FPSCR);
  586. current->thread.spefscr_last = __FPU_FPSCR;
  587. current->thread.evr[fc] = vc.wp[0];
  588. regs->gpr[fc] = vc.wp[1];
  589. pr_debug("ccr = %08lx\n", regs->ccr);
  590. pr_debug("cur exceptions = %08x spefscr = %08lx\n",
  591. FP_CUR_EXCEPTIONS, __FPU_FPSCR);
  592. pr_debug("vc: %08x %08x\n", vc.wp[0], vc.wp[1]);
  593. pr_debug("va: %08x %08x\n", va.wp[0], va.wp[1]);
  594. pr_debug("vb: %08x %08x\n", vb.wp[0], vb.wp[1]);
  595. if (current->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) {
  596. if ((FP_CUR_EXCEPTIONS & FP_EX_DIVZERO)
  597. && (current->thread.fpexc_mode & PR_FP_EXC_DIV))
  598. return 1;
  599. if ((FP_CUR_EXCEPTIONS & FP_EX_OVERFLOW)
  600. && (current->thread.fpexc_mode & PR_FP_EXC_OVF))
  601. return 1;
  602. if ((FP_CUR_EXCEPTIONS & FP_EX_UNDERFLOW)
  603. && (current->thread.fpexc_mode & PR_FP_EXC_UND))
  604. return 1;
  605. if ((FP_CUR_EXCEPTIONS & FP_EX_INEXACT)
  606. && (current->thread.fpexc_mode & PR_FP_EXC_RES))
  607. return 1;
  608. if ((FP_CUR_EXCEPTIONS & FP_EX_INVALID)
  609. && (current->thread.fpexc_mode & PR_FP_EXC_INV))
  610. return 1;
  611. }
  612. return 0;
  613. illegal:
  614. if (have_e500_cpu_a005_erratum) {
  615. /* according to e500 cpu a005 erratum, reissue efp inst */
  616. regs->nip -= 4;
  617. pr_debug("re-issue efp inst: %08lx\n", speinsn);
  618. return 0;
  619. }
  620. printk(KERN_ERR "\nOoops! IEEE-754 compliance handler encountered un-supported instruction.\ninst code: %08lx\n", speinsn);
  621. return -ENOSYS;
  622. }
  623. int speround_handler(struct pt_regs *regs)
  624. {
  625. union dw_union fgpr;
  626. int s_lo, s_hi;
  627. int lo_inexact, hi_inexact;
  628. int fp_result;
  629. unsigned long speinsn, type, fb, fc, fptype, func;
  630. if (get_user(speinsn, (unsigned int __user *) regs->nip))
  631. return -EFAULT;
  632. if ((speinsn >> 26) != 4)
  633. return -EINVAL; /* not an spe instruction */
  634. func = speinsn & 0x7ff;
  635. type = insn_type(func);
  636. if (type == XCR) return -ENOSYS;
  637. __FPU_FPSCR = mfspr(SPRN_SPEFSCR);
  638. pr_debug("speinsn:%08lx spefscr:%08lx\n", speinsn, __FPU_FPSCR);
  639. fptype = (speinsn >> 5) & 0x7;
  640. /* No need to round if the result is exact */
  641. lo_inexact = __FPU_FPSCR & (SPEFSCR_FG | SPEFSCR_FX);
  642. hi_inexact = __FPU_FPSCR & (SPEFSCR_FGH | SPEFSCR_FXH);
  643. if (!(lo_inexact || (hi_inexact && fptype == VCT)))
  644. return 0;
  645. fc = (speinsn >> 21) & 0x1f;
  646. s_lo = regs->gpr[fc] & SIGN_BIT_S;
  647. s_hi = current->thread.evr[fc] & SIGN_BIT_S;
  648. fgpr.wp[0] = current->thread.evr[fc];
  649. fgpr.wp[1] = regs->gpr[fc];
  650. fb = (speinsn >> 11) & 0x1f;
  651. switch (func) {
  652. case EFSCTUIZ:
  653. case EFSCTSIZ:
  654. case EVFSCTUIZ:
  655. case EVFSCTSIZ:
  656. case EFDCTUIDZ:
  657. case EFDCTSIDZ:
  658. case EFDCTUIZ:
  659. case EFDCTSIZ:
  660. /*
  661. * These instructions always round to zero,
  662. * independent of the rounding mode.
  663. */
  664. return 0;
  665. case EFSCTUI:
  666. case EFSCTUF:
  667. case EVFSCTUI:
  668. case EVFSCTUF:
  669. case EFDCTUI:
  670. case EFDCTUF:
  671. fp_result = 0;
  672. s_lo = 0;
  673. s_hi = 0;
  674. break;
  675. case EFSCTSI:
  676. case EFSCTSF:
  677. fp_result = 0;
  678. /* Recover the sign of a zero result if possible. */
  679. if (fgpr.wp[1] == 0)
  680. s_lo = regs->gpr[fb] & SIGN_BIT_S;
  681. break;
  682. case EVFSCTSI:
  683. case EVFSCTSF:
  684. fp_result = 0;
  685. /* Recover the sign of a zero result if possible. */
  686. if (fgpr.wp[1] == 0)
  687. s_lo = regs->gpr[fb] & SIGN_BIT_S;
  688. if (fgpr.wp[0] == 0)
  689. s_hi = current->thread.evr[fb] & SIGN_BIT_S;
  690. break;
  691. case EFDCTSI:
  692. case EFDCTSF:
  693. fp_result = 0;
  694. s_hi = s_lo;
  695. /* Recover the sign of a zero result if possible. */
  696. if (fgpr.wp[1] == 0)
  697. s_hi = current->thread.evr[fb] & SIGN_BIT_S;
  698. break;
  699. default:
  700. fp_result = 1;
  701. break;
  702. }
  703. pr_debug("round fgpr: %08x %08x\n", fgpr.wp[0], fgpr.wp[1]);
  704. switch (fptype) {
  705. /* Since SPE instructions on E500 core can handle round to nearest
  706. * and round toward zero with IEEE-754 complied, we just need
  707. * to handle round toward +Inf and round toward -Inf by software.
  708. */
  709. case SPFP:
  710. if ((FP_ROUNDMODE) == FP_RND_PINF) {
  711. if (!s_lo) fgpr.wp[1]++; /* Z > 0, choose Z1 */
  712. } else { /* round to -Inf */
  713. if (s_lo) {
  714. if (fp_result)
  715. fgpr.wp[1]++; /* Z < 0, choose Z2 */
  716. else
  717. fgpr.wp[1]--; /* Z < 0, choose Z2 */
  718. }
  719. }
  720. break;
  721. case DPFP:
  722. if (FP_ROUNDMODE == FP_RND_PINF) {
  723. if (!s_hi) {
  724. if (fp_result)
  725. fgpr.dp[0]++; /* Z > 0, choose Z1 */
  726. else
  727. fgpr.wp[1]++; /* Z > 0, choose Z1 */
  728. }
  729. } else { /* round to -Inf */
  730. if (s_hi) {
  731. if (fp_result)
  732. fgpr.dp[0]++; /* Z < 0, choose Z2 */
  733. else
  734. fgpr.wp[1]--; /* Z < 0, choose Z2 */
  735. }
  736. }
  737. break;
  738. case VCT:
  739. if (FP_ROUNDMODE == FP_RND_PINF) {
  740. if (lo_inexact && !s_lo)
  741. fgpr.wp[1]++; /* Z_low > 0, choose Z1 */
  742. if (hi_inexact && !s_hi)
  743. fgpr.wp[0]++; /* Z_high word > 0, choose Z1 */
  744. } else { /* round to -Inf */
  745. if (lo_inexact && s_lo) {
  746. if (fp_result)
  747. fgpr.wp[1]++; /* Z_low < 0, choose Z2 */
  748. else
  749. fgpr.wp[1]--; /* Z_low < 0, choose Z2 */
  750. }
  751. if (hi_inexact && s_hi) {
  752. if (fp_result)
  753. fgpr.wp[0]++; /* Z_high < 0, choose Z2 */
  754. else
  755. fgpr.wp[0]--; /* Z_high < 0, choose Z2 */
  756. }
  757. }
  758. break;
  759. default:
  760. return -EINVAL;
  761. }
  762. current->thread.evr[fc] = fgpr.wp[0];
  763. regs->gpr[fc] = fgpr.wp[1];
  764. pr_debug(" to fgpr: %08x %08x\n", fgpr.wp[0], fgpr.wp[1]);
  765. if (current->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
  766. return (current->thread.fpexc_mode & PR_FP_EXC_RES) ? 1 : 0;
  767. return 0;
  768. }
  769. int __init spe_mathemu_init(void)
  770. {
  771. u32 pvr, maj, min;
  772. pvr = mfspr(SPRN_PVR);
  773. if ((PVR_VER(pvr) == PVR_VER_E500V1) ||
  774. (PVR_VER(pvr) == PVR_VER_E500V2)) {
  775. maj = PVR_MAJ(pvr);
  776. min = PVR_MIN(pvr);
  777. /*
  778. * E500 revision below 1.1, 2.3, 3.1, 4.1, 5.1
  779. * need cpu a005 errata workaround
  780. */
  781. switch (maj) {
  782. case 1:
  783. if (min < 1)
  784. have_e500_cpu_a005_erratum = 1;
  785. break;
  786. case 2:
  787. if (min < 3)
  788. have_e500_cpu_a005_erratum = 1;
  789. break;
  790. case 3:
  791. case 4:
  792. case 5:
  793. if (min < 1)
  794. have_e500_cpu_a005_erratum = 1;
  795. break;
  796. default:
  797. break;
  798. }
  799. }
  800. return 0;
  801. }
  802. module_init(spe_mathemu_init);