iommu.c 7.1 KB

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  1. /*
  2. * Copyright (C) 2005-2008, PA Semi, Inc
  3. *
  4. * Maintained by: Olof Johansson <olof@lixom.net>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. */
  19. #undef DEBUG
  20. #include <linux/memblock.h>
  21. #include <linux/types.h>
  22. #include <linux/spinlock.h>
  23. #include <linux/pci.h>
  24. #include <asm/iommu.h>
  25. #include <asm/machdep.h>
  26. #include <asm/firmware.h>
  27. #include "pasemi.h"
  28. #define IOBMAP_PAGE_SHIFT 12
  29. #define IOBMAP_PAGE_SIZE (1 << IOBMAP_PAGE_SHIFT)
  30. #define IOBMAP_PAGE_MASK (IOBMAP_PAGE_SIZE - 1)
  31. #define IOB_BASE 0xe0000000
  32. #define IOB_SIZE 0x3000
  33. /* Configuration registers */
  34. #define IOBCAP_REG 0x40
  35. #define IOBCOM_REG 0x100
  36. /* Enable IOB address translation */
  37. #define IOBCOM_ATEN 0x00000100
  38. /* Address decode configuration register */
  39. #define IOB_AD_REG 0x14c
  40. /* IOBCOM_AD_REG fields */
  41. #define IOB_AD_VGPRT 0x00000e00
  42. #define IOB_AD_VGAEN 0x00000100
  43. /* Direct mapping settings */
  44. #define IOB_AD_MPSEL_MASK 0x00000030
  45. #define IOB_AD_MPSEL_B38 0x00000000
  46. #define IOB_AD_MPSEL_B40 0x00000010
  47. #define IOB_AD_MPSEL_B42 0x00000020
  48. /* Translation window size / enable */
  49. #define IOB_AD_TRNG_MASK 0x00000003
  50. #define IOB_AD_TRNG_256M 0x00000000
  51. #define IOB_AD_TRNG_2G 0x00000001
  52. #define IOB_AD_TRNG_128G 0x00000003
  53. #define IOB_TABLEBASE_REG 0x154
  54. /* Base of the 64 4-byte L1 registers */
  55. #define IOB_XLT_L1_REGBASE 0x2b00
  56. /* Register to invalidate TLB entries */
  57. #define IOB_AT_INVAL_TLB_REG 0x2d00
  58. /* The top two bits of the level 1 entry contains valid and type flags */
  59. #define IOBMAP_L1E_V 0x40000000
  60. #define IOBMAP_L1E_V_B 0x80000000
  61. /* For big page entries, the bottom two bits contains flags */
  62. #define IOBMAP_L1E_BIG_CACHED 0x00000002
  63. #define IOBMAP_L1E_BIG_PRIORITY 0x00000001
  64. /* For regular level 2 entries, top 2 bits contain valid and cache flags */
  65. #define IOBMAP_L2E_V 0x80000000
  66. #define IOBMAP_L2E_V_CACHED 0xc0000000
  67. static void __iomem *iob;
  68. static u32 iob_l1_emptyval;
  69. static u32 iob_l2_emptyval;
  70. static u32 *iob_l2_base;
  71. static struct iommu_table iommu_table_iobmap;
  72. static int iommu_table_iobmap_inited;
  73. static int iobmap_build(struct iommu_table *tbl, long index,
  74. long npages, unsigned long uaddr,
  75. enum dma_data_direction direction,
  76. struct dma_attrs *attrs)
  77. {
  78. u32 *ip;
  79. u32 rpn;
  80. unsigned long bus_addr;
  81. pr_debug("iobmap: build at: %lx, %lx, addr: %lx\n", index, npages, uaddr);
  82. bus_addr = (tbl->it_offset + index) << IOBMAP_PAGE_SHIFT;
  83. ip = ((u32 *)tbl->it_base) + index;
  84. while (npages--) {
  85. rpn = __pa(uaddr) >> IOBMAP_PAGE_SHIFT;
  86. *(ip++) = IOBMAP_L2E_V | rpn;
  87. /* invalidate tlb, can be optimized more */
  88. out_le32(iob+IOB_AT_INVAL_TLB_REG, bus_addr >> 14);
  89. uaddr += IOBMAP_PAGE_SIZE;
  90. bus_addr += IOBMAP_PAGE_SIZE;
  91. }
  92. return 0;
  93. }
  94. static void iobmap_free(struct iommu_table *tbl, long index,
  95. long npages)
  96. {
  97. u32 *ip;
  98. unsigned long bus_addr;
  99. pr_debug("iobmap: free at: %lx, %lx\n", index, npages);
  100. bus_addr = (tbl->it_offset + index) << IOBMAP_PAGE_SHIFT;
  101. ip = ((u32 *)tbl->it_base) + index;
  102. while (npages--) {
  103. *(ip++) = iob_l2_emptyval;
  104. /* invalidate tlb, can be optimized more */
  105. out_le32(iob+IOB_AT_INVAL_TLB_REG, bus_addr >> 14);
  106. bus_addr += IOBMAP_PAGE_SIZE;
  107. }
  108. }
  109. static struct iommu_table_ops iommu_table_iobmap_ops = {
  110. .set = iobmap_build,
  111. .clear = iobmap_free
  112. };
  113. static void iommu_table_iobmap_setup(void)
  114. {
  115. pr_debug(" -> %s\n", __func__);
  116. iommu_table_iobmap.it_busno = 0;
  117. iommu_table_iobmap.it_offset = 0;
  118. iommu_table_iobmap.it_page_shift = IOBMAP_PAGE_SHIFT;
  119. /* it_size is in number of entries */
  120. iommu_table_iobmap.it_size =
  121. 0x80000000 >> iommu_table_iobmap.it_page_shift;
  122. /* Initialize the common IOMMU code */
  123. iommu_table_iobmap.it_base = (unsigned long)iob_l2_base;
  124. iommu_table_iobmap.it_index = 0;
  125. /* XXXOJN tune this to avoid IOB cache invals.
  126. * Should probably be 8 (64 bytes)
  127. */
  128. iommu_table_iobmap.it_blocksize = 4;
  129. iommu_table_iobmap.it_ops = &iommu_table_iobmap_ops;
  130. iommu_init_table(&iommu_table_iobmap, 0);
  131. pr_debug(" <- %s\n", __func__);
  132. }
  133. static void pci_dma_bus_setup_pasemi(struct pci_bus *bus)
  134. {
  135. pr_debug("pci_dma_bus_setup, bus %p, bus->self %p\n", bus, bus->self);
  136. if (!iommu_table_iobmap_inited) {
  137. iommu_table_iobmap_inited = 1;
  138. iommu_table_iobmap_setup();
  139. }
  140. }
  141. static void pci_dma_dev_setup_pasemi(struct pci_dev *dev)
  142. {
  143. pr_debug("pci_dma_dev_setup, dev %p (%s)\n", dev, pci_name(dev));
  144. #if !defined(CONFIG_PPC_PASEMI_IOMMU_DMA_FORCE)
  145. /* For non-LPAR environment, don't translate anything for the DMA
  146. * engine. The exception to this is if the user has enabled
  147. * CONFIG_PPC_PASEMI_IOMMU_DMA_FORCE at build time.
  148. */
  149. if (dev->vendor == 0x1959 && dev->device == 0xa007 &&
  150. !firmware_has_feature(FW_FEATURE_LPAR)) {
  151. dev->dev.archdata.dma_ops = &dma_direct_ops;
  152. return;
  153. }
  154. #endif
  155. set_iommu_table_base(&dev->dev, &iommu_table_iobmap);
  156. }
  157. int __init iob_init(struct device_node *dn)
  158. {
  159. unsigned long tmp;
  160. u32 regword;
  161. int i;
  162. pr_debug(" -> %s\n", __func__);
  163. /* Allocate a spare page to map all invalid IOTLB pages. */
  164. tmp = memblock_alloc(IOBMAP_PAGE_SIZE, IOBMAP_PAGE_SIZE);
  165. if (!tmp)
  166. panic("IOBMAP: Cannot allocate spare page!");
  167. /* Empty l1 is marked invalid */
  168. iob_l1_emptyval = 0;
  169. /* Empty l2 is mapped to dummy page */
  170. iob_l2_emptyval = IOBMAP_L2E_V | (tmp >> IOBMAP_PAGE_SHIFT);
  171. iob = ioremap(IOB_BASE, IOB_SIZE);
  172. if (!iob)
  173. panic("IOBMAP: Cannot map registers!");
  174. /* setup direct mapping of the L1 entries */
  175. for (i = 0; i < 64; i++) {
  176. /* Each L1 covers 32MB, i.e. 8K entries = 32K of ram */
  177. regword = IOBMAP_L1E_V | (__pa(iob_l2_base + i*0x2000) >> 12);
  178. out_le32(iob+IOB_XLT_L1_REGBASE+i*4, regword);
  179. }
  180. /* set 2GB translation window, based at 0 */
  181. regword = in_le32(iob+IOB_AD_REG);
  182. regword &= ~IOB_AD_TRNG_MASK;
  183. regword |= IOB_AD_TRNG_2G;
  184. out_le32(iob+IOB_AD_REG, regword);
  185. /* Enable translation */
  186. regword = in_le32(iob+IOBCOM_REG);
  187. regword |= IOBCOM_ATEN;
  188. out_le32(iob+IOBCOM_REG, regword);
  189. pr_debug(" <- %s\n", __func__);
  190. return 0;
  191. }
  192. /* These are called very early. */
  193. void __init iommu_init_early_pasemi(void)
  194. {
  195. int iommu_off;
  196. #ifndef CONFIG_PPC_PASEMI_IOMMU
  197. iommu_off = 1;
  198. #else
  199. iommu_off = of_chosen &&
  200. of_get_property(of_chosen, "linux,iommu-off", NULL);
  201. #endif
  202. if (iommu_off)
  203. return;
  204. iob_init(NULL);
  205. pasemi_pci_controller_ops.dma_dev_setup = pci_dma_dev_setup_pasemi;
  206. pasemi_pci_controller_ops.dma_bus_setup = pci_dma_bus_setup_pasemi;
  207. set_pci_dma_ops(&dma_iommu_ops);
  208. }
  209. void __init alloc_iobmap_l2(void)
  210. {
  211. #ifndef CONFIG_PPC_PASEMI_IOMMU
  212. return;
  213. #endif
  214. /* For 2G space, 8x64 pages (2^21 bytes) is max total l2 size */
  215. iob_l2_base = (u32 *)__va(memblock_alloc_base(1UL<<21, 1UL<<21, 0x80000000));
  216. printk(KERN_INFO "IOBMAP L2 allocated at: %p\n", iob_l2_base);
  217. }