board-magicpanelr2.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393
  1. /*
  2. * linux/arch/sh/boards/magicpanel/setup.c
  3. *
  4. * Copyright (C) 2007 Markus Brunner, Mark Jonas
  5. *
  6. * Magic Panel Release 2 board setup
  7. *
  8. * This file is subject to the terms and conditions of the GNU General Public
  9. * License. See the file "COPYING" in the main directory of this archive
  10. * for more details.
  11. */
  12. #include <linux/init.h>
  13. #include <linux/irq.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/delay.h>
  16. #include <linux/gpio.h>
  17. #include <linux/regulator/fixed.h>
  18. #include <linux/regulator/machine.h>
  19. #include <linux/smsc911x.h>
  20. #include <linux/mtd/mtd.h>
  21. #include <linux/mtd/partitions.h>
  22. #include <linux/mtd/physmap.h>
  23. #include <linux/mtd/map.h>
  24. #include <linux/sh_intc.h>
  25. #include <mach/magicpanelr2.h>
  26. #include <asm/heartbeat.h>
  27. #include <cpu/sh7720.h>
  28. /* Dummy supplies, where voltage doesn't matter */
  29. static struct regulator_consumer_supply dummy_supplies[] = {
  30. REGULATOR_SUPPLY("vddvario", "smsc911x"),
  31. REGULATOR_SUPPLY("vdd33a", "smsc911x"),
  32. };
  33. #define LAN9115_READY (__raw_readl(0xA8000084UL) & 0x00000001UL)
  34. /* Wait until reset finished. Timeout is 100ms. */
  35. static int __init ethernet_reset_finished(void)
  36. {
  37. int i;
  38. if (LAN9115_READY)
  39. return 1;
  40. for (i = 0; i < 10; ++i) {
  41. mdelay(10);
  42. if (LAN9115_READY)
  43. return 1;
  44. }
  45. return 0;
  46. }
  47. static void __init reset_ethernet(void)
  48. {
  49. /* PMDR: LAN_RESET=on */
  50. CLRBITS_OUTB(0x10, PORT_PMDR);
  51. udelay(200);
  52. /* PMDR: LAN_RESET=off */
  53. SETBITS_OUTB(0x10, PORT_PMDR);
  54. }
  55. static void __init setup_chip_select(void)
  56. {
  57. /* CS2: LAN (0x08000000 - 0x0bffffff) */
  58. /* no idle cycles, normal space, 8 bit data bus */
  59. __raw_writel(0x36db0400, CS2BCR);
  60. /* (SW:1.5 WR:3 HW:1.5), ext. wait */
  61. __raw_writel(0x000003c0, CS2WCR);
  62. /* CS4: CAN1 (0xb0000000 - 0xb3ffffff) */
  63. /* no idle cycles, normal space, 8 bit data bus */
  64. __raw_writel(0x00000200, CS4BCR);
  65. /* (SW:1.5 WR:3 HW:1.5), ext. wait */
  66. __raw_writel(0x00100981, CS4WCR);
  67. /* CS5a: CAN2 (0xb4000000 - 0xb5ffffff) */
  68. /* no idle cycles, normal space, 8 bit data bus */
  69. __raw_writel(0x00000200, CS5ABCR);
  70. /* (SW:1.5 WR:3 HW:1.5), ext. wait */
  71. __raw_writel(0x00100981, CS5AWCR);
  72. /* CS5b: CAN3 (0xb6000000 - 0xb7ffffff) */
  73. /* no idle cycles, normal space, 8 bit data bus */
  74. __raw_writel(0x00000200, CS5BBCR);
  75. /* (SW:1.5 WR:3 HW:1.5), ext. wait */
  76. __raw_writel(0x00100981, CS5BWCR);
  77. /* CS6a: Rotary (0xb8000000 - 0xb9ffffff) */
  78. /* no idle cycles, normal space, 8 bit data bus */
  79. __raw_writel(0x00000200, CS6ABCR);
  80. /* (SW:1.5 WR:3 HW:1.5), no ext. wait */
  81. __raw_writel(0x001009C1, CS6AWCR);
  82. }
  83. static void __init setup_port_multiplexing(void)
  84. {
  85. /* A7 GPO(LED8); A6 GPO(LED7); A5 GPO(LED6); A4 GPO(LED5);
  86. * A3 GPO(LED4); A2 GPO(LED3); A1 GPO(LED2); A0 GPO(LED1);
  87. */
  88. __raw_writew(0x5555, PORT_PACR); /* 01 01 01 01 01 01 01 01 */
  89. /* B7 GPO(RST4); B6 GPO(RST3); B5 GPO(RST2); B4 GPO(RST1);
  90. * B3 GPO(PB3); B2 GPO(PB2); B1 GPO(PB1); B0 GPO(PB0);
  91. */
  92. __raw_writew(0x5555, PORT_PBCR); /* 01 01 01 01 01 01 01 01 */
  93. /* C7 GPO(PC7); C6 GPO(PC6); C5 GPO(PC5); C4 GPO(PC4);
  94. * C3 LCD_DATA3; C2 LCD_DATA2; C1 LCD_DATA1; C0 LCD_DATA0;
  95. */
  96. __raw_writew(0x5500, PORT_PCCR); /* 01 01 01 01 00 00 00 00 */
  97. /* D7 GPO(PD7); D6 GPO(PD6); D5 GPO(PD5); D4 GPO(PD4);
  98. * D3 GPO(PD3); D2 GPO(PD2); D1 GPO(PD1); D0 GPO(PD0);
  99. */
  100. __raw_writew(0x5555, PORT_PDCR); /* 01 01 01 01 01 01 01 01 */
  101. /* E7 (x); E6 GPI(nu); E5 GPI(nu); E4 LCD_M_DISP;
  102. * E3 LCD_CL1; E2 LCD_CL2; E1 LCD_DON; E0 LCD_FLM;
  103. */
  104. __raw_writew(0x3C00, PORT_PECR); /* 00 11 11 00 00 00 00 00 */
  105. /* F7 (x); F6 DA1(VLCD); F5 DA0(nc); F4 AN3;
  106. * F3 AN2(MID_AD); F2 AN1(EARTH_AD); F1 AN0(TEMP); F0 GPI+(nc);
  107. */
  108. __raw_writew(0x0002, PORT_PFCR); /* 00 00 00 00 00 00 00 10 */
  109. /* G7 (x); G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ); G4 GPI(KEY2);
  110. * G3 GPI(KEY1); G2 GPO(LED11); G1 GPO(LED10); G0 GPO(LED9);
  111. */
  112. __raw_writew(0x03D5, PORT_PGCR); /* 00 00 00 11 11 01 01 01 */
  113. /* H7 (x); H6 /RAS(BRAS); H5 /CAS(BCAS); H4 CKE(BCKE);
  114. * H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR; H0 USB1_PWR;
  115. */
  116. __raw_writew(0x0050, PORT_PHCR); /* 00 00 00 00 01 01 00 00 */
  117. /* J7 (x); J6 AUDCK; J5 ASEBRKAK; J4 AUDATA3;
  118. * J3 AUDATA2; J2 AUDATA1; J1 AUDATA0; J0 AUDSYNC;
  119. */
  120. __raw_writew(0x0000, PORT_PJCR); /* 00 00 00 00 00 00 00 00 */
  121. /* K7 (x); K6 (x); K5 (x); K4 (x);
  122. * K3 PINT7(/PWR2); K2 PINT6(/PWR1); K1 PINT5(nu); K0 PINT4(FLASH_READY)
  123. */
  124. __raw_writew(0x00FF, PORT_PKCR); /* 00 00 00 00 11 11 11 11 */
  125. /* L7 TRST; L6 TMS; L5 TDO; L4 TDI;
  126. * L3 TCK; L2 (x); L1 (x); L0 (x);
  127. */
  128. __raw_writew(0x0000, PORT_PLCR); /* 00 00 00 00 00 00 00 00 */
  129. /* M7 GPO(CURRENT_SINK); M6 GPO(PWR_SWITCH); M5 GPO(LAN_SPEED);
  130. * M4 GPO(LAN_RESET); M3 GPO(BUZZER); M2 GPO(LCD_BL);
  131. * M1 CS5B(CAN3_CS); M0 GPI+(nc);
  132. */
  133. __raw_writew(0x5552, PORT_PMCR); /* 01 01 01 01 01 01 00 10 */
  134. /* CURRENT_SINK=off, PWR_SWITCH=off, LAN_SPEED=100MBit,
  135. * LAN_RESET=off, BUZZER=off, LCD_BL=off
  136. */
  137. #if CONFIG_SH_MAGIC_PANEL_R2_VERSION == 2
  138. __raw_writeb(0x30, PORT_PMDR);
  139. #elif CONFIG_SH_MAGIC_PANEL_R2_VERSION == 3
  140. __raw_writeb(0xF0, PORT_PMDR);
  141. #else
  142. #error Unknown revision of PLATFORM_MP_R2
  143. #endif
  144. /* P7 (x); P6 (x); P5 (x);
  145. * P4 GPO(nu); P3 IRQ3(LAN_IRQ); P2 IRQ2(CAN3_IRQ);
  146. * P1 IRQ1(CAN2_IRQ); P0 IRQ0(CAN1_IRQ)
  147. */
  148. __raw_writew(0x0100, PORT_PPCR); /* 00 00 00 01 00 00 00 00 */
  149. __raw_writeb(0x10, PORT_PPDR);
  150. /* R7 A25; R6 A24; R5 A23; R4 A22;
  151. * R3 A21; R2 A20; R1 A19; R0 A0;
  152. */
  153. gpio_request(GPIO_FN_A25, NULL);
  154. gpio_request(GPIO_FN_A24, NULL);
  155. gpio_request(GPIO_FN_A23, NULL);
  156. gpio_request(GPIO_FN_A22, NULL);
  157. gpio_request(GPIO_FN_A21, NULL);
  158. gpio_request(GPIO_FN_A20, NULL);
  159. gpio_request(GPIO_FN_A19, NULL);
  160. gpio_request(GPIO_FN_A0, NULL);
  161. /* S7 (x); S6 (x); S5 (x); S4 GPO(EEPROM_CS2);
  162. * S3 GPO(EEPROM_CS1); S2 SIOF0_TXD; S1 SIOF0_RXD; S0 SIOF0_SCK;
  163. */
  164. __raw_writew(0x0140, PORT_PSCR); /* 00 00 00 01 01 00 00 00 */
  165. /* T7 (x); T6 (x); T5 (x); T4 COM1_CTS;
  166. * T3 COM1_RTS; T2 COM1_TXD; T1 COM1_RXD; T0 GPO(WDOG)
  167. */
  168. __raw_writew(0x0001, PORT_PTCR); /* 00 00 00 00 00 00 00 01 */
  169. /* U7 (x); U6 (x); U5 (x); U4 GPI+(/AC_FAULT);
  170. * U3 GPO(TOUCH_CS); U2 TOUCH_TXD; U1 TOUCH_RXD; U0 TOUCH_SCK;
  171. */
  172. __raw_writew(0x0240, PORT_PUCR); /* 00 00 00 10 01 00 00 00 */
  173. /* V7 (x); V6 (x); V5 (x); V4 GPO(MID2);
  174. * V3 GPO(MID1); V2 CARD_TxD; V1 CARD_RxD; V0 GPI+(/BAT_FAULT);
  175. */
  176. __raw_writew(0x0142, PORT_PVCR); /* 00 00 00 01 01 00 00 10 */
  177. }
  178. static void __init mpr2_setup(char **cmdline_p)
  179. {
  180. /* set Pin Select Register A:
  181. * /PCC_CD1, /PCC_CD2, PCC_BVD1, PCC_BVD2,
  182. * /IOIS16, IRQ4, IRQ5, USB1d_SUSPEND
  183. */
  184. __raw_writew(0xAABC, PORT_PSELA);
  185. /* set Pin Select Register B:
  186. * /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC,
  187. * LCD_VEPWC, IIC_SDA, IIC_SCL, Reserved
  188. */
  189. __raw_writew(0x3C00, PORT_PSELB);
  190. /* set Pin Select Register C:
  191. * SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved
  192. */
  193. __raw_writew(0x0000, PORT_PSELC);
  194. /* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK,
  195. * Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved
  196. */
  197. __raw_writew(0x0000, PORT_PSELD);
  198. /* set USB TxRx Control: Reserved, DRV, Reserved, USB_TRANS, USB_SEL */
  199. __raw_writew(0x0101, PORT_UTRCTL);
  200. /* set USB Clock Control: USSCS, USSTB, Reserved (HighByte always A5) */
  201. __raw_writew(0xA5C0, PORT_UCLKCR_W);
  202. setup_chip_select();
  203. setup_port_multiplexing();
  204. reset_ethernet();
  205. printk(KERN_INFO "Magic Panel Release 2 A.%i\n",
  206. CONFIG_SH_MAGIC_PANEL_R2_VERSION);
  207. if (ethernet_reset_finished() == 0)
  208. printk(KERN_WARNING "Ethernet not ready\n");
  209. }
  210. static struct resource smsc911x_resources[] = {
  211. [0] = {
  212. .start = 0xa8000000,
  213. .end = 0xabffffff,
  214. .flags = IORESOURCE_MEM,
  215. },
  216. [1] = {
  217. .start = evt2irq(0x660),
  218. .end = evt2irq(0x660),
  219. .flags = IORESOURCE_IRQ,
  220. },
  221. };
  222. static struct smsc911x_platform_config smsc911x_config = {
  223. .phy_interface = PHY_INTERFACE_MODE_MII,
  224. .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
  225. .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
  226. .flags = SMSC911X_USE_32BIT,
  227. };
  228. static struct platform_device smsc911x_device = {
  229. .name = "smsc911x",
  230. .id = -1,
  231. .num_resources = ARRAY_SIZE(smsc911x_resources),
  232. .resource = smsc911x_resources,
  233. .dev = {
  234. .platform_data = &smsc911x_config,
  235. },
  236. };
  237. static struct resource heartbeat_resources[] = {
  238. [0] = {
  239. .start = PA_LED,
  240. .end = PA_LED,
  241. .flags = IORESOURCE_MEM,
  242. },
  243. };
  244. static struct heartbeat_data heartbeat_data = {
  245. .flags = HEARTBEAT_INVERTED,
  246. };
  247. static struct platform_device heartbeat_device = {
  248. .name = "heartbeat",
  249. .id = -1,
  250. .dev = {
  251. .platform_data = &heartbeat_data,
  252. },
  253. .num_resources = ARRAY_SIZE(heartbeat_resources),
  254. .resource = heartbeat_resources,
  255. };
  256. static struct mtd_partition mpr2_partitions[] = {
  257. /* Reserved for bootloader, read-only */
  258. {
  259. .name = "Bootloader",
  260. .offset = 0x00000000UL,
  261. .size = MPR2_MTD_BOOTLOADER_SIZE,
  262. .mask_flags = MTD_WRITEABLE,
  263. },
  264. /* Reserved for kernel image */
  265. {
  266. .name = "Kernel",
  267. .offset = MTDPART_OFS_NXTBLK,
  268. .size = MPR2_MTD_KERNEL_SIZE,
  269. },
  270. /* Rest is used for Flash FS */
  271. {
  272. .name = "Flash_FS",
  273. .offset = MTDPART_OFS_NXTBLK,
  274. .size = MTDPART_SIZ_FULL,
  275. }
  276. };
  277. static struct physmap_flash_data flash_data = {
  278. .parts = mpr2_partitions,
  279. .nr_parts = ARRAY_SIZE(mpr2_partitions),
  280. .width = 2,
  281. };
  282. static struct resource flash_resource = {
  283. .start = 0x00000000,
  284. .end = 0x2000000UL,
  285. .flags = IORESOURCE_MEM,
  286. };
  287. static struct platform_device flash_device = {
  288. .name = "physmap-flash",
  289. .id = -1,
  290. .resource = &flash_resource,
  291. .num_resources = 1,
  292. .dev = {
  293. .platform_data = &flash_data,
  294. },
  295. };
  296. /*
  297. * Add all resources to the platform_device
  298. */
  299. static struct platform_device *mpr2_devices[] __initdata = {
  300. &heartbeat_device,
  301. &smsc911x_device,
  302. &flash_device,
  303. };
  304. static int __init mpr2_devices_setup(void)
  305. {
  306. regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
  307. return platform_add_devices(mpr2_devices, ARRAY_SIZE(mpr2_devices));
  308. }
  309. device_initcall(mpr2_devices_setup);
  310. /*
  311. * Initialize IRQ setting
  312. */
  313. static void __init init_mpr2_IRQ(void)
  314. {
  315. plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-5 */
  316. irq_set_irq_type(evt2irq(0x600), IRQ_TYPE_LEVEL_LOW); /* IRQ0 CAN1 */
  317. irq_set_irq_type(evt2irq(0x620), IRQ_TYPE_LEVEL_LOW); /* IRQ1 CAN2 */
  318. irq_set_irq_type(evt2irq(0x640), IRQ_TYPE_LEVEL_LOW); /* IRQ2 CAN3 */
  319. irq_set_irq_type(evt2irq(0x660), IRQ_TYPE_LEVEL_LOW); /* IRQ3 SMSC9115 */
  320. irq_set_irq_type(evt2irq(0x680), IRQ_TYPE_EDGE_RISING); /* IRQ4 touchscreen */
  321. irq_set_irq_type(evt2irq(0x6a0), IRQ_TYPE_EDGE_FALLING); /* IRQ5 touchscreen */
  322. intc_set_priority(evt2irq(0x600), 13); /* IRQ0 CAN1 */
  323. intc_set_priority(evt2irq(0x620), 13); /* IRQ0 CAN2 */
  324. intc_set_priority(evt2irq(0x640), 13); /* IRQ0 CAN3 */
  325. intc_set_priority(evt2irq(0x660), 6); /* IRQ3 SMSC9115 */
  326. }
  327. /*
  328. * The Machine Vector
  329. */
  330. static struct sh_machine_vector mv_mpr2 __initmv = {
  331. .mv_name = "mpr2",
  332. .mv_setup = mpr2_setup,
  333. .mv_init_irq = init_mpr2_IRQ,
  334. };