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CooCenter-Sy...
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arch
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sh
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include
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cpu-sh4
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cpu
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freq.h

freq.h 2.1 KB
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  1. /*
    2. 

  2.  * include/asm-sh/cpu-sh4/freq.h
    3. 

  3.  *
    4. 

  4.  * Copyright (C) 2002, 2003 Paul Mundt
    5. 

  5.  *
    6. 

  6.  * This file is subject to the terms and conditions of the GNU General Public
    7. 

  7.  * License.  See the file "COPYING" in the main directory of this archive
    8. 

  8.  * for more details.
    9. 

  9.  */
    10. 

  10. #ifndef __ASM_CPU_SH4_FREQ_H
    11. 

  11. #define __ASM_CPU_SH4_FREQ_H
    12. 

  12. 

  13. #if defined(CONFIG_CPU_SUBTYPE_SH7722) || \
    14. 

  14.     defined(CONFIG_CPU_SUBTYPE_SH7723) || \
    15. 

  15.     defined(CONFIG_CPU_SUBTYPE_SH7343) || \
    16. 

  16.     defined(CONFIG_CPU_SUBTYPE_SH7366)
    17. 

  17. #define FRQCR		        0xa4150000
    18. 

  18. #define VCLKCR			0xa4150004
    19. 

  19. #define SCLKACR			0xa4150008
    20. 

  20. #define SCLKBCR			0xa415000c
    21. 

  21. #define IrDACLKCR		0xa4150010
    22. 

  22. #define MSTPCR0			0xa4150030
    23. 

  23. #define MSTPCR1			0xa4150034
    24. 

  24. #define MSTPCR2			0xa4150038
    25. 

  25. #elif defined(CONFIG_CPU_SUBTYPE_SH7757)
    26. 

  26. #define	FRQCR			0xffc80000
    27. 

  27. #define	OSCCR			0xffc80018
    28. 

  28. #define	PLLCR			0xffc80024
    29. 

  29. #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
    30. 

  30.       defined(CONFIG_CPU_SUBTYPE_SH7780)
    31. 

  31. #define	FRQCR			0xffc80000
    32. 

  32. #elif defined(CONFIG_CPU_SUBTYPE_SH7724)
    33. 

  33. #define FRQCRA			0xa4150000
    34. 

  34. #define FRQCRB			0xa4150004
    35. 

  35. #define VCLKCR			0xa4150048
    36. 

  36. 

  37. #define FCLKACR			0xa4150008
    38. 

  38. #define FCLKBCR			0xa415000c
    39. 

  39. #define FRQCR			FRQCRA
    40. 

  40. #define SCLKACR			FCLKACR
    41. 

  41. #define SCLKBCR			FCLKBCR
    42. 

  42. #define FCLKACR			0xa4150008
    43. 

  43. #define FCLKBCR			0xa415000c
    44. 

  44. #define IrDACLKCR		0xa4150018
    45. 

  45. 

  46. #define MSTPCR0			0xa4150030
    47. 

  47. #define MSTPCR1			0xa4150034
    48. 

  48. #define MSTPCR2			0xa4150038
    49. 

  49. 

  50. #elif defined(CONFIG_CPU_SUBTYPE_SH7734)
    51. 

  51. #define FRQCR0			0xffc80000
    52. 

  52. #define FRQCR2			0xffc80008
    53. 

  53. #define FRQMR1			0xffc80014
    54. 

  54. #define FRQMR2			0xffc80018
    55. 

  55. #elif defined(CONFIG_CPU_SUBTYPE_SH7785)
    56. 

  56. #define FRQCR0			0xffc80000
    57. 

  57. #define FRQCR1			0xffc80004
    58. 

  58. #define FRQMR1			0xffc80014
    59. 

  59. #elif defined(CONFIG_CPU_SUBTYPE_SH7786)
    60. 

  60. #define FRQCR0			0xffc40000
    61. 

  61. #define FRQCR1			0xffc40004
    62. 

  62. #define FRQMR1			0xffc40014
    63. 

  63. #elif defined(CONFIG_CPU_SUBTYPE_SHX3)
    64. 

  64. #define FRQCR0			0xffc00000
    65. 

  65. #define FRQCR1			0xffc00004
    66. 

  66. #define FRQMR1			0xffc00014
    67. 

  67. #else
    68. 

  68. #define FRQCR			0xffc00000
    69. 

  69. #define FRQCR_PSTBY		0x0200
    70. 

  70. #define FRQCR_PLLEN		0x0400
    71. 

  71. #define FRQCR_CKOEN		0x0800
    72. 

  72. #endif
    73. 

  73. #define MIN_DIVISOR_NR		0
    74. 

  74. #define MAX_DIVISOR_NR		3
    75. 

  75. 

  76. #endif /* __ASM_CPU_SH4_FREQ_H */
    77. 

  77.