mmu_context.h 2.0 KB

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  1. /*
  2. * include/asm-sh/cpu-sh4/mmu_context.h
  3. *
  4. * Copyright (C) 1999 Niibe Yutaka
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. */
  10. #ifndef __ASM_CPU_SH4_MMU_CONTEXT_H
  11. #define __ASM_CPU_SH4_MMU_CONTEXT_H
  12. #define MMU_PTEH 0xFF000000 /* Page table entry register HIGH */
  13. #define MMU_PTEL 0xFF000004 /* Page table entry register LOW */
  14. #define MMU_TTB 0xFF000008 /* Translation table base register */
  15. #define MMU_TEA 0xFF00000C /* TLB Exception Address */
  16. #define MMU_PTEA 0xFF000034 /* PTE assistance register */
  17. #define MMU_PTEAEX 0xFF00007C /* PTE ASID extension register */
  18. #define MMUCR 0xFF000010 /* MMU Control Register */
  19. #define MMU_TLB_ENTRY_SHIFT 8
  20. #define MMU_ITLB_ADDRESS_ARRAY 0xF2000000
  21. #define MMU_ITLB_ADDRESS_ARRAY2 0xF2800000
  22. #define MMU_ITLB_DATA_ARRAY 0xF3000000
  23. #define MMU_ITLB_DATA_ARRAY2 0xF3800000
  24. #define MMU_UTLB_ADDRESS_ARRAY 0xF6000000
  25. #define MMU_UTLB_ADDRESS_ARRAY2 0xF6800000
  26. #define MMU_UTLB_DATA_ARRAY 0xF7000000
  27. #define MMU_UTLB_DATA_ARRAY2 0xF7800000
  28. #define MMU_PAGE_ASSOC_BIT 0x80
  29. #ifdef CONFIG_MMU
  30. #define MMUCR_AT (1 << 0)
  31. #else
  32. #define MMUCR_AT (0)
  33. #endif
  34. #define MMUCR_TI (1 << 2)
  35. #define MMUCR_URB 0x00FC0000
  36. #define MMUCR_URB_SHIFT 18
  37. #define MMUCR_URB_NENTRIES 64
  38. #define MMUCR_URC 0x0000FC00
  39. #define MMUCR_URC_SHIFT 10
  40. #if defined(CONFIG_32BIT) && defined(CONFIG_CPU_SUBTYPE_ST40)
  41. #define MMUCR_SE (1 << 4)
  42. #else
  43. #define MMUCR_SE (0)
  44. #endif
  45. #ifdef CONFIG_CPU_HAS_PTEAEX
  46. #define MMUCR_AEX (1 << 6)
  47. #else
  48. #define MMUCR_AEX (0)
  49. #endif
  50. #ifdef CONFIG_X2TLB
  51. #define MMUCR_ME (1 << 7)
  52. #else
  53. #define MMUCR_ME (0)
  54. #endif
  55. #ifdef CONFIG_SH_STORE_QUEUES
  56. #define MMUCR_SQMD (1 << 9)
  57. #else
  58. #define MMUCR_SQMD (0)
  59. #endif
  60. #define MMU_NTLB_ENTRIES 64
  61. #define MMU_CONTROL_INIT (MMUCR_AT | MMUCR_TI | MMUCR_SQMD | \
  62. MMUCR_ME | MMUCR_SE | MMUCR_AEX)
  63. #define TRA 0xff000020
  64. #define EXPEVT 0xff000024
  65. #define INTEVT 0xff000028
  66. #endif /* __ASM_CPU_SH4_MMU_CONTEXT_H */