devicetree.c 6.0 KB

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  1. /*
  2. * Architecture specific OF callbacks.
  3. */
  4. #include <linux/bootmem.h>
  5. #include <linux/export.h>
  6. #include <linux/io.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/list.h>
  9. #include <linux/of.h>
  10. #include <linux/of_fdt.h>
  11. #include <linux/of_address.h>
  12. #include <linux/of_platform.h>
  13. #include <linux/of_irq.h>
  14. #include <linux/libfdt.h>
  15. #include <linux/slab.h>
  16. #include <linux/pci.h>
  17. #include <linux/of_pci.h>
  18. #include <linux/initrd.h>
  19. #include <asm/irqdomain.h>
  20. #include <asm/hpet.h>
  21. #include <asm/apic.h>
  22. #include <asm/pci_x86.h>
  23. #include <asm/setup.h>
  24. #include <asm/i8259.h>
  25. __initdata u64 initial_dtb;
  26. char __initdata cmd_line[COMMAND_LINE_SIZE];
  27. int __initdata of_ioapic;
  28. void __init early_init_dt_scan_chosen_arch(unsigned long node)
  29. {
  30. BUG();
  31. }
  32. void __init early_init_dt_add_memory_arch(u64 base, u64 size)
  33. {
  34. BUG();
  35. }
  36. void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
  37. {
  38. return __alloc_bootmem(size, align, __pa(MAX_DMA_ADDRESS));
  39. }
  40. void __init add_dtb(u64 data)
  41. {
  42. initial_dtb = data + offsetof(struct setup_data, data);
  43. }
  44. /*
  45. * CE4100 ids. Will be moved to machine_device_initcall() once we have it.
  46. */
  47. static struct of_device_id __initdata ce4100_ids[] = {
  48. { .compatible = "intel,ce4100-cp", },
  49. { .compatible = "isa", },
  50. { .compatible = "pci", },
  51. {},
  52. };
  53. static int __init add_bus_probe(void)
  54. {
  55. if (!of_have_populated_dt())
  56. return 0;
  57. return of_platform_bus_probe(NULL, ce4100_ids, NULL);
  58. }
  59. device_initcall(add_bus_probe);
  60. #ifdef CONFIG_PCI
  61. struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
  62. {
  63. struct device_node *np;
  64. for_each_node_by_type(np, "pci") {
  65. const void *prop;
  66. unsigned int bus_min;
  67. prop = of_get_property(np, "bus-range", NULL);
  68. if (!prop)
  69. continue;
  70. bus_min = be32_to_cpup(prop);
  71. if (bus->number == bus_min)
  72. return np;
  73. }
  74. return NULL;
  75. }
  76. static int x86_of_pci_irq_enable(struct pci_dev *dev)
  77. {
  78. u32 virq;
  79. int ret;
  80. u8 pin;
  81. ret = pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
  82. if (ret)
  83. return ret;
  84. if (!pin)
  85. return 0;
  86. virq = of_irq_parse_and_map_pci(dev, 0, 0);
  87. if (virq == 0)
  88. return -EINVAL;
  89. dev->irq = virq;
  90. return 0;
  91. }
  92. static void x86_of_pci_irq_disable(struct pci_dev *dev)
  93. {
  94. }
  95. void x86_of_pci_init(void)
  96. {
  97. pcibios_enable_irq = x86_of_pci_irq_enable;
  98. pcibios_disable_irq = x86_of_pci_irq_disable;
  99. }
  100. #endif
  101. static void __init dtb_setup_hpet(void)
  102. {
  103. #ifdef CONFIG_HPET_TIMER
  104. struct device_node *dn;
  105. struct resource r;
  106. int ret;
  107. dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-hpet");
  108. if (!dn)
  109. return;
  110. ret = of_address_to_resource(dn, 0, &r);
  111. if (ret) {
  112. WARN_ON(1);
  113. return;
  114. }
  115. hpet_address = r.start;
  116. #endif
  117. }
  118. static void __init dtb_lapic_setup(void)
  119. {
  120. #ifdef CONFIG_X86_LOCAL_APIC
  121. struct device_node *dn;
  122. struct resource r;
  123. int ret;
  124. dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic");
  125. if (!dn)
  126. return;
  127. ret = of_address_to_resource(dn, 0, &r);
  128. if (WARN_ON(ret))
  129. return;
  130. /* Did the boot loader setup the local APIC ? */
  131. if (!cpu_has_apic) {
  132. if (apic_force_enable(r.start))
  133. return;
  134. }
  135. smp_found_config = 1;
  136. pic_mode = 1;
  137. register_lapic_address(r.start);
  138. generic_processor_info(boot_cpu_physical_apicid,
  139. GET_APIC_VERSION(apic_read(APIC_LVR)));
  140. #endif
  141. }
  142. #ifdef CONFIG_X86_IO_APIC
  143. static unsigned int ioapic_id;
  144. struct of_ioapic_type {
  145. u32 out_type;
  146. u32 trigger;
  147. u32 polarity;
  148. };
  149. static struct of_ioapic_type of_ioapic_type[] =
  150. {
  151. {
  152. .out_type = IRQ_TYPE_EDGE_RISING,
  153. .trigger = IOAPIC_EDGE,
  154. .polarity = 1,
  155. },
  156. {
  157. .out_type = IRQ_TYPE_LEVEL_LOW,
  158. .trigger = IOAPIC_LEVEL,
  159. .polarity = 0,
  160. },
  161. {
  162. .out_type = IRQ_TYPE_LEVEL_HIGH,
  163. .trigger = IOAPIC_LEVEL,
  164. .polarity = 1,
  165. },
  166. {
  167. .out_type = IRQ_TYPE_EDGE_FALLING,
  168. .trigger = IOAPIC_EDGE,
  169. .polarity = 0,
  170. },
  171. };
  172. static int dt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
  173. unsigned int nr_irqs, void *arg)
  174. {
  175. struct irq_fwspec *fwspec = (struct irq_fwspec *)arg;
  176. struct of_ioapic_type *it;
  177. struct irq_alloc_info tmp;
  178. int type_index;
  179. if (WARN_ON(fwspec->param_count < 2))
  180. return -EINVAL;
  181. type_index = fwspec->param[1];
  182. if (type_index >= ARRAY_SIZE(of_ioapic_type))
  183. return -EINVAL;
  184. it = &of_ioapic_type[type_index];
  185. ioapic_set_alloc_attr(&tmp, NUMA_NO_NODE, it->trigger, it->polarity);
  186. tmp.ioapic_id = mpc_ioapic_id(mp_irqdomain_ioapic_idx(domain));
  187. tmp.ioapic_pin = fwspec->param[0];
  188. return mp_irqdomain_alloc(domain, virq, nr_irqs, &tmp);
  189. }
  190. static const struct irq_domain_ops ioapic_irq_domain_ops = {
  191. .alloc = dt_irqdomain_alloc,
  192. .free = mp_irqdomain_free,
  193. .activate = mp_irqdomain_activate,
  194. .deactivate = mp_irqdomain_deactivate,
  195. };
  196. static void __init dtb_add_ioapic(struct device_node *dn)
  197. {
  198. struct resource r;
  199. int ret;
  200. struct ioapic_domain_cfg cfg = {
  201. .type = IOAPIC_DOMAIN_DYNAMIC,
  202. .ops = &ioapic_irq_domain_ops,
  203. .dev = dn,
  204. };
  205. ret = of_address_to_resource(dn, 0, &r);
  206. if (ret) {
  207. printk(KERN_ERR "Can't obtain address from node %s.\n",
  208. dn->full_name);
  209. return;
  210. }
  211. mp_register_ioapic(++ioapic_id, r.start, gsi_top, &cfg);
  212. }
  213. static void __init dtb_ioapic_setup(void)
  214. {
  215. struct device_node *dn;
  216. for_each_compatible_node(dn, NULL, "intel,ce4100-ioapic")
  217. dtb_add_ioapic(dn);
  218. if (nr_ioapics) {
  219. of_ioapic = 1;
  220. return;
  221. }
  222. printk(KERN_ERR "Error: No information about IO-APIC in OF.\n");
  223. }
  224. #else
  225. static void __init dtb_ioapic_setup(void) {}
  226. #endif
  227. static void __init dtb_apic_setup(void)
  228. {
  229. dtb_lapic_setup();
  230. dtb_ioapic_setup();
  231. }
  232. #ifdef CONFIG_OF_FLATTREE
  233. static void __init x86_flattree_get_config(void)
  234. {
  235. u32 size, map_len;
  236. void *dt;
  237. if (!initial_dtb)
  238. return;
  239. map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK), (u64)128);
  240. dt = early_memremap(initial_dtb, map_len);
  241. size = fdt_totalsize(dt);
  242. if (map_len < size) {
  243. early_memunmap(dt, map_len);
  244. dt = early_memremap(initial_dtb, size);
  245. map_len = size;
  246. }
  247. early_init_dt_verify(dt);
  248. unflatten_and_copy_device_tree();
  249. early_memunmap(dt, map_len);
  250. }
  251. #else
  252. static inline void x86_flattree_get_config(void) { }
  253. #endif
  254. void __init x86_dtb_init(void)
  255. {
  256. x86_flattree_get_config();
  257. if (!of_have_populated_dt())
  258. return;
  259. dtb_setup_hpet();
  260. dtb_apic_setup();
  261. }