mmconf-fam10h_64.c 5.3 KB

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  1. /*
  2. * AMD Family 10h mmconfig enablement
  3. */
  4. #include <linux/types.h>
  5. #include <linux/mm.h>
  6. #include <linux/string.h>
  7. #include <linux/pci.h>
  8. #include <linux/dmi.h>
  9. #include <linux/range.h>
  10. #include <asm/pci-direct.h>
  11. #include <linux/sort.h>
  12. #include <asm/io.h>
  13. #include <asm/msr.h>
  14. #include <asm/acpi.h>
  15. #include <asm/mmconfig.h>
  16. #include <asm/pci_x86.h>
  17. struct pci_hostbridge_probe {
  18. u32 bus;
  19. u32 slot;
  20. u32 vendor;
  21. u32 device;
  22. };
  23. static u64 fam10h_pci_mmconf_base;
  24. static struct pci_hostbridge_probe pci_probes[] = {
  25. { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
  26. { 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
  27. };
  28. static int cmp_range(const void *x1, const void *x2)
  29. {
  30. const struct range *r1 = x1;
  31. const struct range *r2 = x2;
  32. int start1, start2;
  33. start1 = r1->start >> 32;
  34. start2 = r2->start >> 32;
  35. return start1 - start2;
  36. }
  37. #define MMCONF_UNIT (1ULL << FAM10H_MMIO_CONF_BASE_SHIFT)
  38. #define MMCONF_MASK (~(MMCONF_UNIT - 1))
  39. #define MMCONF_SIZE (MMCONF_UNIT << 8)
  40. /* need to avoid (0xfd<<32), (0xfe<<32), and (0xff<<32), ht used space */
  41. #define FAM10H_PCI_MMCONF_BASE (0xfcULL<<32)
  42. #define BASE_VALID(b) ((b) + MMCONF_SIZE <= (0xfdULL<<32) || (b) >= (1ULL<<40))
  43. static void get_fam10h_pci_mmconf_base(void)
  44. {
  45. int i;
  46. unsigned bus;
  47. unsigned slot;
  48. int found;
  49. u64 val;
  50. u32 address;
  51. u64 tom2;
  52. u64 base = FAM10H_PCI_MMCONF_BASE;
  53. int hi_mmio_num;
  54. struct range range[8];
  55. /* only try to get setting from BSP */
  56. if (fam10h_pci_mmconf_base)
  57. return;
  58. if (!early_pci_allowed())
  59. return;
  60. found = 0;
  61. for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
  62. u32 id;
  63. u16 device;
  64. u16 vendor;
  65. bus = pci_probes[i].bus;
  66. slot = pci_probes[i].slot;
  67. id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);
  68. vendor = id & 0xffff;
  69. device = (id>>16) & 0xffff;
  70. if (pci_probes[i].vendor == vendor &&
  71. pci_probes[i].device == device) {
  72. found = 1;
  73. break;
  74. }
  75. }
  76. if (!found)
  77. return;
  78. /* SYS_CFG */
  79. address = MSR_K8_SYSCFG;
  80. rdmsrl(address, val);
  81. /* TOP_MEM2 is not enabled? */
  82. if (!(val & (1<<21))) {
  83. tom2 = 1ULL << 32;
  84. } else {
  85. /* TOP_MEM2 */
  86. address = MSR_K8_TOP_MEM2;
  87. rdmsrl(address, val);
  88. tom2 = max(val & 0xffffff800000ULL, 1ULL << 32);
  89. }
  90. if (base <= tom2)
  91. base = (tom2 + 2 * MMCONF_UNIT - 1) & MMCONF_MASK;
  92. /*
  93. * need to check if the range is in the high mmio range that is
  94. * above 4G
  95. */
  96. hi_mmio_num = 0;
  97. for (i = 0; i < 8; i++) {
  98. u32 reg;
  99. u64 start;
  100. u64 end;
  101. reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
  102. if (!(reg & 3))
  103. continue;
  104. start = (u64)(reg & 0xffffff00) << 8; /* 39:16 on 31:8*/
  105. reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
  106. end = ((u64)(reg & 0xffffff00) << 8) | 0xffff; /* 39:16 on 31:8*/
  107. if (end < tom2)
  108. continue;
  109. range[hi_mmio_num].start = start;
  110. range[hi_mmio_num].end = end;
  111. hi_mmio_num++;
  112. }
  113. if (!hi_mmio_num)
  114. goto out;
  115. /* sort the range */
  116. sort(range, hi_mmio_num, sizeof(struct range), cmp_range, NULL);
  117. if (range[hi_mmio_num - 1].end < base)
  118. goto out;
  119. if (range[0].start > base + MMCONF_SIZE)
  120. goto out;
  121. /* need to find one window */
  122. base = (range[0].start & MMCONF_MASK) - MMCONF_UNIT;
  123. if ((base > tom2) && BASE_VALID(base))
  124. goto out;
  125. base = (range[hi_mmio_num - 1].end + MMCONF_UNIT) & MMCONF_MASK;
  126. if (BASE_VALID(base))
  127. goto out;
  128. /* need to find window between ranges */
  129. for (i = 1; i < hi_mmio_num; i++) {
  130. base = (range[i - 1].end + MMCONF_UNIT) & MMCONF_MASK;
  131. val = range[i].start & MMCONF_MASK;
  132. if (val >= base + MMCONF_SIZE && BASE_VALID(base))
  133. goto out;
  134. }
  135. return;
  136. out:
  137. fam10h_pci_mmconf_base = base;
  138. }
  139. void fam10h_check_enable_mmcfg(void)
  140. {
  141. u64 val;
  142. u32 address;
  143. if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
  144. return;
  145. address = MSR_FAM10H_MMIO_CONF_BASE;
  146. rdmsrl(address, val);
  147. /* try to make sure that AP's setting is identical to BSP setting */
  148. if (val & FAM10H_MMIO_CONF_ENABLE) {
  149. unsigned busnbits;
  150. busnbits = (val >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
  151. FAM10H_MMIO_CONF_BUSRANGE_MASK;
  152. /* only trust the one handle 256 buses, if acpi=off */
  153. if (!acpi_pci_disabled || busnbits >= 8) {
  154. u64 base = val & MMCONF_MASK;
  155. if (!fam10h_pci_mmconf_base) {
  156. fam10h_pci_mmconf_base = base;
  157. return;
  158. } else if (fam10h_pci_mmconf_base == base)
  159. return;
  160. }
  161. }
  162. /*
  163. * if it is not enabled, try to enable it and assume only one segment
  164. * with 256 buses
  165. */
  166. get_fam10h_pci_mmconf_base();
  167. if (!fam10h_pci_mmconf_base) {
  168. pci_probe &= ~PCI_CHECK_ENABLE_AMD_MMCONF;
  169. return;
  170. }
  171. printk(KERN_INFO "Enable MMCONFIG on AMD Family 10h\n");
  172. val &= ~((FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT) |
  173. (FAM10H_MMIO_CONF_BUSRANGE_MASK<<FAM10H_MMIO_CONF_BUSRANGE_SHIFT));
  174. val |= fam10h_pci_mmconf_base | (8 << FAM10H_MMIO_CONF_BUSRANGE_SHIFT) |
  175. FAM10H_MMIO_CONF_ENABLE;
  176. wrmsrl(address, val);
  177. }
  178. static int __init set_check_enable_amd_mmconf(const struct dmi_system_id *d)
  179. {
  180. pci_probe |= PCI_CHECK_ENABLE_AMD_MMCONF;
  181. return 0;
  182. }
  183. static const struct dmi_system_id __initconst mmconf_dmi_table[] = {
  184. {
  185. .callback = set_check_enable_amd_mmconf,
  186. .ident = "Sun Microsystems Machine",
  187. .matches = {
  188. DMI_MATCH(DMI_SYS_VENDOR, "Sun Microsystems"),
  189. },
  190. },
  191. {}
  192. };
  193. /* Called from a non __init function, but only on the BSP. */
  194. void __ref check_enable_amd_mmconf_dmi(void)
  195. {
  196. dmi_check_system(mmconf_dmi_table);
  197. }