tsc_msr.c 3.4 KB

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  1. /*
  2. * tsc_msr.c - MSR based TSC calibration on Intel Atom SoC platforms.
  3. *
  4. * TSC in Intel Atom SoC runs at a constant rate which can be figured
  5. * by this formula:
  6. * <maximum core-clock to bus-clock ratio> * <maximum resolved frequency>
  7. * See Intel 64 and IA-32 System Programming Guid section 16.12 and 30.11.5
  8. * for details.
  9. * Especially some Intel Atom SoCs don't have PIT(i8254) or HPET, so MSR
  10. * based calibration is the only option.
  11. *
  12. *
  13. * Copyright (C) 2013 Intel Corporation
  14. * Author: Bin Gao <bin.gao@intel.com>
  15. *
  16. * This file is released under the GPLv2.
  17. */
  18. #include <linux/kernel.h>
  19. #include <asm/processor.h>
  20. #include <asm/setup.h>
  21. #include <asm/apic.h>
  22. #include <asm/param.h>
  23. #include <asm/tsc.h>
  24. /* CPU reference clock frequency: in KHz */
  25. #define FREQ_83 83200
  26. #define FREQ_100 99840
  27. #define FREQ_133 133200
  28. #define FREQ_166 166400
  29. #define MAX_NUM_FREQS 8
  30. /*
  31. * According to Intel 64 and IA-32 System Programming Guide,
  32. * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
  33. * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
  34. * Unfortunately some Intel Atom SoCs aren't quite compliant to this,
  35. * so we need manually differentiate SoC families. This is what the
  36. * field msr_plat does.
  37. */
  38. struct freq_desc {
  39. u8 x86_family; /* CPU family */
  40. u8 x86_model; /* model */
  41. u8 msr_plat; /* 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
  42. u32 freqs[MAX_NUM_FREQS];
  43. };
  44. static struct freq_desc freq_desc_tables[] = {
  45. /* PNW */
  46. { 6, 0x27, 0, { 0, 0, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
  47. /* CLV+ */
  48. { 6, 0x35, 0, { 0, FREQ_133, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
  49. /* TNG */
  50. { 6, 0x4a, 1, { 0, FREQ_100, FREQ_133, 0, 0, 0, 0, 0 } },
  51. /* VLV2 */
  52. { 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },
  53. /* ANN */
  54. { 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } },
  55. };
  56. static int match_cpu(u8 family, u8 model)
  57. {
  58. int i;
  59. for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) {
  60. if ((family == freq_desc_tables[i].x86_family) &&
  61. (model == freq_desc_tables[i].x86_model))
  62. return i;
  63. }
  64. return -1;
  65. }
  66. /* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
  67. #define id_to_freq(cpu_index, freq_id) \
  68. (freq_desc_tables[cpu_index].freqs[freq_id])
  69. /*
  70. * Do MSR calibration only for known/supported CPUs.
  71. *
  72. * Returns the calibration value or 0 if MSR calibration failed.
  73. */
  74. unsigned long try_msr_calibrate_tsc(void)
  75. {
  76. u32 lo, hi, ratio, freq_id, freq;
  77. unsigned long res;
  78. int cpu_index;
  79. cpu_index = match_cpu(boot_cpu_data.x86, boot_cpu_data.x86_model);
  80. if (cpu_index < 0)
  81. return 0;
  82. if (freq_desc_tables[cpu_index].msr_plat) {
  83. rdmsr(MSR_PLATFORM_INFO, lo, hi);
  84. ratio = (lo >> 8) & 0xff;
  85. } else {
  86. rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
  87. ratio = (hi >> 8) & 0x1f;
  88. }
  89. pr_info("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
  90. if (!ratio)
  91. goto fail;
  92. /* Get FSB FREQ ID */
  93. rdmsr(MSR_FSB_FREQ, lo, hi);
  94. freq_id = lo & 0x7;
  95. freq = id_to_freq(cpu_index, freq_id);
  96. pr_info("Resolved frequency ID: %u, frequency: %u KHz\n",
  97. freq_id, freq);
  98. if (!freq)
  99. goto fail;
  100. /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
  101. res = freq * ratio;
  102. pr_info("TSC runs at %lu KHz\n", res);
  103. #ifdef CONFIG_X86_LOCAL_APIC
  104. lapic_timer_frequency = (freq * 1000) / HZ;
  105. pr_info("lapic_timer_frequency = %d\n", lapic_timer_frequency);
  106. #endif
  107. return res;
  108. fail:
  109. pr_warn("Fast TSC calibration using MSR failed\n");
  110. return 0;
  111. }