common.c 16 KB

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  1. /*
  2. * Low-Level PCI Support for PC
  3. *
  4. * (c) 1999--2000 Martin Mares <mj@ucw.cz>
  5. */
  6. #include <linux/sched.h>
  7. #include <linux/pci.h>
  8. #include <linux/pci-acpi.h>
  9. #include <linux/ioport.h>
  10. #include <linux/init.h>
  11. #include <linux/dmi.h>
  12. #include <linux/slab.h>
  13. #include <asm-generic/pci-bridge.h>
  14. #include <asm/acpi.h>
  15. #include <asm/segment.h>
  16. #include <asm/io.h>
  17. #include <asm/smp.h>
  18. #include <asm/pci_x86.h>
  19. #include <asm/setup.h>
  20. unsigned int pci_probe = PCI_PROBE_BIOS | PCI_PROBE_CONF1 | PCI_PROBE_CONF2 |
  21. PCI_PROBE_MMCONF;
  22. unsigned int pci_early_dump_regs;
  23. static int pci_bf_sort;
  24. static int smbios_type_b1_flag;
  25. int pci_routeirq;
  26. int noioapicquirk;
  27. #ifdef CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS
  28. int noioapicreroute = 0;
  29. #else
  30. int noioapicreroute = 1;
  31. #endif
  32. int pcibios_last_bus = -1;
  33. unsigned long pirq_table_addr;
  34. const struct pci_raw_ops *__read_mostly raw_pci_ops;
  35. const struct pci_raw_ops *__read_mostly raw_pci_ext_ops;
  36. int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
  37. int reg, int len, u32 *val)
  38. {
  39. if (domain == 0 && reg < 256 && raw_pci_ops)
  40. return raw_pci_ops->read(domain, bus, devfn, reg, len, val);
  41. if (raw_pci_ext_ops)
  42. return raw_pci_ext_ops->read(domain, bus, devfn, reg, len, val);
  43. return -EINVAL;
  44. }
  45. int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
  46. int reg, int len, u32 val)
  47. {
  48. if (domain == 0 && reg < 256 && raw_pci_ops)
  49. return raw_pci_ops->write(domain, bus, devfn, reg, len, val);
  50. if (raw_pci_ext_ops)
  51. return raw_pci_ext_ops->write(domain, bus, devfn, reg, len, val);
  52. return -EINVAL;
  53. }
  54. static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
  55. {
  56. return raw_pci_read(pci_domain_nr(bus), bus->number,
  57. devfn, where, size, value);
  58. }
  59. static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
  60. {
  61. return raw_pci_write(pci_domain_nr(bus), bus->number,
  62. devfn, where, size, value);
  63. }
  64. struct pci_ops pci_root_ops = {
  65. .read = pci_read,
  66. .write = pci_write,
  67. };
  68. /*
  69. * This interrupt-safe spinlock protects all accesses to PCI
  70. * configuration space.
  71. */
  72. DEFINE_RAW_SPINLOCK(pci_config_lock);
  73. static int __init can_skip_ioresource_align(const struct dmi_system_id *d)
  74. {
  75. pci_probe |= PCI_CAN_SKIP_ISA_ALIGN;
  76. printk(KERN_INFO "PCI: %s detected, can skip ISA alignment\n", d->ident);
  77. return 0;
  78. }
  79. static const struct dmi_system_id can_skip_pciprobe_dmi_table[] __initconst = {
  80. /*
  81. * Systems where PCI IO resource ISA alignment can be skipped
  82. * when the ISA enable bit in the bridge control is not set
  83. */
  84. {
  85. .callback = can_skip_ioresource_align,
  86. .ident = "IBM System x3800",
  87. .matches = {
  88. DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
  89. DMI_MATCH(DMI_PRODUCT_NAME, "x3800"),
  90. },
  91. },
  92. {
  93. .callback = can_skip_ioresource_align,
  94. .ident = "IBM System x3850",
  95. .matches = {
  96. DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
  97. DMI_MATCH(DMI_PRODUCT_NAME, "x3850"),
  98. },
  99. },
  100. {
  101. .callback = can_skip_ioresource_align,
  102. .ident = "IBM System x3950",
  103. .matches = {
  104. DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
  105. DMI_MATCH(DMI_PRODUCT_NAME, "x3950"),
  106. },
  107. },
  108. {}
  109. };
  110. void __init dmi_check_skip_isa_align(void)
  111. {
  112. dmi_check_system(can_skip_pciprobe_dmi_table);
  113. }
  114. static void pcibios_fixup_device_resources(struct pci_dev *dev)
  115. {
  116. struct resource *rom_r = &dev->resource[PCI_ROM_RESOURCE];
  117. struct resource *bar_r;
  118. int bar;
  119. if (pci_probe & PCI_NOASSIGN_BARS) {
  120. /*
  121. * If the BIOS did not assign the BAR, zero out the
  122. * resource so the kernel doesn't attmept to assign
  123. * it later on in pci_assign_unassigned_resources
  124. */
  125. for (bar = 0; bar <= PCI_STD_RESOURCE_END; bar++) {
  126. bar_r = &dev->resource[bar];
  127. if (bar_r->start == 0 && bar_r->end != 0) {
  128. bar_r->flags = 0;
  129. bar_r->end = 0;
  130. }
  131. }
  132. }
  133. if (pci_probe & PCI_NOASSIGN_ROMS) {
  134. if (rom_r->parent)
  135. return;
  136. if (rom_r->start) {
  137. /* we deal with BIOS assigned ROM later */
  138. return;
  139. }
  140. rom_r->start = rom_r->end = rom_r->flags = 0;
  141. }
  142. }
  143. /*
  144. * Called after each bus is probed, but before its children
  145. * are examined.
  146. */
  147. void pcibios_fixup_bus(struct pci_bus *b)
  148. {
  149. struct pci_dev *dev;
  150. pci_read_bridge_bases(b);
  151. list_for_each_entry(dev, &b->devices, bus_list)
  152. pcibios_fixup_device_resources(dev);
  153. }
  154. void pcibios_add_bus(struct pci_bus *bus)
  155. {
  156. acpi_pci_add_bus(bus);
  157. }
  158. void pcibios_remove_bus(struct pci_bus *bus)
  159. {
  160. acpi_pci_remove_bus(bus);
  161. }
  162. /*
  163. * Only use DMI information to set this if nothing was passed
  164. * on the kernel command line (which was parsed earlier).
  165. */
  166. static int __init set_bf_sort(const struct dmi_system_id *d)
  167. {
  168. if (pci_bf_sort == pci_bf_sort_default) {
  169. pci_bf_sort = pci_dmi_bf;
  170. printk(KERN_INFO "PCI: %s detected, enabling pci=bfsort.\n", d->ident);
  171. }
  172. return 0;
  173. }
  174. static void __init read_dmi_type_b1(const struct dmi_header *dm,
  175. void *private_data)
  176. {
  177. u8 *d = (u8 *)dm + 4;
  178. if (dm->type != 0xB1)
  179. return;
  180. switch (((*(u32 *)d) >> 9) & 0x03) {
  181. case 0x00:
  182. printk(KERN_INFO "dmi type 0xB1 record - unknown flag\n");
  183. break;
  184. case 0x01: /* set pci=bfsort */
  185. smbios_type_b1_flag = 1;
  186. break;
  187. case 0x02: /* do not set pci=bfsort */
  188. smbios_type_b1_flag = 2;
  189. break;
  190. default:
  191. break;
  192. }
  193. }
  194. static int __init find_sort_method(const struct dmi_system_id *d)
  195. {
  196. dmi_walk(read_dmi_type_b1, NULL);
  197. if (smbios_type_b1_flag == 1) {
  198. set_bf_sort(d);
  199. return 0;
  200. }
  201. return -1;
  202. }
  203. /*
  204. * Enable renumbering of PCI bus# ranges to reach all PCI busses (Cardbus)
  205. */
  206. #ifdef __i386__
  207. static int __init assign_all_busses(const struct dmi_system_id *d)
  208. {
  209. pci_probe |= PCI_ASSIGN_ALL_BUSSES;
  210. printk(KERN_INFO "%s detected: enabling PCI bus# renumbering"
  211. " (pci=assign-busses)\n", d->ident);
  212. return 0;
  213. }
  214. #endif
  215. static int __init set_scan_all(const struct dmi_system_id *d)
  216. {
  217. printk(KERN_INFO "PCI: %s detected, enabling pci=pcie_scan_all\n",
  218. d->ident);
  219. pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
  220. return 0;
  221. }
  222. static const struct dmi_system_id pciprobe_dmi_table[] __initconst = {
  223. #ifdef __i386__
  224. /*
  225. * Laptops which need pci=assign-busses to see Cardbus cards
  226. */
  227. {
  228. .callback = assign_all_busses,
  229. .ident = "Samsung X20 Laptop",
  230. .matches = {
  231. DMI_MATCH(DMI_SYS_VENDOR, "Samsung Electronics"),
  232. DMI_MATCH(DMI_PRODUCT_NAME, "SX20S"),
  233. },
  234. },
  235. #endif /* __i386__ */
  236. {
  237. .callback = set_bf_sort,
  238. .ident = "Dell PowerEdge 1950",
  239. .matches = {
  240. DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
  241. DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 1950"),
  242. },
  243. },
  244. {
  245. .callback = set_bf_sort,
  246. .ident = "Dell PowerEdge 1955",
  247. .matches = {
  248. DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
  249. DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 1955"),
  250. },
  251. },
  252. {
  253. .callback = set_bf_sort,
  254. .ident = "Dell PowerEdge 2900",
  255. .matches = {
  256. DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
  257. DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 2900"),
  258. },
  259. },
  260. {
  261. .callback = set_bf_sort,
  262. .ident = "Dell PowerEdge 2950",
  263. .matches = {
  264. DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
  265. DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 2950"),
  266. },
  267. },
  268. {
  269. .callback = set_bf_sort,
  270. .ident = "Dell PowerEdge R900",
  271. .matches = {
  272. DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
  273. DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge R900"),
  274. },
  275. },
  276. {
  277. .callback = find_sort_method,
  278. .ident = "Dell System",
  279. .matches = {
  280. DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"),
  281. },
  282. },
  283. {
  284. .callback = set_bf_sort,
  285. .ident = "HP ProLiant BL20p G3",
  286. .matches = {
  287. DMI_MATCH(DMI_SYS_VENDOR, "HP"),
  288. DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL20p G3"),
  289. },
  290. },
  291. {
  292. .callback = set_bf_sort,
  293. .ident = "HP ProLiant BL20p G4",
  294. .matches = {
  295. DMI_MATCH(DMI_SYS_VENDOR, "HP"),
  296. DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL20p G4"),
  297. },
  298. },
  299. {
  300. .callback = set_bf_sort,
  301. .ident = "HP ProLiant BL30p G1",
  302. .matches = {
  303. DMI_MATCH(DMI_SYS_VENDOR, "HP"),
  304. DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL30p G1"),
  305. },
  306. },
  307. {
  308. .callback = set_bf_sort,
  309. .ident = "HP ProLiant BL25p G1",
  310. .matches = {
  311. DMI_MATCH(DMI_SYS_VENDOR, "HP"),
  312. DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL25p G1"),
  313. },
  314. },
  315. {
  316. .callback = set_bf_sort,
  317. .ident = "HP ProLiant BL35p G1",
  318. .matches = {
  319. DMI_MATCH(DMI_SYS_VENDOR, "HP"),
  320. DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL35p G1"),
  321. },
  322. },
  323. {
  324. .callback = set_bf_sort,
  325. .ident = "HP ProLiant BL45p G1",
  326. .matches = {
  327. DMI_MATCH(DMI_SYS_VENDOR, "HP"),
  328. DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL45p G1"),
  329. },
  330. },
  331. {
  332. .callback = set_bf_sort,
  333. .ident = "HP ProLiant BL45p G2",
  334. .matches = {
  335. DMI_MATCH(DMI_SYS_VENDOR, "HP"),
  336. DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL45p G2"),
  337. },
  338. },
  339. {
  340. .callback = set_bf_sort,
  341. .ident = "HP ProLiant BL460c G1",
  342. .matches = {
  343. DMI_MATCH(DMI_SYS_VENDOR, "HP"),
  344. DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL460c G1"),
  345. },
  346. },
  347. {
  348. .callback = set_bf_sort,
  349. .ident = "HP ProLiant BL465c G1",
  350. .matches = {
  351. DMI_MATCH(DMI_SYS_VENDOR, "HP"),
  352. DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL465c G1"),
  353. },
  354. },
  355. {
  356. .callback = set_bf_sort,
  357. .ident = "HP ProLiant BL480c G1",
  358. .matches = {
  359. DMI_MATCH(DMI_SYS_VENDOR, "HP"),
  360. DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL480c G1"),
  361. },
  362. },
  363. {
  364. .callback = set_bf_sort,
  365. .ident = "HP ProLiant BL685c G1",
  366. .matches = {
  367. DMI_MATCH(DMI_SYS_VENDOR, "HP"),
  368. DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL685c G1"),
  369. },
  370. },
  371. {
  372. .callback = set_bf_sort,
  373. .ident = "HP ProLiant DL360",
  374. .matches = {
  375. DMI_MATCH(DMI_SYS_VENDOR, "HP"),
  376. DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL360"),
  377. },
  378. },
  379. {
  380. .callback = set_bf_sort,
  381. .ident = "HP ProLiant DL380",
  382. .matches = {
  383. DMI_MATCH(DMI_SYS_VENDOR, "HP"),
  384. DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL380"),
  385. },
  386. },
  387. #ifdef __i386__
  388. {
  389. .callback = assign_all_busses,
  390. .ident = "Compaq EVO N800c",
  391. .matches = {
  392. DMI_MATCH(DMI_SYS_VENDOR, "Compaq"),
  393. DMI_MATCH(DMI_PRODUCT_NAME, "EVO N800c"),
  394. },
  395. },
  396. #endif
  397. {
  398. .callback = set_bf_sort,
  399. .ident = "HP ProLiant DL385 G2",
  400. .matches = {
  401. DMI_MATCH(DMI_SYS_VENDOR, "HP"),
  402. DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL385 G2"),
  403. },
  404. },
  405. {
  406. .callback = set_bf_sort,
  407. .ident = "HP ProLiant DL585 G2",
  408. .matches = {
  409. DMI_MATCH(DMI_SYS_VENDOR, "HP"),
  410. DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL585 G2"),
  411. },
  412. },
  413. {
  414. .callback = set_scan_all,
  415. .ident = "Stratus/NEC ftServer",
  416. .matches = {
  417. DMI_MATCH(DMI_SYS_VENDOR, "Stratus"),
  418. DMI_MATCH(DMI_PRODUCT_NAME, "ftServer"),
  419. },
  420. },
  421. {
  422. .callback = set_scan_all,
  423. .ident = "Stratus/NEC ftServer",
  424. .matches = {
  425. DMI_MATCH(DMI_SYS_VENDOR, "NEC"),
  426. DMI_MATCH(DMI_PRODUCT_NAME, "Express5800/R32"),
  427. },
  428. },
  429. {
  430. .callback = set_scan_all,
  431. .ident = "Stratus/NEC ftServer",
  432. .matches = {
  433. DMI_MATCH(DMI_SYS_VENDOR, "NEC"),
  434. DMI_MATCH(DMI_PRODUCT_NAME, "Express5800/R31"),
  435. },
  436. },
  437. {}
  438. };
  439. void __init dmi_check_pciprobe(void)
  440. {
  441. dmi_check_system(pciprobe_dmi_table);
  442. }
  443. void pcibios_scan_root(int busnum)
  444. {
  445. struct pci_bus *bus;
  446. struct pci_sysdata *sd;
  447. LIST_HEAD(resources);
  448. sd = kzalloc(sizeof(*sd), GFP_KERNEL);
  449. if (!sd) {
  450. printk(KERN_ERR "PCI: OOM, skipping PCI bus %02x\n", busnum);
  451. return;
  452. }
  453. sd->node = x86_pci_root_bus_node(busnum);
  454. x86_pci_root_bus_resources(busnum, &resources);
  455. printk(KERN_DEBUG "PCI: Probing PCI hardware (bus %02x)\n", busnum);
  456. bus = pci_scan_root_bus(NULL, busnum, &pci_root_ops, sd, &resources);
  457. if (!bus) {
  458. pci_free_resource_list(&resources);
  459. kfree(sd);
  460. return;
  461. }
  462. pci_bus_add_devices(bus);
  463. }
  464. void __init pcibios_set_cache_line_size(void)
  465. {
  466. struct cpuinfo_x86 *c = &boot_cpu_data;
  467. /*
  468. * Set PCI cacheline size to that of the CPU if the CPU has reported it.
  469. * (For older CPUs that don't support cpuid, we se it to 32 bytes
  470. * It's also good for 386/486s (which actually have 16)
  471. * as quite a few PCI devices do not support smaller values.
  472. */
  473. if (c->x86_clflush_size > 0) {
  474. pci_dfl_cache_line_size = c->x86_clflush_size >> 2;
  475. printk(KERN_DEBUG "PCI: pci_cache_line_size set to %d bytes\n",
  476. pci_dfl_cache_line_size << 2);
  477. } else {
  478. pci_dfl_cache_line_size = 32 >> 2;
  479. printk(KERN_DEBUG "PCI: Unknown cacheline size. Setting to 32 bytes\n");
  480. }
  481. }
  482. int __init pcibios_init(void)
  483. {
  484. if (!raw_pci_ops) {
  485. printk(KERN_WARNING "PCI: System does not support PCI\n");
  486. return 0;
  487. }
  488. pcibios_set_cache_line_size();
  489. pcibios_resource_survey();
  490. if (pci_bf_sort >= pci_force_bf)
  491. pci_sort_breadthfirst();
  492. return 0;
  493. }
  494. char *__init pcibios_setup(char *str)
  495. {
  496. if (!strcmp(str, "off")) {
  497. pci_probe = 0;
  498. return NULL;
  499. } else if (!strcmp(str, "bfsort")) {
  500. pci_bf_sort = pci_force_bf;
  501. return NULL;
  502. } else if (!strcmp(str, "nobfsort")) {
  503. pci_bf_sort = pci_force_nobf;
  504. return NULL;
  505. }
  506. #ifdef CONFIG_PCI_BIOS
  507. else if (!strcmp(str, "bios")) {
  508. pci_probe = PCI_PROBE_BIOS;
  509. return NULL;
  510. } else if (!strcmp(str, "nobios")) {
  511. pci_probe &= ~PCI_PROBE_BIOS;
  512. return NULL;
  513. } else if (!strcmp(str, "biosirq")) {
  514. pci_probe |= PCI_BIOS_IRQ_SCAN;
  515. return NULL;
  516. } else if (!strncmp(str, "pirqaddr=", 9)) {
  517. pirq_table_addr = simple_strtoul(str+9, NULL, 0);
  518. return NULL;
  519. }
  520. #endif
  521. #ifdef CONFIG_PCI_DIRECT
  522. else if (!strcmp(str, "conf1")) {
  523. pci_probe = PCI_PROBE_CONF1 | PCI_NO_CHECKS;
  524. return NULL;
  525. }
  526. else if (!strcmp(str, "conf2")) {
  527. pci_probe = PCI_PROBE_CONF2 | PCI_NO_CHECKS;
  528. return NULL;
  529. }
  530. #endif
  531. #ifdef CONFIG_PCI_MMCONFIG
  532. else if (!strcmp(str, "nommconf")) {
  533. pci_probe &= ~PCI_PROBE_MMCONF;
  534. return NULL;
  535. }
  536. else if (!strcmp(str, "check_enable_amd_mmconf")) {
  537. pci_probe |= PCI_CHECK_ENABLE_AMD_MMCONF;
  538. return NULL;
  539. }
  540. #endif
  541. else if (!strcmp(str, "noacpi")) {
  542. acpi_noirq_set();
  543. return NULL;
  544. }
  545. else if (!strcmp(str, "noearly")) {
  546. pci_probe |= PCI_PROBE_NOEARLY;
  547. return NULL;
  548. }
  549. else if (!strcmp(str, "usepirqmask")) {
  550. pci_probe |= PCI_USE_PIRQ_MASK;
  551. return NULL;
  552. } else if (!strncmp(str, "irqmask=", 8)) {
  553. pcibios_irq_mask = simple_strtol(str+8, NULL, 0);
  554. return NULL;
  555. } else if (!strncmp(str, "lastbus=", 8)) {
  556. pcibios_last_bus = simple_strtol(str+8, NULL, 0);
  557. return NULL;
  558. } else if (!strcmp(str, "rom")) {
  559. pci_probe |= PCI_ASSIGN_ROMS;
  560. return NULL;
  561. } else if (!strcmp(str, "norom")) {
  562. pci_probe |= PCI_NOASSIGN_ROMS;
  563. return NULL;
  564. } else if (!strcmp(str, "nobar")) {
  565. pci_probe |= PCI_NOASSIGN_BARS;
  566. return NULL;
  567. } else if (!strcmp(str, "assign-busses")) {
  568. pci_probe |= PCI_ASSIGN_ALL_BUSSES;
  569. return NULL;
  570. } else if (!strcmp(str, "use_crs")) {
  571. pci_probe |= PCI_USE__CRS;
  572. return NULL;
  573. } else if (!strcmp(str, "nocrs")) {
  574. pci_probe |= PCI_ROOT_NO_CRS;
  575. return NULL;
  576. } else if (!strcmp(str, "earlydump")) {
  577. pci_early_dump_regs = 1;
  578. return NULL;
  579. } else if (!strcmp(str, "routeirq")) {
  580. pci_routeirq = 1;
  581. return NULL;
  582. } else if (!strcmp(str, "skip_isa_align")) {
  583. pci_probe |= PCI_CAN_SKIP_ISA_ALIGN;
  584. return NULL;
  585. } else if (!strcmp(str, "noioapicquirk")) {
  586. noioapicquirk = 1;
  587. return NULL;
  588. } else if (!strcmp(str, "ioapicreroute")) {
  589. if (noioapicreroute != -1)
  590. noioapicreroute = 0;
  591. return NULL;
  592. } else if (!strcmp(str, "noioapicreroute")) {
  593. if (noioapicreroute != -1)
  594. noioapicreroute = 1;
  595. return NULL;
  596. }
  597. return str;
  598. }
  599. unsigned int pcibios_assign_all_busses(void)
  600. {
  601. return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
  602. }
  603. int pcibios_add_device(struct pci_dev *dev)
  604. {
  605. struct setup_data *data;
  606. struct pci_setup_rom *rom;
  607. u64 pa_data;
  608. pa_data = boot_params.hdr.setup_data;
  609. while (pa_data) {
  610. data = ioremap(pa_data, sizeof(*rom));
  611. if (!data)
  612. return -ENOMEM;
  613. if (data->type == SETUP_PCI) {
  614. rom = (struct pci_setup_rom *)data;
  615. if ((pci_domain_nr(dev->bus) == rom->segment) &&
  616. (dev->bus->number == rom->bus) &&
  617. (PCI_SLOT(dev->devfn) == rom->device) &&
  618. (PCI_FUNC(dev->devfn) == rom->function) &&
  619. (dev->vendor == rom->vendor) &&
  620. (dev->device == rom->devid)) {
  621. dev->rom = pa_data +
  622. offsetof(struct pci_setup_rom, romdata);
  623. dev->romlen = rom->pcilen;
  624. }
  625. }
  626. pa_data = data->next;
  627. iounmap(data);
  628. }
  629. return 0;
  630. }
  631. int pcibios_enable_device(struct pci_dev *dev, int mask)
  632. {
  633. int err;
  634. if ((err = pci_enable_resources(dev, mask)) < 0)
  635. return err;
  636. if (!pci_dev_msi_enabled(dev))
  637. return pcibios_enable_irq(dev);
  638. return 0;
  639. }
  640. void pcibios_disable_device (struct pci_dev *dev)
  641. {
  642. if (!pci_dev_msi_enabled(dev) && pcibios_disable_irq)
  643. pcibios_disable_irq(dev);
  644. }
  645. int pci_ext_cfg_avail(void)
  646. {
  647. if (raw_pci_ext_ops)
  648. return 1;
  649. else
  650. return 0;
  651. }