pata_hpt3x3.c 7.2 KB

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  1. /*
  2. * pata_hpt3x3 - HPT3x3 driver
  3. * (c) Copyright 2005-2006 Red Hat
  4. *
  5. * Was pata_hpt34x but the naming was confusing as it supported the
  6. * 343 and 363 so it has been renamed.
  7. *
  8. * Based on:
  9. * linux/drivers/ide/pci/hpt34x.c Version 0.40 Sept 10, 2002
  10. * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
  11. *
  12. * May be copied or modified under the terms of the GNU General Public
  13. * License
  14. */
  15. #include <linux/kernel.h>
  16. #include <linux/module.h>
  17. #include <linux/pci.h>
  18. #include <linux/blkdev.h>
  19. #include <linux/delay.h>
  20. #include <scsi/scsi_host.h>
  21. #include <linux/libata.h>
  22. #define DRV_NAME "pata_hpt3x3"
  23. #define DRV_VERSION "0.6.1"
  24. /**
  25. * hpt3x3_set_piomode - PIO setup
  26. * @ap: ATA interface
  27. * @adev: device on the interface
  28. *
  29. * Set our PIO requirements. This is fairly simple on the HPT3x3 as
  30. * all we have to do is clear the MWDMA and UDMA bits then load the
  31. * mode number.
  32. */
  33. static void hpt3x3_set_piomode(struct ata_port *ap, struct ata_device *adev)
  34. {
  35. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  36. u32 r1, r2;
  37. int dn = 2 * ap->port_no + adev->devno;
  38. pci_read_config_dword(pdev, 0x44, &r1);
  39. pci_read_config_dword(pdev, 0x48, &r2);
  40. /* Load the PIO timing number */
  41. r1 &= ~(7 << (3 * dn));
  42. r1 |= (adev->pio_mode - XFER_PIO_0) << (3 * dn);
  43. r2 &= ~(0x11 << dn); /* Clear MWDMA and UDMA bits */
  44. pci_write_config_dword(pdev, 0x44, r1);
  45. pci_write_config_dword(pdev, 0x48, r2);
  46. }
  47. #if defined(CONFIG_PATA_HPT3X3_DMA)
  48. /**
  49. * hpt3x3_set_dmamode - DMA timing setup
  50. * @ap: ATA interface
  51. * @adev: Device being configured
  52. *
  53. * Set up the channel for MWDMA or UDMA modes. Much the same as with
  54. * PIO, load the mode number and then set MWDMA or UDMA flag.
  55. *
  56. * 0x44 : bit 0-2 master mode, 3-5 slave mode, etc
  57. * 0x48 : bit 4/0 DMA/UDMA bit 5/1 for slave etc
  58. */
  59. static void hpt3x3_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  60. {
  61. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  62. u32 r1, r2;
  63. int dn = 2 * ap->port_no + adev->devno;
  64. int mode_num = adev->dma_mode & 0x0F;
  65. pci_read_config_dword(pdev, 0x44, &r1);
  66. pci_read_config_dword(pdev, 0x48, &r2);
  67. /* Load the timing number */
  68. r1 &= ~(7 << (3 * dn));
  69. r1 |= (mode_num << (3 * dn));
  70. r2 &= ~(0x11 << dn); /* Clear MWDMA and UDMA bits */
  71. if (adev->dma_mode >= XFER_UDMA_0)
  72. r2 |= (0x01 << dn); /* Ultra mode */
  73. else
  74. r2 |= (0x10 << dn); /* MWDMA */
  75. pci_write_config_dword(pdev, 0x44, r1);
  76. pci_write_config_dword(pdev, 0x48, r2);
  77. }
  78. /**
  79. * hpt3x3_freeze - DMA workaround
  80. * @ap: port to freeze
  81. *
  82. * When freezing an HPT3x3 we must stop any pending DMA before
  83. * writing to the control register or the chip will hang
  84. */
  85. static void hpt3x3_freeze(struct ata_port *ap)
  86. {
  87. void __iomem *mmio = ap->ioaddr.bmdma_addr;
  88. iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ ATA_DMA_START,
  89. mmio + ATA_DMA_CMD);
  90. ata_sff_dma_pause(ap);
  91. ata_sff_freeze(ap);
  92. }
  93. /**
  94. * hpt3x3_bmdma_setup - DMA workaround
  95. * @qc: Queued command
  96. *
  97. * When issuing BMDMA we must clean up the error/active bits in
  98. * software on this device
  99. */
  100. static void hpt3x3_bmdma_setup(struct ata_queued_cmd *qc)
  101. {
  102. struct ata_port *ap = qc->ap;
  103. u8 r = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
  104. r |= ATA_DMA_INTR | ATA_DMA_ERR;
  105. iowrite8(r, ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
  106. return ata_bmdma_setup(qc);
  107. }
  108. /**
  109. * hpt3x3_atapi_dma - ATAPI DMA check
  110. * @qc: Queued command
  111. *
  112. * Just say no - we don't do ATAPI DMA
  113. */
  114. static int hpt3x3_atapi_dma(struct ata_queued_cmd *qc)
  115. {
  116. return 1;
  117. }
  118. #endif /* CONFIG_PATA_HPT3X3_DMA */
  119. static struct scsi_host_template hpt3x3_sht = {
  120. ATA_BMDMA_SHT(DRV_NAME),
  121. };
  122. static struct ata_port_operations hpt3x3_port_ops = {
  123. .inherits = &ata_bmdma_port_ops,
  124. .cable_detect = ata_cable_40wire,
  125. .set_piomode = hpt3x3_set_piomode,
  126. #if defined(CONFIG_PATA_HPT3X3_DMA)
  127. .set_dmamode = hpt3x3_set_dmamode,
  128. .bmdma_setup = hpt3x3_bmdma_setup,
  129. .check_atapi_dma= hpt3x3_atapi_dma,
  130. .freeze = hpt3x3_freeze,
  131. #endif
  132. };
  133. /**
  134. * hpt3x3_init_chipset - chip setup
  135. * @dev: PCI device
  136. *
  137. * Perform the setup required at boot and on resume.
  138. */
  139. static void hpt3x3_init_chipset(struct pci_dev *dev)
  140. {
  141. u16 cmd;
  142. /* Initialize the board */
  143. pci_write_config_word(dev, 0x80, 0x00);
  144. /* Check if it is a 343 or a 363. 363 has COMMAND_MEMORY set */
  145. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  146. if (cmd & PCI_COMMAND_MEMORY)
  147. pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
  148. else
  149. pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
  150. }
  151. /**
  152. * hpt3x3_init_one - Initialise an HPT343/363
  153. * @pdev: PCI device
  154. * @id: Entry in match table
  155. *
  156. * Perform basic initialisation. We set the device up so we access all
  157. * ports via BAR4. This is necessary to work around errata.
  158. */
  159. static int hpt3x3_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
  160. {
  161. static const struct ata_port_info info = {
  162. .flags = ATA_FLAG_SLAVE_POSS,
  163. .pio_mask = ATA_PIO4,
  164. #if defined(CONFIG_PATA_HPT3X3_DMA)
  165. /* Further debug needed */
  166. .mwdma_mask = ATA_MWDMA2,
  167. .udma_mask = ATA_UDMA2,
  168. #endif
  169. .port_ops = &hpt3x3_port_ops
  170. };
  171. /* Register offsets of taskfiles in BAR4 area */
  172. static const u8 offset_cmd[2] = { 0x20, 0x28 };
  173. static const u8 offset_ctl[2] = { 0x36, 0x3E };
  174. const struct ata_port_info *ppi[] = { &info, NULL };
  175. struct ata_host *host;
  176. int i, rc;
  177. void __iomem *base;
  178. hpt3x3_init_chipset(pdev);
  179. ata_print_version_once(&pdev->dev, DRV_VERSION);
  180. host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
  181. if (!host)
  182. return -ENOMEM;
  183. /* acquire resources and fill host */
  184. rc = pcim_enable_device(pdev);
  185. if (rc)
  186. return rc;
  187. /* Everything is relative to BAR4 if we set up this way */
  188. rc = pcim_iomap_regions(pdev, 1 << 4, DRV_NAME);
  189. if (rc == -EBUSY)
  190. pcim_pin_device(pdev);
  191. if (rc)
  192. return rc;
  193. host->iomap = pcim_iomap_table(pdev);
  194. rc = dma_set_mask(&pdev->dev, ATA_DMA_MASK);
  195. if (rc)
  196. return rc;
  197. rc = dma_set_coherent_mask(&pdev->dev, ATA_DMA_MASK);
  198. if (rc)
  199. return rc;
  200. base = host->iomap[4]; /* Bus mastering base */
  201. for (i = 0; i < host->n_ports; i++) {
  202. struct ata_port *ap = host->ports[i];
  203. struct ata_ioports *ioaddr = &ap->ioaddr;
  204. ioaddr->cmd_addr = base + offset_cmd[i];
  205. ioaddr->altstatus_addr =
  206. ioaddr->ctl_addr = base + offset_ctl[i];
  207. ioaddr->scr_addr = NULL;
  208. ata_sff_std_ports(ioaddr);
  209. ioaddr->bmdma_addr = base + 8 * i;
  210. ata_port_pbar_desc(ap, 4, -1, "ioport");
  211. ata_port_pbar_desc(ap, 4, offset_cmd[i], "cmd");
  212. }
  213. pci_set_master(pdev);
  214. return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
  215. IRQF_SHARED, &hpt3x3_sht);
  216. }
  217. #ifdef CONFIG_PM_SLEEP
  218. static int hpt3x3_reinit_one(struct pci_dev *dev)
  219. {
  220. struct ata_host *host = pci_get_drvdata(dev);
  221. int rc;
  222. rc = ata_pci_device_do_resume(dev);
  223. if (rc)
  224. return rc;
  225. hpt3x3_init_chipset(dev);
  226. ata_host_resume(host);
  227. return 0;
  228. }
  229. #endif
  230. static const struct pci_device_id hpt3x3[] = {
  231. { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT343), },
  232. { },
  233. };
  234. static struct pci_driver hpt3x3_pci_driver = {
  235. .name = DRV_NAME,
  236. .id_table = hpt3x3,
  237. .probe = hpt3x3_init_one,
  238. .remove = ata_pci_remove_one,
  239. #ifdef CONFIG_PM_SLEEP
  240. .suspend = ata_pci_device_suspend,
  241. .resume = hpt3x3_reinit_one,
  242. #endif
  243. };
  244. module_pci_driver(hpt3x3_pci_driver);
  245. MODULE_AUTHOR("Alan Cox");
  246. MODULE_DESCRIPTION("low-level driver for the Highpoint HPT343/363");
  247. MODULE_LICENSE("GPL");
  248. MODULE_DEVICE_TABLE(pci, hpt3x3);
  249. MODULE_VERSION(DRV_VERSION);