uPD98401.h 12 KB

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  1. /* drivers/atm/uPD98401.h - NEC uPD98401 (SAR) declarations */
  2. /* Written 1995 by Werner Almesberger, EPFL LRC */
  3. #ifndef DRIVERS_ATM_uPD98401_H
  4. #define DRIVERS_ATM_uPD98401_H
  5. #define MAX_CRAM_SIZE (1 << 18) /* 2^18 words */
  6. #define RAM_INCREMENT 1024 /* check in 4 kB increments */
  7. #define uPD98401_PORTS 0x24 /* probably more ? */
  8. /*
  9. * Commands
  10. */
  11. #define uPD98401_OPEN_CHAN 0x20000000 /* open channel */
  12. #define uPD98401_CHAN_ADDR 0x0003fff8 /* channel address */
  13. #define uPD98401_CHAN_ADDR_SHIFT 3
  14. #define uPD98401_CLOSE_CHAN 0x24000000 /* close channel */
  15. #define uPD98401_CHAN_RT 0x02000000 /* RX/TX (0 TX, 1 RX) */
  16. #define uPD98401_DEACT_CHAN 0x28000000 /* deactivate channel */
  17. #define uPD98401_TX_READY 0x30000000 /* TX ready */
  18. #define uPD98401_ADD_BAT 0x34000000 /* add batches */
  19. #define uPD98401_POOL 0x000f0000 /* pool number */
  20. #define uPD98401_POOL_SHIFT 16
  21. #define uPD98401_POOL_NUMBAT 0x0000ffff /* number of batches */
  22. #define uPD98401_NOP 0x3f000000 /* NOP */
  23. #define uPD98401_IND_ACC 0x00000000 /* Indirect Access */
  24. #define uPD98401_IA_RW 0x10000000 /* Read/Write (0 W, 1 R) */
  25. #define uPD98401_IA_B3 0x08000000 /* Byte select, 1 enable */
  26. #define uPD98401_IA_B2 0x04000000
  27. #define uPD98401_IA_B1 0x02000000
  28. #define uPD98401_IA_B0 0x01000000
  29. #define uPD98401_IA_BALL 0x0f000000 /* whole longword */
  30. #define uPD98401_IA_TGT 0x000c0000 /* Target */
  31. #define uPD98401_IA_TGT_SHIFT 18
  32. #define uPD98401_IA_TGT_CM 0 /* - Control Memory */
  33. #define uPD98401_IA_TGT_SAR 1 /* - uPD98401 registers */
  34. #define uPD98401_IA_TGT_PHY 3 /* - PHY device */
  35. #define uPD98401_IA_ADDR 0x0003ffff
  36. /*
  37. * Command Register Status
  38. */
  39. #define uPD98401_BUSY 0x80000000 /* SAR is busy */
  40. #define uPD98401_LOCKED 0x40000000 /* SAR is locked by other CPU */
  41. /*
  42. * Indications
  43. */
  44. /* Normal (AAL5) Receive Indication */
  45. #define uPD98401_AAL5_UINFO 0xffff0000 /* user-supplied information */
  46. #define uPD98401_AAL5_UINFO_SHIFT 16
  47. #define uPD98401_AAL5_SIZE 0x0000ffff /* PDU size (in _CELLS_ !!) */
  48. #define uPD98401_AAL5_CHAN 0x7fff0000 /* Channel number */
  49. #define uPD98401_AAL5_CHAN_SHIFT 16
  50. #define uPD98401_AAL5_ERR 0x00008000 /* Error indication */
  51. #define uPD98401_AAL5_CI 0x00004000 /* Congestion Indication */
  52. #define uPD98401_AAL5_CLP 0x00002000 /* CLP (>= 1 cell had CLP=1) */
  53. #define uPD98401_AAL5_ES 0x00000f00 /* Error Status */
  54. #define uPD98401_AAL5_ES_SHIFT 8
  55. #define uPD98401_AAL5_ES_NONE 0 /* No error */
  56. #define uPD98401_AAL5_ES_FREE 1 /* Receiver free buf underflow */
  57. #define uPD98401_AAL5_ES_FIFO 2 /* Receiver FIFO overrun */
  58. #define uPD98401_AAL5_ES_TOOBIG 3 /* Maximum length violation */
  59. #define uPD98401_AAL5_ES_CRC 4 /* CRC error */
  60. #define uPD98401_AAL5_ES_ABORT 5 /* User abort */
  61. #define uPD98401_AAL5_ES_LENGTH 6 /* Length violation */
  62. #define uPD98401_AAL5_ES_T1 7 /* T1 error (timeout) */
  63. #define uPD98401_AAL5_ES_DEACT 8 /* Deactivated with DEACT_CHAN */
  64. #define uPD98401_AAL5_POOL 0x0000001f /* Free buffer pool number */
  65. /* Raw Cell Indication */
  66. #define uPD98401_RAW_UINFO uPD98401_AAL5_UINFO
  67. #define uPD98401_RAW_UINFO_SHIFT uPD98401_AAL5_UINFO_SHIFT
  68. #define uPD98401_RAW_HEC 0x000000ff /* HEC */
  69. #define uPD98401_RAW_CHAN uPD98401_AAL5_CHAN
  70. #define uPD98401_RAW_CHAN_SHIFT uPD98401_AAL5_CHAN_SHIFT
  71. /* Transmit Indication */
  72. #define uPD98401_TXI_CONN 0x7fff0000 /* Connection Number */
  73. #define uPD98401_TXI_CONN_SHIFT 16
  74. #define uPD98401_TXI_ACTIVE 0x00008000 /* Channel remains active */
  75. #define uPD98401_TXI_PQP 0x00007fff /* Packet Queue Pointer */
  76. /*
  77. * Directly Addressable Registers
  78. */
  79. #define uPD98401_GMR 0x00 /* General Mode Register */
  80. #define uPD98401_GSR 0x01 /* General Status Register */
  81. #define uPD98401_IMR 0x02 /* Interrupt Mask Register */
  82. #define uPD98401_RQU 0x03 /* Receive Queue Underrun */
  83. #define uPD98401_RQA 0x04 /* Receive Queue Alert */
  84. #define uPD98401_ADDR 0x05 /* Last Burst Address */
  85. #define uPD98401_VER 0x06 /* Version Number */
  86. #define uPD98401_SWR 0x07 /* Software Reset */
  87. #define uPD98401_CMR 0x08 /* Command Register */
  88. #define uPD98401_CMR_L 0x09 /* Command Register and Lock/Unlock */
  89. #define uPD98401_CER 0x0a /* Command Extension Register */
  90. #define uPD98401_CER_L 0x0b /* Command Ext Reg and Lock/Unlock */
  91. #define uPD98401_MSH(n) (0x10+(n)) /* Mailbox n Start Address High */
  92. #define uPD98401_MSL(n) (0x14+(n)) /* Mailbox n Start Address High */
  93. #define uPD98401_MBA(n) (0x18+(n)) /* Mailbox n Bottom Address */
  94. #define uPD98401_MTA(n) (0x1c+(n)) /* Mailbox n Tail Address */
  95. #define uPD98401_MWA(n) (0x20+(n)) /* Mailbox n Write Address */
  96. /* GMR is at 0x00 */
  97. #define uPD98401_GMR_ONE 0x80000000 /* Must be set to one */
  98. #define uPD98401_GMR_SLM 0x40000000 /* Address mode (0 word, 1 byte) */
  99. #define uPD98401_GMR_CPE 0x00008000 /* Control Memory Parity Enable */
  100. #define uPD98401_GMR_LP 0x00004000 /* Loopback */
  101. #define uPD98401_GMR_WA 0x00002000 /* Early Bus Write Abort/RDY */
  102. #define uPD98401_GMR_RA 0x00001000 /* Early Read Abort/RDY */
  103. #define uPD98401_GMR_SZ 0x00000f00 /* Burst Size Enable */
  104. #define uPD98401_BURST16 0x00000800 /* 16-word burst */
  105. #define uPD98401_BURST8 0x00000400 /* 8-word burst */
  106. #define uPD98401_BURST4 0x00000200 /* 4-word burst */
  107. #define uPD98401_BURST2 0x00000100 /* 2-word burst */
  108. #define uPD98401_GMR_AD 0x00000080 /* Address (burst resolution) Disable */
  109. #define uPD98401_GMR_BO 0x00000040 /* Byte Order (0 little, 1 big) */
  110. #define uPD98401_GMR_PM 0x00000020 /* Bus Parity Mode (0 byte, 1 word)*/
  111. #define uPD98401_GMR_PC 0x00000010 /* Bus Parity Control (0even,1odd) */
  112. #define uPD98401_GMR_BPE 0x00000008 /* Bus Parity Enable */
  113. #define uPD98401_GMR_DR 0x00000004 /* Receive Drop Mode (0drop,1don't)*/
  114. #define uPD98401_GMR_SE 0x00000002 /* Shapers Enable */
  115. #define uPD98401_GMR_RE 0x00000001 /* Receiver Enable */
  116. /* GSR is at 0x01, IMR is at 0x02 */
  117. #define uPD98401_INT_PI 0x80000000 /* PHY interrupt */
  118. #define uPD98401_INT_RQA 0x40000000 /* Receive Queue Alert */
  119. #define uPD98401_INT_RQU 0x20000000 /* Receive Queue Underrun */
  120. #define uPD98401_INT_RD 0x10000000 /* Receiver Deactivated */
  121. #define uPD98401_INT_SPE 0x08000000 /* System Parity Error */
  122. #define uPD98401_INT_CPE 0x04000000 /* Control Memory Parity Error */
  123. #define uPD98401_INT_SBE 0x02000000 /* System Bus Error */
  124. #define uPD98401_INT_IND 0x01000000 /* Initialization Done */
  125. #define uPD98401_INT_RCR 0x0000ff00 /* Raw Cell Received */
  126. #define uPD98401_INT_RCR_SHIFT 8
  127. #define uPD98401_INT_MF 0x000000f0 /* Mailbox Full */
  128. #define uPD98401_INT_MF_SHIFT 4
  129. #define uPD98401_INT_MM 0x0000000f /* Mailbox Modified */
  130. /* VER is at 0x06 */
  131. #define uPD98401_MAJOR 0x0000ff00 /* Major revision */
  132. #define uPD98401_MAJOR_SHIFT 8
  133. #define uPD98401_MINOR 0x000000ff /* Minor revision */
  134. /*
  135. * Indirectly Addressable Registers
  136. */
  137. #define uPD98401_IM(n) (0x40000+(n)) /* Scheduler n I and M */
  138. #define uPD98401_X(n) (0x40010+(n)) /* Scheduler n X */
  139. #define uPD98401_Y(n) (0x40020+(n)) /* Scheduler n Y */
  140. #define uPD98401_PC(n) (0x40030+(n)) /* Scheduler n P, C, p and c */
  141. #define uPD98401_PS(n) (0x40040+(n)) /* Scheduler n priority and status */
  142. /* IM contents */
  143. #define uPD98401_IM_I 0xff000000 /* I */
  144. #define uPD98401_IM_I_SHIFT 24
  145. #define uPD98401_IM_M 0x00ffffff /* M */
  146. /* PC contents */
  147. #define uPD98401_PC_P 0xff000000 /* P */
  148. #define uPD98401_PC_P_SHIFT 24
  149. #define uPD98401_PC_C 0x00ff0000 /* C */
  150. #define uPD98401_PC_C_SHIFT 16
  151. #define uPD98401_PC_p 0x0000ff00 /* p */
  152. #define uPD98401_PC_p_SHIFT 8
  153. #define uPD98401_PC_c 0x000000ff /* c */
  154. /* PS contents */
  155. #define uPD98401_PS_PRIO 0xf0 /* Priority level (0 high, 15 low) */
  156. #define uPD98401_PS_PRIO_SHIFT 4
  157. #define uPD98401_PS_S 0x08 /* Scan - must be 0 (internal) */
  158. #define uPD98401_PS_R 0x04 /* Round Robin (internal) */
  159. #define uPD98401_PS_A 0x02 /* Active (internal) */
  160. #define uPD98401_PS_E 0x01 /* Enabled */
  161. #define uPD98401_TOS 0x40100 /* Top of Stack Control Memory Address */
  162. #define uPD98401_SMA 0x40200 /* Shapers Control Memory Start Address */
  163. #define uPD98401_PMA 0x40201 /* Receive Pool Control Memory Start Address */
  164. #define uPD98401_T1R 0x40300 /* T1 Register */
  165. #define uPD98401_VRR 0x40301 /* VPI/VCI Reduction Register/Recv. Shutdown */
  166. #define uPD98401_TSR 0x40302 /* Time-Stamp Register */
  167. /* VRR is at 0x40301 */
  168. #define uPD98401_VRR_SDM 0x80000000 /* Shutdown Mode */
  169. #define uPD98401_VRR_SHIFT 0x000f0000 /* VPI/VCI Shift */
  170. #define uPD98401_VRR_SHIFT_SHIFT 16
  171. #define uPD98401_VRR_MASK 0x0000ffff /* VPI/VCI mask */
  172. /*
  173. * TX packet descriptor
  174. */
  175. #define uPD98401_TXPD_SIZE 16 /* descriptor size (in bytes) */
  176. #define uPD98401_TXPD_V 0x80000000 /* Valid bit */
  177. #define uPD98401_TXPD_DP 0x40000000 /* Descriptor (1) or Pointer (0) */
  178. #define uPD98401_TXPD_SM 0x20000000 /* Single (1) or Multiple (0) */
  179. #define uPD98401_TXPD_CLPM 0x18000000 /* CLP mode */
  180. #define uPD98401_CLPM_0 0 /* 00 CLP = 0 */
  181. #define uPD98401_CLPM_1 3 /* 11 CLP = 1 */
  182. #define uPD98401_CLPM_LAST 1 /* 01 CLP unless last cell */
  183. #define uPD98401_TXPD_CLPM_SHIFT 27
  184. #define uPD98401_TXPD_PTI 0x07000000 /* PTI pattern */
  185. #define uPD98401_TXPD_PTI_SHIFT 24
  186. #define uPD98401_TXPD_GFC 0x00f00000 /* GFC pattern */
  187. #define uPD98401_TXPD_GFC_SHIFT 20
  188. #define uPD98401_TXPD_C10 0x00040000 /* insert CRC-10 */
  189. #define uPD98401_TXPD_AAL5 0x00020000 /* AAL5 processing */
  190. #define uPD98401_TXPD_MB 0x00010000 /* TX mailbox number */
  191. #define uPD98401_TXPD_UU 0x0000ff00 /* CPCS-UU */
  192. #define uPD98401_TXPD_UU_SHIFT 8
  193. #define uPD98401_TXPD_CPI 0x000000ff /* CPI */
  194. /*
  195. * TX buffer descriptor
  196. */
  197. #define uPD98401_TXBD_SIZE 8 /* descriptor size (in bytes) */
  198. #define uPD98401_TXBD_LAST 0x80000000 /* last buffer in packet */
  199. /*
  200. * TX VC table
  201. */
  202. /* 1st word has the same structure as in a TX packet descriptor */
  203. #define uPD98401_TXVC_L 0x80000000 /* last buffer */
  204. #define uPD98401_TXVC_SHP 0x0f000000 /* shaper number */
  205. #define uPD98401_TXVC_SHP_SHIFT 24
  206. #define uPD98401_TXVC_VPI 0x00ff0000 /* VPI */
  207. #define uPD98401_TXVC_VPI_SHIFT 16
  208. #define uPD98401_TXVC_VCI 0x0000ffff /* VCI */
  209. #define uPD98401_TXVC_QRP 6 /* Queue Read Pointer is in word 6 */
  210. /*
  211. * RX free buffer pools descriptor
  212. */
  213. #define uPD98401_RXFP_ALERT 0x70000000 /* low water mark */
  214. #define uPD98401_RXFP_ALERT_SHIFT 28
  215. #define uPD98401_RXFP_BFSZ 0x0f000000 /* buffer size, 64*2^n */
  216. #define uPD98401_RXFP_BFSZ_SHIFT 24
  217. #define uPD98401_RXFP_BTSZ 0x00ff0000 /* batch size, n+1 */
  218. #define uPD98401_RXFP_BTSZ_SHIFT 16
  219. #define uPD98401_RXFP_REMAIN 0x0000ffff /* remaining batches in pool */
  220. /*
  221. * RX VC table
  222. */
  223. #define uPD98401_RXVC_BTSZ 0xff000000 /* remaining free buffers in batch */
  224. #define uPD98401_RXVC_BTSZ_SHIFT 24
  225. #define uPD98401_RXVC_MB 0x00200000 /* RX mailbox number */
  226. #define uPD98401_RXVC_POOL 0x001f0000 /* free buffer pool number */
  227. #define uPD98401_RXVC_POOL_SHIFT 16
  228. #define uPD98401_RXVC_UINFO 0x0000ffff /* user-supplied information */
  229. #define uPD98401_RXVC_T1 0xffff0000 /* T1 timestamp */
  230. #define uPD98401_RXVC_T1_SHIFT 16
  231. #define uPD98401_RXVC_PR 0x00008000 /* Packet Reception, 1 if busy */
  232. #define uPD98401_RXVC_DR 0x00004000 /* FIFO Drop */
  233. #define uPD98401_RXVC_OD 0x00001000 /* Drop OAM cells */
  234. #define uPD98401_RXVC_AR 0x00000800 /* AAL5 or raw cell; 1 if AAL5 */
  235. #define uPD98401_RXVC_MAXSEG 0x000007ff /* max number of segments per PDU */
  236. #define uPD98401_RXVC_REM 0xfffe0000 /* remaining words in curr buffer */
  237. #define uPD98401_RXVC_REM_SHIFT 17
  238. #define uPD98401_RXVC_CLP 0x00010000 /* CLP received */
  239. #define uPD98401_RXVC_BFA 0x00008000 /* Buffer Assigned */
  240. #define uPD98401_RXVC_BTA 0x00004000 /* Batch Assigned */
  241. #define uPD98401_RXVC_CI 0x00002000 /* Congestion Indication */
  242. #define uPD98401_RXVC_DD 0x00001000 /* Dropping incoming cells */
  243. #define uPD98401_RXVC_DP 0x00000800 /* like PR ? */
  244. #define uPD98401_RXVC_CURSEG 0x000007ff /* Current Segment count */
  245. /*
  246. * RX lookup table
  247. */
  248. #define uPD98401_RXLT_ENBL 0x8000 /* Enable */
  249. #endif