iproc-rng200.c 6.3 KB

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  1. /*
  2. * Copyright (C) 2015 Broadcom Corporation
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License as
  6. * published by the Free Software Foundation version 2.
  7. *
  8. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  9. * kind, whether express or implied; without even the implied warranty
  10. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. /*
  14. * DESCRIPTION: The Broadcom iProc RNG200 Driver
  15. */
  16. #include <linux/hw_random.h>
  17. #include <linux/init.h>
  18. #include <linux/io.h>
  19. #include <linux/kernel.h>
  20. #include <linux/module.h>
  21. #include <linux/of_address.h>
  22. #include <linux/of_platform.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/delay.h>
  25. /* Registers */
  26. #define RNG_CTRL_OFFSET 0x00
  27. #define RNG_CTRL_RNG_RBGEN_MASK 0x00001FFF
  28. #define RNG_CTRL_RNG_RBGEN_ENABLE 0x00000001
  29. #define RNG_CTRL_RNG_RBGEN_DISABLE 0x00000000
  30. #define RNG_SOFT_RESET_OFFSET 0x04
  31. #define RNG_SOFT_RESET 0x00000001
  32. #define RBG_SOFT_RESET_OFFSET 0x08
  33. #define RBG_SOFT_RESET 0x00000001
  34. #define RNG_INT_STATUS_OFFSET 0x18
  35. #define RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK 0x80000000
  36. #define RNG_INT_STATUS_STARTUP_TRANSITIONS_MET_IRQ_MASK 0x00020000
  37. #define RNG_INT_STATUS_NIST_FAIL_IRQ_MASK 0x00000020
  38. #define RNG_INT_STATUS_TOTAL_BITS_COUNT_IRQ_MASK 0x00000001
  39. #define RNG_FIFO_DATA_OFFSET 0x20
  40. #define RNG_FIFO_COUNT_OFFSET 0x24
  41. #define RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK 0x000000FF
  42. struct iproc_rng200_dev {
  43. struct hwrng rng;
  44. void __iomem *base;
  45. };
  46. #define to_rng_priv(rng) container_of(rng, struct iproc_rng200_dev, rng)
  47. static void iproc_rng200_restart(void __iomem *rng_base)
  48. {
  49. uint32_t val;
  50. /* Disable RBG */
  51. val = ioread32(rng_base + RNG_CTRL_OFFSET);
  52. val &= ~RNG_CTRL_RNG_RBGEN_MASK;
  53. val |= RNG_CTRL_RNG_RBGEN_DISABLE;
  54. iowrite32(val, rng_base + RNG_CTRL_OFFSET);
  55. /* Clear all interrupt status */
  56. iowrite32(0xFFFFFFFFUL, rng_base + RNG_INT_STATUS_OFFSET);
  57. /* Reset RNG and RBG */
  58. val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET);
  59. val |= RBG_SOFT_RESET;
  60. iowrite32(val, rng_base + RBG_SOFT_RESET_OFFSET);
  61. val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET);
  62. val |= RNG_SOFT_RESET;
  63. iowrite32(val, rng_base + RNG_SOFT_RESET_OFFSET);
  64. val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET);
  65. val &= ~RNG_SOFT_RESET;
  66. iowrite32(val, rng_base + RNG_SOFT_RESET_OFFSET);
  67. val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET);
  68. val &= ~RBG_SOFT_RESET;
  69. iowrite32(val, rng_base + RBG_SOFT_RESET_OFFSET);
  70. /* Enable RBG */
  71. val = ioread32(rng_base + RNG_CTRL_OFFSET);
  72. val &= ~RNG_CTRL_RNG_RBGEN_MASK;
  73. val |= RNG_CTRL_RNG_RBGEN_ENABLE;
  74. iowrite32(val, rng_base + RNG_CTRL_OFFSET);
  75. }
  76. static int iproc_rng200_read(struct hwrng *rng, void *buf, size_t max,
  77. bool wait)
  78. {
  79. struct iproc_rng200_dev *priv = to_rng_priv(rng);
  80. uint32_t num_remaining = max;
  81. uint32_t status;
  82. #define MAX_RESETS_PER_READ 1
  83. uint32_t num_resets = 0;
  84. #define MAX_IDLE_TIME (1 * HZ)
  85. unsigned long idle_endtime = jiffies + MAX_IDLE_TIME;
  86. while ((num_remaining > 0) && time_before(jiffies, idle_endtime)) {
  87. /* Is RNG sane? If not, reset it. */
  88. status = ioread32(priv->base + RNG_INT_STATUS_OFFSET);
  89. if ((status & (RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK |
  90. RNG_INT_STATUS_NIST_FAIL_IRQ_MASK)) != 0) {
  91. if (num_resets >= MAX_RESETS_PER_READ)
  92. return max - num_remaining;
  93. iproc_rng200_restart(priv->base);
  94. num_resets++;
  95. }
  96. /* Are there any random numbers available? */
  97. if ((ioread32(priv->base + RNG_FIFO_COUNT_OFFSET) &
  98. RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK) > 0) {
  99. if (num_remaining >= sizeof(uint32_t)) {
  100. /* Buffer has room to store entire word */
  101. *(uint32_t *)buf = ioread32(priv->base +
  102. RNG_FIFO_DATA_OFFSET);
  103. buf += sizeof(uint32_t);
  104. num_remaining -= sizeof(uint32_t);
  105. } else {
  106. /* Buffer can only store partial word */
  107. uint32_t rnd_number = ioread32(priv->base +
  108. RNG_FIFO_DATA_OFFSET);
  109. memcpy(buf, &rnd_number, num_remaining);
  110. buf += num_remaining;
  111. num_remaining = 0;
  112. }
  113. /* Reset the IDLE timeout */
  114. idle_endtime = jiffies + MAX_IDLE_TIME;
  115. } else {
  116. if (!wait)
  117. /* Cannot wait, return immediately */
  118. return max - num_remaining;
  119. /* Can wait, give others chance to run */
  120. usleep_range(min(num_remaining * 10, 500U), 500);
  121. }
  122. }
  123. return max - num_remaining;
  124. }
  125. static int iproc_rng200_init(struct hwrng *rng)
  126. {
  127. struct iproc_rng200_dev *priv = to_rng_priv(rng);
  128. uint32_t val;
  129. /* Setup RNG. */
  130. val = ioread32(priv->base + RNG_CTRL_OFFSET);
  131. val &= ~RNG_CTRL_RNG_RBGEN_MASK;
  132. val |= RNG_CTRL_RNG_RBGEN_ENABLE;
  133. iowrite32(val, priv->base + RNG_CTRL_OFFSET);
  134. return 0;
  135. }
  136. static void iproc_rng200_cleanup(struct hwrng *rng)
  137. {
  138. struct iproc_rng200_dev *priv = to_rng_priv(rng);
  139. uint32_t val;
  140. /* Disable RNG hardware */
  141. val = ioread32(priv->base + RNG_CTRL_OFFSET);
  142. val &= ~RNG_CTRL_RNG_RBGEN_MASK;
  143. val |= RNG_CTRL_RNG_RBGEN_DISABLE;
  144. iowrite32(val, priv->base + RNG_CTRL_OFFSET);
  145. }
  146. static int iproc_rng200_probe(struct platform_device *pdev)
  147. {
  148. struct iproc_rng200_dev *priv;
  149. struct resource *res;
  150. struct device *dev = &pdev->dev;
  151. int ret;
  152. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  153. if (!priv)
  154. return -ENOMEM;
  155. /* Map peripheral */
  156. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  157. if (!res) {
  158. dev_err(dev, "failed to get rng resources\n");
  159. return -EINVAL;
  160. }
  161. priv->base = devm_ioremap_resource(dev, res);
  162. if (IS_ERR(priv->base)) {
  163. dev_err(dev, "failed to remap rng regs\n");
  164. return PTR_ERR(priv->base);
  165. }
  166. priv->rng.name = "iproc-rng200",
  167. priv->rng.read = iproc_rng200_read,
  168. priv->rng.init = iproc_rng200_init,
  169. priv->rng.cleanup = iproc_rng200_cleanup,
  170. /* Register driver */
  171. ret = devm_hwrng_register(dev, &priv->rng);
  172. if (ret) {
  173. dev_err(dev, "hwrng registration failed\n");
  174. return ret;
  175. }
  176. dev_info(dev, "hwrng registered\n");
  177. return 0;
  178. }
  179. static const struct of_device_id iproc_rng200_of_match[] = {
  180. { .compatible = "brcm,iproc-rng200", },
  181. {},
  182. };
  183. MODULE_DEVICE_TABLE(of, iproc_rng200_of_match);
  184. static struct platform_driver iproc_rng200_driver = {
  185. .driver = {
  186. .name = "iproc-rng200",
  187. .of_match_table = iproc_rng200_of_match,
  188. },
  189. .probe = iproc_rng200_probe,
  190. };
  191. module_platform_driver(iproc_rng200_driver);
  192. MODULE_AUTHOR("Broadcom");
  193. MODULE_DESCRIPTION("iProc RNG200 Random Number Generator driver");
  194. MODULE_LICENSE("GPL v2");