tlclk.c 23 KB

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  1. /*
  2. * Telecom Clock driver for Intel NetStructure(tm) MPCBL0010
  3. *
  4. * Copyright (C) 2005 Kontron Canada
  5. *
  6. * All rights reserved.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or (at
  11. * your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  16. * NON INFRINGEMENT. See the GNU General Public License for more
  17. * details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22. *
  23. * Send feedback to <sebastien.bouchard@ca.kontron.com> and the current
  24. * Maintainer <mark.gross@intel.com>
  25. *
  26. * Description : This is the TELECOM CLOCK module driver for the ATCA
  27. * MPCBL0010 ATCA computer.
  28. */
  29. #include <linux/module.h>
  30. #include <linux/init.h>
  31. #include <linux/kernel.h> /* printk() */
  32. #include <linux/fs.h> /* everything... */
  33. #include <linux/errno.h> /* error codes */
  34. #include <linux/sched.h>
  35. #include <linux/slab.h>
  36. #include <linux/ioport.h>
  37. #include <linux/interrupt.h>
  38. #include <linux/spinlock.h>
  39. #include <linux/mutex.h>
  40. #include <linux/timer.h>
  41. #include <linux/sysfs.h>
  42. #include <linux/device.h>
  43. #include <linux/miscdevice.h>
  44. #include <linux/platform_device.h>
  45. #include <asm/io.h> /* inb/outb */
  46. #include <asm/uaccess.h>
  47. MODULE_AUTHOR("Sebastien Bouchard <sebastien.bouchard@ca.kontron.com>");
  48. MODULE_LICENSE("GPL");
  49. /*Hardware Reset of the PLL */
  50. #define RESET_ON 0x00
  51. #define RESET_OFF 0x01
  52. /* MODE SELECT */
  53. #define NORMAL_MODE 0x00
  54. #define HOLDOVER_MODE 0x10
  55. #define FREERUN_MODE 0x20
  56. /* FILTER SELECT */
  57. #define FILTER_6HZ 0x04
  58. #define FILTER_12HZ 0x00
  59. /* SELECT REFERENCE FREQUENCY */
  60. #define REF_CLK1_8kHz 0x00
  61. #define REF_CLK2_19_44MHz 0x02
  62. /* Select primary or secondary redundant clock */
  63. #define PRIMARY_CLOCK 0x00
  64. #define SECONDARY_CLOCK 0x01
  65. /* CLOCK TRANSMISSION DEFINE */
  66. #define CLK_8kHz 0xff
  67. #define CLK_16_384MHz 0xfb
  68. #define CLK_1_544MHz 0x00
  69. #define CLK_2_048MHz 0x01
  70. #define CLK_4_096MHz 0x02
  71. #define CLK_6_312MHz 0x03
  72. #define CLK_8_192MHz 0x04
  73. #define CLK_19_440MHz 0x06
  74. #define CLK_8_592MHz 0x08
  75. #define CLK_11_184MHz 0x09
  76. #define CLK_34_368MHz 0x0b
  77. #define CLK_44_736MHz 0x0a
  78. /* RECEIVED REFERENCE */
  79. #define AMC_B1 0
  80. #define AMC_B2 1
  81. /* HARDWARE SWITCHING DEFINE */
  82. #define HW_ENABLE 0x80
  83. #define HW_DISABLE 0x00
  84. /* HARDWARE SWITCHING MODE DEFINE */
  85. #define PLL_HOLDOVER 0x40
  86. #define LOST_CLOCK 0x00
  87. /* ALARMS DEFINE */
  88. #define UNLOCK_MASK 0x10
  89. #define HOLDOVER_MASK 0x20
  90. #define SEC_LOST_MASK 0x40
  91. #define PRI_LOST_MASK 0x80
  92. /* INTERRUPT CAUSE DEFINE */
  93. #define PRI_LOS_01_MASK 0x01
  94. #define PRI_LOS_10_MASK 0x02
  95. #define SEC_LOS_01_MASK 0x04
  96. #define SEC_LOS_10_MASK 0x08
  97. #define HOLDOVER_01_MASK 0x10
  98. #define HOLDOVER_10_MASK 0x20
  99. #define UNLOCK_01_MASK 0x40
  100. #define UNLOCK_10_MASK 0x80
  101. struct tlclk_alarms {
  102. __u32 lost_clocks;
  103. __u32 lost_primary_clock;
  104. __u32 lost_secondary_clock;
  105. __u32 primary_clock_back;
  106. __u32 secondary_clock_back;
  107. __u32 switchover_primary;
  108. __u32 switchover_secondary;
  109. __u32 pll_holdover;
  110. __u32 pll_end_holdover;
  111. __u32 pll_lost_sync;
  112. __u32 pll_sync;
  113. };
  114. /* Telecom clock I/O register definition */
  115. #define TLCLK_BASE 0xa08
  116. #define TLCLK_REG0 TLCLK_BASE
  117. #define TLCLK_REG1 (TLCLK_BASE+1)
  118. #define TLCLK_REG2 (TLCLK_BASE+2)
  119. #define TLCLK_REG3 (TLCLK_BASE+3)
  120. #define TLCLK_REG4 (TLCLK_BASE+4)
  121. #define TLCLK_REG5 (TLCLK_BASE+5)
  122. #define TLCLK_REG6 (TLCLK_BASE+6)
  123. #define TLCLK_REG7 (TLCLK_BASE+7)
  124. #define SET_PORT_BITS(port, mask, val) outb(((inb(port) & mask) | val), port)
  125. /* 0 = Dynamic allocation of the major device number */
  126. #define TLCLK_MAJOR 0
  127. /* sysfs interface definition:
  128. Upon loading the driver will create a sysfs directory under
  129. /sys/devices/platform/telco_clock.
  130. This directory exports the following interfaces. There operation is
  131. documented in the MCPBL0010 TPS under the Telecom Clock API section, 11.4.
  132. alarms :
  133. current_ref :
  134. received_ref_clk3a :
  135. received_ref_clk3b :
  136. enable_clk3a_output :
  137. enable_clk3b_output :
  138. enable_clka0_output :
  139. enable_clka1_output :
  140. enable_clkb0_output :
  141. enable_clkb1_output :
  142. filter_select :
  143. hardware_switching :
  144. hardware_switching_mode :
  145. telclock_version :
  146. mode_select :
  147. refalign :
  148. reset :
  149. select_amcb1_transmit_clock :
  150. select_amcb2_transmit_clock :
  151. select_redundant_clock :
  152. select_ref_frequency :
  153. All sysfs interfaces are integers in hex format, i.e echo 99 > refalign
  154. has the same effect as echo 0x99 > refalign.
  155. */
  156. static unsigned int telclk_interrupt;
  157. static int int_events; /* Event that generate a interrupt */
  158. static int got_event; /* if events processing have been done */
  159. static void switchover_timeout(unsigned long data);
  160. static struct timer_list switchover_timer =
  161. TIMER_INITIALIZER(switchover_timeout , 0, 0);
  162. static unsigned long tlclk_timer_data;
  163. static struct tlclk_alarms *alarm_events;
  164. static DEFINE_SPINLOCK(event_lock);
  165. static int tlclk_major = TLCLK_MAJOR;
  166. static irqreturn_t tlclk_interrupt(int irq, void *dev_id);
  167. static DECLARE_WAIT_QUEUE_HEAD(wq);
  168. static unsigned long useflags;
  169. static DEFINE_MUTEX(tlclk_mutex);
  170. static int tlclk_open(struct inode *inode, struct file *filp)
  171. {
  172. int result;
  173. mutex_lock(&tlclk_mutex);
  174. if (test_and_set_bit(0, &useflags)) {
  175. result = -EBUSY;
  176. /* this legacy device is always one per system and it doesn't
  177. * know how to handle multiple concurrent clients.
  178. */
  179. goto out;
  180. }
  181. /* Make sure there is no interrupt pending while
  182. * initialising interrupt handler */
  183. inb(TLCLK_REG6);
  184. /* This device is wired through the FPGA IO space of the ATCA blade
  185. * we can't share this IRQ */
  186. result = request_irq(telclk_interrupt, &tlclk_interrupt,
  187. 0, "telco_clock", tlclk_interrupt);
  188. if (result == -EBUSY)
  189. printk(KERN_ERR "tlclk: Interrupt can't be reserved.\n");
  190. else
  191. inb(TLCLK_REG6); /* Clear interrupt events */
  192. out:
  193. mutex_unlock(&tlclk_mutex);
  194. return result;
  195. }
  196. static int tlclk_release(struct inode *inode, struct file *filp)
  197. {
  198. free_irq(telclk_interrupt, tlclk_interrupt);
  199. clear_bit(0, &useflags);
  200. return 0;
  201. }
  202. static ssize_t tlclk_read(struct file *filp, char __user *buf, size_t count,
  203. loff_t *f_pos)
  204. {
  205. if (count < sizeof(struct tlclk_alarms))
  206. return -EIO;
  207. if (mutex_lock_interruptible(&tlclk_mutex))
  208. return -EINTR;
  209. wait_event_interruptible(wq, got_event);
  210. if (copy_to_user(buf, alarm_events, sizeof(struct tlclk_alarms))) {
  211. mutex_unlock(&tlclk_mutex);
  212. return -EFAULT;
  213. }
  214. memset(alarm_events, 0, sizeof(struct tlclk_alarms));
  215. got_event = 0;
  216. mutex_unlock(&tlclk_mutex);
  217. return sizeof(struct tlclk_alarms);
  218. }
  219. static const struct file_operations tlclk_fops = {
  220. .read = tlclk_read,
  221. .open = tlclk_open,
  222. .release = tlclk_release,
  223. .llseek = noop_llseek,
  224. };
  225. static struct miscdevice tlclk_miscdev = {
  226. .minor = MISC_DYNAMIC_MINOR,
  227. .name = "telco_clock",
  228. .fops = &tlclk_fops,
  229. };
  230. static ssize_t show_current_ref(struct device *d,
  231. struct device_attribute *attr, char *buf)
  232. {
  233. unsigned long ret_val;
  234. unsigned long flags;
  235. spin_lock_irqsave(&event_lock, flags);
  236. ret_val = ((inb(TLCLK_REG1) & 0x08) >> 3);
  237. spin_unlock_irqrestore(&event_lock, flags);
  238. return sprintf(buf, "0x%lX\n", ret_val);
  239. }
  240. static DEVICE_ATTR(current_ref, S_IRUGO, show_current_ref, NULL);
  241. static ssize_t show_telclock_version(struct device *d,
  242. struct device_attribute *attr, char *buf)
  243. {
  244. unsigned long ret_val;
  245. unsigned long flags;
  246. spin_lock_irqsave(&event_lock, flags);
  247. ret_val = inb(TLCLK_REG5);
  248. spin_unlock_irqrestore(&event_lock, flags);
  249. return sprintf(buf, "0x%lX\n", ret_val);
  250. }
  251. static DEVICE_ATTR(telclock_version, S_IRUGO,
  252. show_telclock_version, NULL);
  253. static ssize_t show_alarms(struct device *d,
  254. struct device_attribute *attr, char *buf)
  255. {
  256. unsigned long ret_val;
  257. unsigned long flags;
  258. spin_lock_irqsave(&event_lock, flags);
  259. ret_val = (inb(TLCLK_REG2) & 0xf0);
  260. spin_unlock_irqrestore(&event_lock, flags);
  261. return sprintf(buf, "0x%lX\n", ret_val);
  262. }
  263. static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
  264. static ssize_t store_received_ref_clk3a(struct device *d,
  265. struct device_attribute *attr, const char *buf, size_t count)
  266. {
  267. unsigned long tmp;
  268. unsigned char val;
  269. unsigned long flags;
  270. sscanf(buf, "%lX", &tmp);
  271. dev_dbg(d, ": tmp = 0x%lX\n", tmp);
  272. val = (unsigned char)tmp;
  273. spin_lock_irqsave(&event_lock, flags);
  274. SET_PORT_BITS(TLCLK_REG1, 0xef, val);
  275. spin_unlock_irqrestore(&event_lock, flags);
  276. return strnlen(buf, count);
  277. }
  278. static DEVICE_ATTR(received_ref_clk3a, (S_IWUSR|S_IWGRP), NULL,
  279. store_received_ref_clk3a);
  280. static ssize_t store_received_ref_clk3b(struct device *d,
  281. struct device_attribute *attr, const char *buf, size_t count)
  282. {
  283. unsigned long tmp;
  284. unsigned char val;
  285. unsigned long flags;
  286. sscanf(buf, "%lX", &tmp);
  287. dev_dbg(d, ": tmp = 0x%lX\n", tmp);
  288. val = (unsigned char)tmp;
  289. spin_lock_irqsave(&event_lock, flags);
  290. SET_PORT_BITS(TLCLK_REG1, 0xdf, val << 1);
  291. spin_unlock_irqrestore(&event_lock, flags);
  292. return strnlen(buf, count);
  293. }
  294. static DEVICE_ATTR(received_ref_clk3b, (S_IWUSR|S_IWGRP), NULL,
  295. store_received_ref_clk3b);
  296. static ssize_t store_enable_clk3b_output(struct device *d,
  297. struct device_attribute *attr, const char *buf, size_t count)
  298. {
  299. unsigned long tmp;
  300. unsigned char val;
  301. unsigned long flags;
  302. sscanf(buf, "%lX", &tmp);
  303. dev_dbg(d, ": tmp = 0x%lX\n", tmp);
  304. val = (unsigned char)tmp;
  305. spin_lock_irqsave(&event_lock, flags);
  306. SET_PORT_BITS(TLCLK_REG3, 0x7f, val << 7);
  307. spin_unlock_irqrestore(&event_lock, flags);
  308. return strnlen(buf, count);
  309. }
  310. static DEVICE_ATTR(enable_clk3b_output, (S_IWUSR|S_IWGRP), NULL,
  311. store_enable_clk3b_output);
  312. static ssize_t store_enable_clk3a_output(struct device *d,
  313. struct device_attribute *attr, const char *buf, size_t count)
  314. {
  315. unsigned long flags;
  316. unsigned long tmp;
  317. unsigned char val;
  318. sscanf(buf, "%lX", &tmp);
  319. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  320. val = (unsigned char)tmp;
  321. spin_lock_irqsave(&event_lock, flags);
  322. SET_PORT_BITS(TLCLK_REG3, 0xbf, val << 6);
  323. spin_unlock_irqrestore(&event_lock, flags);
  324. return strnlen(buf, count);
  325. }
  326. static DEVICE_ATTR(enable_clk3a_output, (S_IWUSR|S_IWGRP), NULL,
  327. store_enable_clk3a_output);
  328. static ssize_t store_enable_clkb1_output(struct device *d,
  329. struct device_attribute *attr, const char *buf, size_t count)
  330. {
  331. unsigned long flags;
  332. unsigned long tmp;
  333. unsigned char val;
  334. sscanf(buf, "%lX", &tmp);
  335. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  336. val = (unsigned char)tmp;
  337. spin_lock_irqsave(&event_lock, flags);
  338. SET_PORT_BITS(TLCLK_REG2, 0xf7, val << 3);
  339. spin_unlock_irqrestore(&event_lock, flags);
  340. return strnlen(buf, count);
  341. }
  342. static DEVICE_ATTR(enable_clkb1_output, (S_IWUSR|S_IWGRP), NULL,
  343. store_enable_clkb1_output);
  344. static ssize_t store_enable_clka1_output(struct device *d,
  345. struct device_attribute *attr, const char *buf, size_t count)
  346. {
  347. unsigned long flags;
  348. unsigned long tmp;
  349. unsigned char val;
  350. sscanf(buf, "%lX", &tmp);
  351. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  352. val = (unsigned char)tmp;
  353. spin_lock_irqsave(&event_lock, flags);
  354. SET_PORT_BITS(TLCLK_REG2, 0xfb, val << 2);
  355. spin_unlock_irqrestore(&event_lock, flags);
  356. return strnlen(buf, count);
  357. }
  358. static DEVICE_ATTR(enable_clka1_output, (S_IWUSR|S_IWGRP), NULL,
  359. store_enable_clka1_output);
  360. static ssize_t store_enable_clkb0_output(struct device *d,
  361. struct device_attribute *attr, const char *buf, size_t count)
  362. {
  363. unsigned long flags;
  364. unsigned long tmp;
  365. unsigned char val;
  366. sscanf(buf, "%lX", &tmp);
  367. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  368. val = (unsigned char)tmp;
  369. spin_lock_irqsave(&event_lock, flags);
  370. SET_PORT_BITS(TLCLK_REG2, 0xfd, val << 1);
  371. spin_unlock_irqrestore(&event_lock, flags);
  372. return strnlen(buf, count);
  373. }
  374. static DEVICE_ATTR(enable_clkb0_output, (S_IWUSR|S_IWGRP), NULL,
  375. store_enable_clkb0_output);
  376. static ssize_t store_enable_clka0_output(struct device *d,
  377. struct device_attribute *attr, const char *buf, size_t count)
  378. {
  379. unsigned long flags;
  380. unsigned long tmp;
  381. unsigned char val;
  382. sscanf(buf, "%lX", &tmp);
  383. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  384. val = (unsigned char)tmp;
  385. spin_lock_irqsave(&event_lock, flags);
  386. SET_PORT_BITS(TLCLK_REG2, 0xfe, val);
  387. spin_unlock_irqrestore(&event_lock, flags);
  388. return strnlen(buf, count);
  389. }
  390. static DEVICE_ATTR(enable_clka0_output, (S_IWUSR|S_IWGRP), NULL,
  391. store_enable_clka0_output);
  392. static ssize_t store_select_amcb2_transmit_clock(struct device *d,
  393. struct device_attribute *attr, const char *buf, size_t count)
  394. {
  395. unsigned long flags;
  396. unsigned long tmp;
  397. unsigned char val;
  398. sscanf(buf, "%lX", &tmp);
  399. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  400. val = (unsigned char)tmp;
  401. spin_lock_irqsave(&event_lock, flags);
  402. if ((val == CLK_8kHz) || (val == CLK_16_384MHz)) {
  403. SET_PORT_BITS(TLCLK_REG3, 0xc7, 0x28);
  404. SET_PORT_BITS(TLCLK_REG1, 0xfb, ~val);
  405. } else if (val >= CLK_8_592MHz) {
  406. SET_PORT_BITS(TLCLK_REG3, 0xc7, 0x38);
  407. switch (val) {
  408. case CLK_8_592MHz:
  409. SET_PORT_BITS(TLCLK_REG0, 0xfc, 2);
  410. break;
  411. case CLK_11_184MHz:
  412. SET_PORT_BITS(TLCLK_REG0, 0xfc, 0);
  413. break;
  414. case CLK_34_368MHz:
  415. SET_PORT_BITS(TLCLK_REG0, 0xfc, 3);
  416. break;
  417. case CLK_44_736MHz:
  418. SET_PORT_BITS(TLCLK_REG0, 0xfc, 1);
  419. break;
  420. }
  421. } else
  422. SET_PORT_BITS(TLCLK_REG3, 0xc7, val << 3);
  423. spin_unlock_irqrestore(&event_lock, flags);
  424. return strnlen(buf, count);
  425. }
  426. static DEVICE_ATTR(select_amcb2_transmit_clock, (S_IWUSR|S_IWGRP), NULL,
  427. store_select_amcb2_transmit_clock);
  428. static ssize_t store_select_amcb1_transmit_clock(struct device *d,
  429. struct device_attribute *attr, const char *buf, size_t count)
  430. {
  431. unsigned long tmp;
  432. unsigned char val;
  433. unsigned long flags;
  434. sscanf(buf, "%lX", &tmp);
  435. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  436. val = (unsigned char)tmp;
  437. spin_lock_irqsave(&event_lock, flags);
  438. if ((val == CLK_8kHz) || (val == CLK_16_384MHz)) {
  439. SET_PORT_BITS(TLCLK_REG3, 0xf8, 0x5);
  440. SET_PORT_BITS(TLCLK_REG1, 0xfb, ~val);
  441. } else if (val >= CLK_8_592MHz) {
  442. SET_PORT_BITS(TLCLK_REG3, 0xf8, 0x7);
  443. switch (val) {
  444. case CLK_8_592MHz:
  445. SET_PORT_BITS(TLCLK_REG0, 0xfc, 2);
  446. break;
  447. case CLK_11_184MHz:
  448. SET_PORT_BITS(TLCLK_REG0, 0xfc, 0);
  449. break;
  450. case CLK_34_368MHz:
  451. SET_PORT_BITS(TLCLK_REG0, 0xfc, 3);
  452. break;
  453. case CLK_44_736MHz:
  454. SET_PORT_BITS(TLCLK_REG0, 0xfc, 1);
  455. break;
  456. }
  457. } else
  458. SET_PORT_BITS(TLCLK_REG3, 0xf8, val);
  459. spin_unlock_irqrestore(&event_lock, flags);
  460. return strnlen(buf, count);
  461. }
  462. static DEVICE_ATTR(select_amcb1_transmit_clock, (S_IWUSR|S_IWGRP), NULL,
  463. store_select_amcb1_transmit_clock);
  464. static ssize_t store_select_redundant_clock(struct device *d,
  465. struct device_attribute *attr, const char *buf, size_t count)
  466. {
  467. unsigned long tmp;
  468. unsigned char val;
  469. unsigned long flags;
  470. sscanf(buf, "%lX", &tmp);
  471. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  472. val = (unsigned char)tmp;
  473. spin_lock_irqsave(&event_lock, flags);
  474. SET_PORT_BITS(TLCLK_REG1, 0xfe, val);
  475. spin_unlock_irqrestore(&event_lock, flags);
  476. return strnlen(buf, count);
  477. }
  478. static DEVICE_ATTR(select_redundant_clock, (S_IWUSR|S_IWGRP), NULL,
  479. store_select_redundant_clock);
  480. static ssize_t store_select_ref_frequency(struct device *d,
  481. struct device_attribute *attr, const char *buf, size_t count)
  482. {
  483. unsigned long tmp;
  484. unsigned char val;
  485. unsigned long flags;
  486. sscanf(buf, "%lX", &tmp);
  487. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  488. val = (unsigned char)tmp;
  489. spin_lock_irqsave(&event_lock, flags);
  490. SET_PORT_BITS(TLCLK_REG1, 0xfd, val);
  491. spin_unlock_irqrestore(&event_lock, flags);
  492. return strnlen(buf, count);
  493. }
  494. static DEVICE_ATTR(select_ref_frequency, (S_IWUSR|S_IWGRP), NULL,
  495. store_select_ref_frequency);
  496. static ssize_t store_filter_select(struct device *d,
  497. struct device_attribute *attr, const char *buf, size_t count)
  498. {
  499. unsigned long tmp;
  500. unsigned char val;
  501. unsigned long flags;
  502. sscanf(buf, "%lX", &tmp);
  503. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  504. val = (unsigned char)tmp;
  505. spin_lock_irqsave(&event_lock, flags);
  506. SET_PORT_BITS(TLCLK_REG0, 0xfb, val);
  507. spin_unlock_irqrestore(&event_lock, flags);
  508. return strnlen(buf, count);
  509. }
  510. static DEVICE_ATTR(filter_select, (S_IWUSR|S_IWGRP), NULL, store_filter_select);
  511. static ssize_t store_hardware_switching_mode(struct device *d,
  512. struct device_attribute *attr, const char *buf, size_t count)
  513. {
  514. unsigned long tmp;
  515. unsigned char val;
  516. unsigned long flags;
  517. sscanf(buf, "%lX", &tmp);
  518. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  519. val = (unsigned char)tmp;
  520. spin_lock_irqsave(&event_lock, flags);
  521. SET_PORT_BITS(TLCLK_REG0, 0xbf, val);
  522. spin_unlock_irqrestore(&event_lock, flags);
  523. return strnlen(buf, count);
  524. }
  525. static DEVICE_ATTR(hardware_switching_mode, (S_IWUSR|S_IWGRP), NULL,
  526. store_hardware_switching_mode);
  527. static ssize_t store_hardware_switching(struct device *d,
  528. struct device_attribute *attr, const char *buf, size_t count)
  529. {
  530. unsigned long tmp;
  531. unsigned char val;
  532. unsigned long flags;
  533. sscanf(buf, "%lX", &tmp);
  534. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  535. val = (unsigned char)tmp;
  536. spin_lock_irqsave(&event_lock, flags);
  537. SET_PORT_BITS(TLCLK_REG0, 0x7f, val);
  538. spin_unlock_irqrestore(&event_lock, flags);
  539. return strnlen(buf, count);
  540. }
  541. static DEVICE_ATTR(hardware_switching, (S_IWUSR|S_IWGRP), NULL,
  542. store_hardware_switching);
  543. static ssize_t store_refalign (struct device *d,
  544. struct device_attribute *attr, const char *buf, size_t count)
  545. {
  546. unsigned long tmp;
  547. unsigned long flags;
  548. sscanf(buf, "%lX", &tmp);
  549. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  550. spin_lock_irqsave(&event_lock, flags);
  551. SET_PORT_BITS(TLCLK_REG0, 0xf7, 0);
  552. SET_PORT_BITS(TLCLK_REG0, 0xf7, 0x08);
  553. SET_PORT_BITS(TLCLK_REG0, 0xf7, 0);
  554. spin_unlock_irqrestore(&event_lock, flags);
  555. return strnlen(buf, count);
  556. }
  557. static DEVICE_ATTR(refalign, (S_IWUSR|S_IWGRP), NULL, store_refalign);
  558. static ssize_t store_mode_select (struct device *d,
  559. struct device_attribute *attr, const char *buf, size_t count)
  560. {
  561. unsigned long tmp;
  562. unsigned char val;
  563. unsigned long flags;
  564. sscanf(buf, "%lX", &tmp);
  565. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  566. val = (unsigned char)tmp;
  567. spin_lock_irqsave(&event_lock, flags);
  568. SET_PORT_BITS(TLCLK_REG0, 0xcf, val);
  569. spin_unlock_irqrestore(&event_lock, flags);
  570. return strnlen(buf, count);
  571. }
  572. static DEVICE_ATTR(mode_select, (S_IWUSR|S_IWGRP), NULL, store_mode_select);
  573. static ssize_t store_reset (struct device *d,
  574. struct device_attribute *attr, const char *buf, size_t count)
  575. {
  576. unsigned long tmp;
  577. unsigned char val;
  578. unsigned long flags;
  579. sscanf(buf, "%lX", &tmp);
  580. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  581. val = (unsigned char)tmp;
  582. spin_lock_irqsave(&event_lock, flags);
  583. SET_PORT_BITS(TLCLK_REG4, 0xfd, val);
  584. spin_unlock_irqrestore(&event_lock, flags);
  585. return strnlen(buf, count);
  586. }
  587. static DEVICE_ATTR(reset, (S_IWUSR|S_IWGRP), NULL, store_reset);
  588. static struct attribute *tlclk_sysfs_entries[] = {
  589. &dev_attr_current_ref.attr,
  590. &dev_attr_telclock_version.attr,
  591. &dev_attr_alarms.attr,
  592. &dev_attr_received_ref_clk3a.attr,
  593. &dev_attr_received_ref_clk3b.attr,
  594. &dev_attr_enable_clk3a_output.attr,
  595. &dev_attr_enable_clk3b_output.attr,
  596. &dev_attr_enable_clkb1_output.attr,
  597. &dev_attr_enable_clka1_output.attr,
  598. &dev_attr_enable_clkb0_output.attr,
  599. &dev_attr_enable_clka0_output.attr,
  600. &dev_attr_select_amcb1_transmit_clock.attr,
  601. &dev_attr_select_amcb2_transmit_clock.attr,
  602. &dev_attr_select_redundant_clock.attr,
  603. &dev_attr_select_ref_frequency.attr,
  604. &dev_attr_filter_select.attr,
  605. &dev_attr_hardware_switching_mode.attr,
  606. &dev_attr_hardware_switching.attr,
  607. &dev_attr_refalign.attr,
  608. &dev_attr_mode_select.attr,
  609. &dev_attr_reset.attr,
  610. NULL
  611. };
  612. static struct attribute_group tlclk_attribute_group = {
  613. .name = NULL, /* put in device directory */
  614. .attrs = tlclk_sysfs_entries,
  615. };
  616. static struct platform_device *tlclk_device;
  617. static int __init tlclk_init(void)
  618. {
  619. int ret;
  620. ret = register_chrdev(tlclk_major, "telco_clock", &tlclk_fops);
  621. if (ret < 0) {
  622. printk(KERN_ERR "tlclk: can't get major %d.\n", tlclk_major);
  623. return ret;
  624. }
  625. tlclk_major = ret;
  626. alarm_events = kzalloc( sizeof(struct tlclk_alarms), GFP_KERNEL);
  627. if (!alarm_events) {
  628. ret = -ENOMEM;
  629. goto out1;
  630. }
  631. /* Read telecom clock IRQ number (Set by BIOS) */
  632. if (!request_region(TLCLK_BASE, 8, "telco_clock")) {
  633. printk(KERN_ERR "tlclk: request_region 0x%X failed.\n",
  634. TLCLK_BASE);
  635. ret = -EBUSY;
  636. goto out2;
  637. }
  638. telclk_interrupt = (inb(TLCLK_REG7) & 0x0f);
  639. if (0x0F == telclk_interrupt ) { /* not MCPBL0010 ? */
  640. printk(KERN_ERR "telclk_interrupt = 0x%x non-mcpbl0010 hw.\n",
  641. telclk_interrupt);
  642. ret = -ENXIO;
  643. goto out3;
  644. }
  645. init_timer(&switchover_timer);
  646. ret = misc_register(&tlclk_miscdev);
  647. if (ret < 0) {
  648. printk(KERN_ERR "tlclk: misc_register returns %d.\n", ret);
  649. goto out3;
  650. }
  651. tlclk_device = platform_device_register_simple("telco_clock",
  652. -1, NULL, 0);
  653. if (IS_ERR(tlclk_device)) {
  654. printk(KERN_ERR "tlclk: platform_device_register failed.\n");
  655. ret = PTR_ERR(tlclk_device);
  656. goto out4;
  657. }
  658. ret = sysfs_create_group(&tlclk_device->dev.kobj,
  659. &tlclk_attribute_group);
  660. if (ret) {
  661. printk(KERN_ERR "tlclk: failed to create sysfs device attributes.\n");
  662. goto out5;
  663. }
  664. return 0;
  665. out5:
  666. platform_device_unregister(tlclk_device);
  667. out4:
  668. misc_deregister(&tlclk_miscdev);
  669. out3:
  670. release_region(TLCLK_BASE, 8);
  671. out2:
  672. kfree(alarm_events);
  673. out1:
  674. unregister_chrdev(tlclk_major, "telco_clock");
  675. return ret;
  676. }
  677. static void __exit tlclk_cleanup(void)
  678. {
  679. sysfs_remove_group(&tlclk_device->dev.kobj, &tlclk_attribute_group);
  680. platform_device_unregister(tlclk_device);
  681. misc_deregister(&tlclk_miscdev);
  682. unregister_chrdev(tlclk_major, "telco_clock");
  683. release_region(TLCLK_BASE, 8);
  684. del_timer_sync(&switchover_timer);
  685. kfree(alarm_events);
  686. }
  687. static void switchover_timeout(unsigned long data)
  688. {
  689. unsigned long flags = *(unsigned long *) data;
  690. if ((flags & 1)) {
  691. if ((inb(TLCLK_REG1) & 0x08) != (flags & 0x08))
  692. alarm_events->switchover_primary++;
  693. } else {
  694. if ((inb(TLCLK_REG1) & 0x08) != (flags & 0x08))
  695. alarm_events->switchover_secondary++;
  696. }
  697. /* Alarm processing is done, wake up read task */
  698. del_timer(&switchover_timer);
  699. got_event = 1;
  700. wake_up(&wq);
  701. }
  702. static irqreturn_t tlclk_interrupt(int irq, void *dev_id)
  703. {
  704. unsigned long flags;
  705. spin_lock_irqsave(&event_lock, flags);
  706. /* Read and clear interrupt events */
  707. int_events = inb(TLCLK_REG6);
  708. /* Primary_Los changed from 0 to 1 ? */
  709. if (int_events & PRI_LOS_01_MASK) {
  710. if (inb(TLCLK_REG2) & SEC_LOST_MASK)
  711. alarm_events->lost_clocks++;
  712. else
  713. alarm_events->lost_primary_clock++;
  714. }
  715. /* Primary_Los changed from 1 to 0 ? */
  716. if (int_events & PRI_LOS_10_MASK) {
  717. alarm_events->primary_clock_back++;
  718. SET_PORT_BITS(TLCLK_REG1, 0xFE, 1);
  719. }
  720. /* Secondary_Los changed from 0 to 1 ? */
  721. if (int_events & SEC_LOS_01_MASK) {
  722. if (inb(TLCLK_REG2) & PRI_LOST_MASK)
  723. alarm_events->lost_clocks++;
  724. else
  725. alarm_events->lost_secondary_clock++;
  726. }
  727. /* Secondary_Los changed from 1 to 0 ? */
  728. if (int_events & SEC_LOS_10_MASK) {
  729. alarm_events->secondary_clock_back++;
  730. SET_PORT_BITS(TLCLK_REG1, 0xFE, 0);
  731. }
  732. if (int_events & HOLDOVER_10_MASK)
  733. alarm_events->pll_end_holdover++;
  734. if (int_events & UNLOCK_01_MASK)
  735. alarm_events->pll_lost_sync++;
  736. if (int_events & UNLOCK_10_MASK)
  737. alarm_events->pll_sync++;
  738. /* Holdover changed from 0 to 1 ? */
  739. if (int_events & HOLDOVER_01_MASK) {
  740. alarm_events->pll_holdover++;
  741. /* TIMEOUT in ~10ms */
  742. switchover_timer.expires = jiffies + msecs_to_jiffies(10);
  743. tlclk_timer_data = inb(TLCLK_REG1);
  744. switchover_timer.data = (unsigned long) &tlclk_timer_data;
  745. mod_timer(&switchover_timer, switchover_timer.expires);
  746. } else {
  747. got_event = 1;
  748. wake_up(&wq);
  749. }
  750. spin_unlock_irqrestore(&event_lock, flags);
  751. return IRQ_HANDLED;
  752. }
  753. module_init(tlclk_init);
  754. module_exit(tlclk_cleanup);