clk-programmable.c 6.8 KB

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  1. /*
  2. * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. *
  9. */
  10. #include <linux/clk-provider.h>
  11. #include <linux/clkdev.h>
  12. #include <linux/clk/at91_pmc.h>
  13. #include <linux/of.h>
  14. #include <linux/of_address.h>
  15. #include <linux/io.h>
  16. #include <linux/wait.h>
  17. #include <linux/sched.h>
  18. #include "pmc.h"
  19. #define PROG_SOURCE_MAX 5
  20. #define PROG_ID_MAX 7
  21. #define PROG_STATUS_MASK(id) (1 << ((id) + 8))
  22. #define PROG_PRES_MASK 0x7
  23. #define PROG_MAX_RM9200_CSS 3
  24. struct clk_programmable_layout {
  25. u8 pres_shift;
  26. u8 css_mask;
  27. u8 have_slck_mck;
  28. };
  29. struct clk_programmable {
  30. struct clk_hw hw;
  31. struct at91_pmc *pmc;
  32. u8 id;
  33. const struct clk_programmable_layout *layout;
  34. };
  35. #define to_clk_programmable(hw) container_of(hw, struct clk_programmable, hw)
  36. static unsigned long clk_programmable_recalc_rate(struct clk_hw *hw,
  37. unsigned long parent_rate)
  38. {
  39. u32 pres;
  40. struct clk_programmable *prog = to_clk_programmable(hw);
  41. struct at91_pmc *pmc = prog->pmc;
  42. const struct clk_programmable_layout *layout = prog->layout;
  43. pres = (pmc_read(pmc, AT91_PMC_PCKR(prog->id)) >> layout->pres_shift) &
  44. PROG_PRES_MASK;
  45. return parent_rate >> pres;
  46. }
  47. static int clk_programmable_determine_rate(struct clk_hw *hw,
  48. struct clk_rate_request *req)
  49. {
  50. struct clk_hw *parent;
  51. long best_rate = -EINVAL;
  52. unsigned long parent_rate;
  53. unsigned long tmp_rate;
  54. int shift;
  55. int i;
  56. for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
  57. parent = clk_hw_get_parent_by_index(hw, i);
  58. if (!parent)
  59. continue;
  60. parent_rate = clk_hw_get_rate(parent);
  61. for (shift = 0; shift < PROG_PRES_MASK; shift++) {
  62. tmp_rate = parent_rate >> shift;
  63. if (tmp_rate <= req->rate)
  64. break;
  65. }
  66. if (tmp_rate > req->rate)
  67. continue;
  68. if (best_rate < 0 ||
  69. (req->rate - tmp_rate) < (req->rate - best_rate)) {
  70. best_rate = tmp_rate;
  71. req->best_parent_rate = parent_rate;
  72. req->best_parent_hw = parent;
  73. }
  74. if (!best_rate)
  75. break;
  76. }
  77. if (best_rate < 0)
  78. return best_rate;
  79. req->rate = best_rate;
  80. return 0;
  81. }
  82. static int clk_programmable_set_parent(struct clk_hw *hw, u8 index)
  83. {
  84. struct clk_programmable *prog = to_clk_programmable(hw);
  85. const struct clk_programmable_layout *layout = prog->layout;
  86. struct at91_pmc *pmc = prog->pmc;
  87. u32 tmp = pmc_read(pmc, AT91_PMC_PCKR(prog->id)) & ~layout->css_mask;
  88. if (layout->have_slck_mck)
  89. tmp &= AT91_PMC_CSSMCK_MCK;
  90. if (index > layout->css_mask) {
  91. if (index > PROG_MAX_RM9200_CSS && layout->have_slck_mck) {
  92. tmp |= AT91_PMC_CSSMCK_MCK;
  93. return 0;
  94. } else {
  95. return -EINVAL;
  96. }
  97. }
  98. pmc_write(pmc, AT91_PMC_PCKR(prog->id), tmp | index);
  99. return 0;
  100. }
  101. static u8 clk_programmable_get_parent(struct clk_hw *hw)
  102. {
  103. u32 tmp;
  104. u8 ret;
  105. struct clk_programmable *prog = to_clk_programmable(hw);
  106. struct at91_pmc *pmc = prog->pmc;
  107. const struct clk_programmable_layout *layout = prog->layout;
  108. tmp = pmc_read(pmc, AT91_PMC_PCKR(prog->id));
  109. ret = tmp & layout->css_mask;
  110. if (layout->have_slck_mck && (tmp & AT91_PMC_CSSMCK_MCK) && !ret)
  111. ret = PROG_MAX_RM9200_CSS + 1;
  112. return ret;
  113. }
  114. static int clk_programmable_set_rate(struct clk_hw *hw, unsigned long rate,
  115. unsigned long parent_rate)
  116. {
  117. struct clk_programmable *prog = to_clk_programmable(hw);
  118. struct at91_pmc *pmc = prog->pmc;
  119. const struct clk_programmable_layout *layout = prog->layout;
  120. unsigned long div = parent_rate / rate;
  121. int shift = 0;
  122. u32 tmp = pmc_read(pmc, AT91_PMC_PCKR(prog->id)) &
  123. ~(PROG_PRES_MASK << layout->pres_shift);
  124. if (!div)
  125. return -EINVAL;
  126. shift = fls(div) - 1;
  127. if (div != (1<<shift))
  128. return -EINVAL;
  129. if (shift >= PROG_PRES_MASK)
  130. return -EINVAL;
  131. pmc_write(pmc, AT91_PMC_PCKR(prog->id),
  132. tmp | (shift << layout->pres_shift));
  133. return 0;
  134. }
  135. static const struct clk_ops programmable_ops = {
  136. .recalc_rate = clk_programmable_recalc_rate,
  137. .determine_rate = clk_programmable_determine_rate,
  138. .get_parent = clk_programmable_get_parent,
  139. .set_parent = clk_programmable_set_parent,
  140. .set_rate = clk_programmable_set_rate,
  141. };
  142. static struct clk * __init
  143. at91_clk_register_programmable(struct at91_pmc *pmc,
  144. const char *name, const char **parent_names,
  145. u8 num_parents, u8 id,
  146. const struct clk_programmable_layout *layout)
  147. {
  148. struct clk_programmable *prog;
  149. struct clk *clk = NULL;
  150. struct clk_init_data init;
  151. if (id > PROG_ID_MAX)
  152. return ERR_PTR(-EINVAL);
  153. prog = kzalloc(sizeof(*prog), GFP_KERNEL);
  154. if (!prog)
  155. return ERR_PTR(-ENOMEM);
  156. init.name = name;
  157. init.ops = &programmable_ops;
  158. init.parent_names = parent_names;
  159. init.num_parents = num_parents;
  160. init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
  161. prog->id = id;
  162. prog->layout = layout;
  163. prog->hw.init = &init;
  164. prog->pmc = pmc;
  165. clk = clk_register(NULL, &prog->hw);
  166. if (IS_ERR(clk))
  167. kfree(prog);
  168. return clk;
  169. }
  170. static const struct clk_programmable_layout at91rm9200_programmable_layout = {
  171. .pres_shift = 2,
  172. .css_mask = 0x3,
  173. .have_slck_mck = 0,
  174. };
  175. static const struct clk_programmable_layout at91sam9g45_programmable_layout = {
  176. .pres_shift = 2,
  177. .css_mask = 0x3,
  178. .have_slck_mck = 1,
  179. };
  180. static const struct clk_programmable_layout at91sam9x5_programmable_layout = {
  181. .pres_shift = 4,
  182. .css_mask = 0x7,
  183. .have_slck_mck = 0,
  184. };
  185. static void __init
  186. of_at91_clk_prog_setup(struct device_node *np, struct at91_pmc *pmc,
  187. const struct clk_programmable_layout *layout)
  188. {
  189. int num;
  190. u32 id;
  191. struct clk *clk;
  192. int num_parents;
  193. const char *parent_names[PROG_SOURCE_MAX];
  194. const char *name;
  195. struct device_node *progclknp;
  196. num_parents = of_clk_get_parent_count(np);
  197. if (num_parents <= 0 || num_parents > PROG_SOURCE_MAX)
  198. return;
  199. of_clk_parent_fill(np, parent_names, num_parents);
  200. num = of_get_child_count(np);
  201. if (!num || num > (PROG_ID_MAX + 1))
  202. return;
  203. for_each_child_of_node(np, progclknp) {
  204. if (of_property_read_u32(progclknp, "reg", &id))
  205. continue;
  206. if (of_property_read_string(np, "clock-output-names", &name))
  207. name = progclknp->name;
  208. clk = at91_clk_register_programmable(pmc, name,
  209. parent_names, num_parents,
  210. id, layout);
  211. if (IS_ERR(clk))
  212. continue;
  213. of_clk_add_provider(progclknp, of_clk_src_simple_get, clk);
  214. }
  215. }
  216. void __init of_at91rm9200_clk_prog_setup(struct device_node *np,
  217. struct at91_pmc *pmc)
  218. {
  219. of_at91_clk_prog_setup(np, pmc, &at91rm9200_programmable_layout);
  220. }
  221. void __init of_at91sam9g45_clk_prog_setup(struct device_node *np,
  222. struct at91_pmc *pmc)
  223. {
  224. of_at91_clk_prog_setup(np, pmc, &at91sam9g45_programmable_layout);
  225. }
  226. void __init of_at91sam9x5_clk_prog_setup(struct device_node *np,
  227. struct at91_pmc *pmc)
  228. {
  229. of_at91_clk_prog_setup(np, pmc, &at91sam9x5_programmable_layout);
  230. }