clk-div.c 1.4 KB

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  1. /*
  2. * H8/300 divide clock driver
  3. *
  4. * Copyright 2015 Yoshinori Sato <ysato@users.sourceforge.jp>
  5. */
  6. #include <linux/clk-provider.h>
  7. #include <linux/err.h>
  8. #include <linux/of.h>
  9. #include <linux/of_address.h>
  10. static DEFINE_SPINLOCK(clklock);
  11. static void __init h8300_div_clk_setup(struct device_node *node)
  12. {
  13. int num_parents;
  14. struct clk *clk;
  15. const char *clk_name = node->name;
  16. const char *parent_name;
  17. void __iomem *divcr = NULL;
  18. int width;
  19. int offset;
  20. num_parents = of_clk_get_parent_count(node);
  21. if (num_parents < 1) {
  22. pr_err("%s: no parent found", clk_name);
  23. return;
  24. }
  25. divcr = of_iomap(node, 0);
  26. if (divcr == NULL) {
  27. pr_err("%s: failed to map divide register", clk_name);
  28. goto error;
  29. }
  30. offset = (unsigned long)divcr & 3;
  31. offset = (3 - offset) * 8;
  32. divcr = (void *)((unsigned long)divcr & ~3);
  33. parent_name = of_clk_get_parent_name(node, 0);
  34. of_property_read_u32(node, "renesas,width", &width);
  35. clk = clk_register_divider(NULL, clk_name, parent_name,
  36. CLK_SET_RATE_GATE, divcr, offset, width,
  37. CLK_DIVIDER_POWER_OF_TWO, &clklock);
  38. if (!IS_ERR(clk)) {
  39. of_clk_add_provider(node, of_clk_src_simple_get, clk);
  40. return;
  41. }
  42. pr_err("%s: failed to register %s div clock (%ld)\n",
  43. __func__, clk_name, PTR_ERR(clk));
  44. error:
  45. if (divcr)
  46. iounmap(divcr);
  47. }
  48. CLK_OF_DECLARE(h8300_div_clk, "renesas,h8300-div-clock", h8300_div_clk_setup);