clk-mstp.c 7.5 KB

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  1. /*
  2. * R-Car MSTP clocks
  3. *
  4. * Copyright (C) 2013 Ideas On Board SPRL
  5. * Copyright (C) 2015 Glider bvba
  6. *
  7. * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; version 2 of the License.
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/clk-provider.h>
  15. #include <linux/clkdev.h>
  16. #include <linux/clk/shmobile.h>
  17. #include <linux/device.h>
  18. #include <linux/io.h>
  19. #include <linux/of.h>
  20. #include <linux/of_address.h>
  21. #include <linux/pm_clock.h>
  22. #include <linux/pm_domain.h>
  23. #include <linux/spinlock.h>
  24. /*
  25. * MSTP clocks. We can't use standard gate clocks as we need to poll on the
  26. * status register when enabling the clock.
  27. */
  28. #define MSTP_MAX_CLOCKS 32
  29. /**
  30. * struct mstp_clock_group - MSTP gating clocks group
  31. *
  32. * @data: clocks in this group
  33. * @smstpcr: module stop control register
  34. * @mstpsr: module stop status register (optional)
  35. * @lock: protects writes to SMSTPCR
  36. */
  37. struct mstp_clock_group {
  38. struct clk_onecell_data data;
  39. void __iomem *smstpcr;
  40. void __iomem *mstpsr;
  41. spinlock_t lock;
  42. };
  43. /**
  44. * struct mstp_clock - MSTP gating clock
  45. * @hw: handle between common and hardware-specific interfaces
  46. * @bit_index: control bit index
  47. * @group: MSTP clocks group
  48. */
  49. struct mstp_clock {
  50. struct clk_hw hw;
  51. u32 bit_index;
  52. struct mstp_clock_group *group;
  53. };
  54. #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
  55. static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
  56. {
  57. struct mstp_clock *clock = to_mstp_clock(hw);
  58. struct mstp_clock_group *group = clock->group;
  59. u32 bitmask = BIT(clock->bit_index);
  60. unsigned long flags;
  61. unsigned int i;
  62. u32 value;
  63. spin_lock_irqsave(&group->lock, flags);
  64. value = clk_readl(group->smstpcr);
  65. if (enable)
  66. value &= ~bitmask;
  67. else
  68. value |= bitmask;
  69. clk_writel(value, group->smstpcr);
  70. spin_unlock_irqrestore(&group->lock, flags);
  71. if (!enable || !group->mstpsr)
  72. return 0;
  73. for (i = 1000; i > 0; --i) {
  74. if (!(clk_readl(group->mstpsr) & bitmask))
  75. break;
  76. cpu_relax();
  77. }
  78. if (!i) {
  79. pr_err("%s: failed to enable %p[%d]\n", __func__,
  80. group->smstpcr, clock->bit_index);
  81. return -ETIMEDOUT;
  82. }
  83. return 0;
  84. }
  85. static int cpg_mstp_clock_enable(struct clk_hw *hw)
  86. {
  87. return cpg_mstp_clock_endisable(hw, true);
  88. }
  89. static void cpg_mstp_clock_disable(struct clk_hw *hw)
  90. {
  91. cpg_mstp_clock_endisable(hw, false);
  92. }
  93. static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
  94. {
  95. struct mstp_clock *clock = to_mstp_clock(hw);
  96. struct mstp_clock_group *group = clock->group;
  97. u32 value;
  98. if (group->mstpsr)
  99. value = clk_readl(group->mstpsr);
  100. else
  101. value = clk_readl(group->smstpcr);
  102. return !(value & BIT(clock->bit_index));
  103. }
  104. static const struct clk_ops cpg_mstp_clock_ops = {
  105. .enable = cpg_mstp_clock_enable,
  106. .disable = cpg_mstp_clock_disable,
  107. .is_enabled = cpg_mstp_clock_is_enabled,
  108. };
  109. static struct clk * __init
  110. cpg_mstp_clock_register(const char *name, const char *parent_name,
  111. unsigned int index, struct mstp_clock_group *group)
  112. {
  113. struct clk_init_data init;
  114. struct mstp_clock *clock;
  115. struct clk *clk;
  116. clock = kzalloc(sizeof(*clock), GFP_KERNEL);
  117. if (!clock) {
  118. pr_err("%s: failed to allocate MSTP clock.\n", __func__);
  119. return ERR_PTR(-ENOMEM);
  120. }
  121. init.name = name;
  122. init.ops = &cpg_mstp_clock_ops;
  123. init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
  124. init.parent_names = &parent_name;
  125. init.num_parents = 1;
  126. clock->bit_index = index;
  127. clock->group = group;
  128. clock->hw.init = &init;
  129. clk = clk_register(NULL, &clock->hw);
  130. if (IS_ERR(clk))
  131. kfree(clock);
  132. return clk;
  133. }
  134. static void __init cpg_mstp_clocks_init(struct device_node *np)
  135. {
  136. struct mstp_clock_group *group;
  137. const char *idxname;
  138. struct clk **clks;
  139. unsigned int i;
  140. group = kzalloc(sizeof(*group), GFP_KERNEL);
  141. clks = kmalloc(MSTP_MAX_CLOCKS * sizeof(*clks), GFP_KERNEL);
  142. if (group == NULL || clks == NULL) {
  143. kfree(group);
  144. kfree(clks);
  145. pr_err("%s: failed to allocate group\n", __func__);
  146. return;
  147. }
  148. spin_lock_init(&group->lock);
  149. group->data.clks = clks;
  150. group->smstpcr = of_iomap(np, 0);
  151. group->mstpsr = of_iomap(np, 1);
  152. if (group->smstpcr == NULL) {
  153. pr_err("%s: failed to remap SMSTPCR\n", __func__);
  154. kfree(group);
  155. kfree(clks);
  156. return;
  157. }
  158. for (i = 0; i < MSTP_MAX_CLOCKS; ++i)
  159. clks[i] = ERR_PTR(-ENOENT);
  160. if (of_find_property(np, "clock-indices", &i))
  161. idxname = "clock-indices";
  162. else
  163. idxname = "renesas,clock-indices";
  164. for (i = 0; i < MSTP_MAX_CLOCKS; ++i) {
  165. const char *parent_name;
  166. const char *name;
  167. u32 clkidx;
  168. int ret;
  169. /* Skip clocks with no name. */
  170. ret = of_property_read_string_index(np, "clock-output-names",
  171. i, &name);
  172. if (ret < 0 || strlen(name) == 0)
  173. continue;
  174. parent_name = of_clk_get_parent_name(np, i);
  175. ret = of_property_read_u32_index(np, idxname, i, &clkidx);
  176. if (parent_name == NULL || ret < 0)
  177. break;
  178. if (clkidx >= MSTP_MAX_CLOCKS) {
  179. pr_err("%s: invalid clock %s %s index %u\n",
  180. __func__, np->name, name, clkidx);
  181. continue;
  182. }
  183. clks[clkidx] = cpg_mstp_clock_register(name, parent_name,
  184. clkidx, group);
  185. if (!IS_ERR(clks[clkidx])) {
  186. group->data.clk_num = max(group->data.clk_num,
  187. clkidx + 1);
  188. /*
  189. * Register a clkdev to let board code retrieve the
  190. * clock by name and register aliases for non-DT
  191. * devices.
  192. *
  193. * FIXME: Remove this when all devices that require a
  194. * clock will be instantiated from DT.
  195. */
  196. clk_register_clkdev(clks[clkidx], name, NULL);
  197. } else {
  198. pr_err("%s: failed to register %s %s clock (%ld)\n",
  199. __func__, np->name, name, PTR_ERR(clks[clkidx]));
  200. }
  201. }
  202. of_clk_add_provider(np, of_clk_src_onecell_get, &group->data);
  203. }
  204. CLK_OF_DECLARE(cpg_mstp_clks, "renesas,cpg-mstp-clocks", cpg_mstp_clocks_init);
  205. #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
  206. int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev)
  207. {
  208. struct device_node *np = dev->of_node;
  209. struct of_phandle_args clkspec;
  210. struct clk *clk;
  211. int i = 0;
  212. int error;
  213. while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
  214. &clkspec)) {
  215. if (of_device_is_compatible(clkspec.np,
  216. "renesas,cpg-mstp-clocks"))
  217. goto found;
  218. /* BSC on r8a73a4/sh73a0 uses zb_clk instead of an mstp clock */
  219. if (!strcmp(clkspec.np->name, "zb_clk"))
  220. goto found;
  221. of_node_put(clkspec.np);
  222. i++;
  223. }
  224. return 0;
  225. found:
  226. clk = of_clk_get_from_provider(&clkspec);
  227. of_node_put(clkspec.np);
  228. if (IS_ERR(clk))
  229. return PTR_ERR(clk);
  230. error = pm_clk_create(dev);
  231. if (error) {
  232. dev_err(dev, "pm_clk_create failed %d\n", error);
  233. goto fail_put;
  234. }
  235. error = pm_clk_add_clk(dev, clk);
  236. if (error) {
  237. dev_err(dev, "pm_clk_add_clk %pC failed %d\n", clk, error);
  238. goto fail_destroy;
  239. }
  240. return 0;
  241. fail_destroy:
  242. pm_clk_destroy(dev);
  243. fail_put:
  244. clk_put(clk);
  245. return error;
  246. }
  247. void cpg_mstp_detach_dev(struct generic_pm_domain *domain, struct device *dev)
  248. {
  249. if (!list_empty(&dev->power.subsys_data->clock_list))
  250. pm_clk_destroy(dev);
  251. }
  252. void __init cpg_mstp_add_clk_domain(struct device_node *np)
  253. {
  254. struct generic_pm_domain *pd;
  255. u32 ncells;
  256. if (of_property_read_u32(np, "#power-domain-cells", &ncells)) {
  257. pr_warn("%s lacks #power-domain-cells\n", np->full_name);
  258. return;
  259. }
  260. pd = kzalloc(sizeof(*pd), GFP_KERNEL);
  261. if (!pd)
  262. return;
  263. pd->name = np->name;
  264. pd->flags = GENPD_FLAG_PM_CLK;
  265. pm_genpd_init(pd, &simple_qos_governor, false);
  266. pd->attach_dev = cpg_mstp_attach_dev;
  267. pd->detach_dev = cpg_mstp_detach_dev;
  268. of_genpd_add_provider_simple(np, pd);
  269. }
  270. #endif /* !CONFIG_PM_GENERIC_DOMAINS_OF */