h8300_tpu.c 4.3 KB

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  1. /*
  2. * H8/300 TPU Driver
  3. *
  4. * Copyright 2015 Yoshinori Sato <ysato@users.sourcefoge.jp>
  5. *
  6. */
  7. #include <linux/errno.h>
  8. #include <linux/sched.h>
  9. #include <linux/kernel.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/init.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/slab.h>
  14. #include <linux/clocksource.h>
  15. #include <linux/module.h>
  16. #include <linux/clk.h>
  17. #include <linux/io.h>
  18. #include <linux/of.h>
  19. #include <asm/irq.h>
  20. #define TCR 0
  21. #define TMDR 1
  22. #define TIOR 2
  23. #define TER 4
  24. #define TSR 5
  25. #define TCNT 6
  26. #define TGRA 8
  27. #define TGRB 10
  28. #define TGRC 12
  29. #define TGRD 14
  30. struct tpu_priv {
  31. struct platform_device *pdev;
  32. struct clocksource cs;
  33. struct clk *clk;
  34. unsigned long mapbase1;
  35. unsigned long mapbase2;
  36. raw_spinlock_t lock;
  37. unsigned int cs_enabled;
  38. };
  39. static inline unsigned long read_tcnt32(struct tpu_priv *p)
  40. {
  41. unsigned long tcnt;
  42. tcnt = ctrl_inw(p->mapbase1 + TCNT) << 16;
  43. tcnt |= ctrl_inw(p->mapbase2 + TCNT);
  44. return tcnt;
  45. }
  46. static int tpu_get_counter(struct tpu_priv *p, unsigned long long *val)
  47. {
  48. unsigned long v1, v2, v3;
  49. int o1, o2;
  50. o1 = ctrl_inb(p->mapbase1 + TSR) & 0x10;
  51. /* Make sure the timer value is stable. Stolen from acpi_pm.c */
  52. do {
  53. o2 = o1;
  54. v1 = read_tcnt32(p);
  55. v2 = read_tcnt32(p);
  56. v3 = read_tcnt32(p);
  57. o1 = ctrl_inb(p->mapbase1 + TSR) & 0x10;
  58. } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
  59. || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
  60. *val = v2;
  61. return o1;
  62. }
  63. static inline struct tpu_priv *cs_to_priv(struct clocksource *cs)
  64. {
  65. return container_of(cs, struct tpu_priv, cs);
  66. }
  67. static cycle_t tpu_clocksource_read(struct clocksource *cs)
  68. {
  69. struct tpu_priv *p = cs_to_priv(cs);
  70. unsigned long flags;
  71. unsigned long long value;
  72. raw_spin_lock_irqsave(&p->lock, flags);
  73. if (tpu_get_counter(p, &value))
  74. value += 0x100000000;
  75. raw_spin_unlock_irqrestore(&p->lock, flags);
  76. return value;
  77. }
  78. static int tpu_clocksource_enable(struct clocksource *cs)
  79. {
  80. struct tpu_priv *p = cs_to_priv(cs);
  81. WARN_ON(p->cs_enabled);
  82. ctrl_outw(0, p->mapbase1 + TCNT);
  83. ctrl_outw(0, p->mapbase2 + TCNT);
  84. ctrl_outb(0x0f, p->mapbase1 + TCR);
  85. ctrl_outb(0x03, p->mapbase2 + TCR);
  86. p->cs_enabled = true;
  87. return 0;
  88. }
  89. static void tpu_clocksource_disable(struct clocksource *cs)
  90. {
  91. struct tpu_priv *p = cs_to_priv(cs);
  92. WARN_ON(!p->cs_enabled);
  93. ctrl_outb(0, p->mapbase1 + TCR);
  94. ctrl_outb(0, p->mapbase2 + TCR);
  95. p->cs_enabled = false;
  96. }
  97. #define CH_L 0
  98. #define CH_H 1
  99. static int __init tpu_setup(struct tpu_priv *p, struct platform_device *pdev)
  100. {
  101. struct resource *res[2];
  102. p->pdev = pdev;
  103. res[CH_L] = platform_get_resource(p->pdev, IORESOURCE_MEM, CH_L);
  104. res[CH_H] = platform_get_resource(p->pdev, IORESOURCE_MEM, CH_H);
  105. if (!res[CH_L] || !res[CH_H]) {
  106. dev_err(&p->pdev->dev, "failed to get I/O memory\n");
  107. return -ENXIO;
  108. }
  109. p->clk = clk_get(&p->pdev->dev, "fck");
  110. if (IS_ERR(p->clk)) {
  111. dev_err(&p->pdev->dev, "can't get clk\n");
  112. return PTR_ERR(p->clk);
  113. }
  114. p->mapbase1 = res[CH_L]->start;
  115. p->mapbase2 = res[CH_H]->start;
  116. p->cs.name = pdev->name;
  117. p->cs.rating = 200;
  118. p->cs.read = tpu_clocksource_read;
  119. p->cs.enable = tpu_clocksource_enable;
  120. p->cs.disable = tpu_clocksource_disable;
  121. p->cs.mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
  122. p->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
  123. clocksource_register_hz(&p->cs, clk_get_rate(p->clk) / 64);
  124. platform_set_drvdata(pdev, p);
  125. return 0;
  126. }
  127. static int tpu_probe(struct platform_device *pdev)
  128. {
  129. struct tpu_priv *p = platform_get_drvdata(pdev);
  130. if (p) {
  131. dev_info(&pdev->dev, "kept as earlytimer\n");
  132. return 0;
  133. }
  134. p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
  135. if (!p)
  136. return -ENOMEM;
  137. return tpu_setup(p, pdev);
  138. }
  139. static int tpu_remove(struct platform_device *pdev)
  140. {
  141. return -EBUSY;
  142. }
  143. static const struct of_device_id tpu_of_table[] = {
  144. { .compatible = "renesas,tpu" },
  145. { }
  146. };
  147. static struct platform_driver tpu_driver = {
  148. .probe = tpu_probe,
  149. .remove = tpu_remove,
  150. .driver = {
  151. .name = "h8s-tpu",
  152. .of_match_table = of_match_ptr(tpu_of_table),
  153. }
  154. };
  155. static int __init tpu_init(void)
  156. {
  157. return platform_driver_register(&tpu_driver);
  158. }
  159. static void __exit tpu_exit(void)
  160. {
  161. platform_driver_unregister(&tpu_driver);
  162. }
  163. subsys_initcall(tpu_init);
  164. module_exit(tpu_exit);
  165. MODULE_AUTHOR("Yoshinori Sato");
  166. MODULE_DESCRIPTION("H8S Timer Pulse Unit Driver");
  167. MODULE_LICENSE("GPL v2");