exynos4_bus.c 26 KB

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  1. /* drivers/devfreq/exynos4210_memorybus.c
  2. *
  3. * Copyright (c) 2011 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com/
  5. * MyungJoo Ham <myungjoo.ham@samsung.com>
  6. *
  7. * EXYNOS4 - Memory/Bus clock frequency scaling support in DEVFREQ framework
  8. * This version supports EXYNOS4210 only. This changes bus frequencies
  9. * and vddint voltages. Exynos4412/4212 should be able to be supported
  10. * with minor modifications.
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License version 2 as
  14. * published by the Free Software Foundation.
  15. *
  16. */
  17. #include <linux/io.h>
  18. #include <linux/slab.h>
  19. #include <linux/mutex.h>
  20. #include <linux/suspend.h>
  21. #include <linux/pm_opp.h>
  22. #include <linux/devfreq.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/regulator/consumer.h>
  25. #include <linux/module.h>
  26. #include <mach/map.h>
  27. #include "exynos_ppmu.h"
  28. #include "exynos4_bus.h"
  29. #define MAX_SAFEVOLT 1200000 /* 1.2V */
  30. enum exynos4_busf_type {
  31. TYPE_BUSF_EXYNOS4210,
  32. TYPE_BUSF_EXYNOS4x12,
  33. };
  34. /* Assume that the bus is saturated if the utilization is 40% */
  35. #define BUS_SATURATION_RATIO 40
  36. enum busclk_level_idx {
  37. LV_0 = 0,
  38. LV_1,
  39. LV_2,
  40. LV_3,
  41. LV_4,
  42. _LV_END
  43. };
  44. enum exynos_ppmu_idx {
  45. PPMU_DMC0,
  46. PPMU_DMC1,
  47. PPMU_END,
  48. };
  49. #define EX4210_LV_MAX LV_2
  50. #define EX4x12_LV_MAX LV_4
  51. #define EX4210_LV_NUM (LV_2 + 1)
  52. #define EX4x12_LV_NUM (LV_4 + 1)
  53. /**
  54. * struct busfreq_opp_info - opp information for bus
  55. * @rate: Frequency in hertz
  56. * @volt: Voltage in microvolts corresponding to this OPP
  57. */
  58. struct busfreq_opp_info {
  59. unsigned long rate;
  60. unsigned long volt;
  61. };
  62. struct busfreq_data {
  63. enum exynos4_busf_type type;
  64. struct device *dev;
  65. struct devfreq *devfreq;
  66. bool disabled;
  67. struct regulator *vdd_int;
  68. struct regulator *vdd_mif; /* Exynos4412/4212 only */
  69. struct busfreq_opp_info curr_oppinfo;
  70. struct busfreq_ppmu_data ppmu_data;
  71. struct notifier_block pm_notifier;
  72. struct mutex lock;
  73. /* Dividers calculated at boot/probe-time */
  74. unsigned int dmc_divtable[_LV_END]; /* DMC0 */
  75. unsigned int top_divtable[_LV_END];
  76. };
  77. /* 4210 controls clock of mif and voltage of int */
  78. static struct bus_opp_table exynos4210_busclk_table[] = {
  79. {LV_0, 400000, 1150000},
  80. {LV_1, 267000, 1050000},
  81. {LV_2, 133000, 1025000},
  82. {0, 0, 0},
  83. };
  84. /*
  85. * MIF is the main control knob clock for Exynos4x12 MIF/INT
  86. * clock and voltage of both mif/int are controlled.
  87. */
  88. static struct bus_opp_table exynos4x12_mifclk_table[] = {
  89. {LV_0, 400000, 1100000},
  90. {LV_1, 267000, 1000000},
  91. {LV_2, 160000, 950000},
  92. {LV_3, 133000, 950000},
  93. {LV_4, 100000, 950000},
  94. {0, 0, 0},
  95. };
  96. /*
  97. * INT is not the control knob of 4x12. LV_x is not meant to represent
  98. * the current performance. (MIF does)
  99. */
  100. static struct bus_opp_table exynos4x12_intclk_table[] = {
  101. {LV_0, 200000, 1000000},
  102. {LV_1, 160000, 950000},
  103. {LV_2, 133000, 925000},
  104. {LV_3, 100000, 900000},
  105. {0, 0, 0},
  106. };
  107. /* TODO: asv volt definitions are "__initdata"? */
  108. /* Some chips have different operating voltages */
  109. static unsigned int exynos4210_asv_volt[][EX4210_LV_NUM] = {
  110. {1150000, 1050000, 1050000},
  111. {1125000, 1025000, 1025000},
  112. {1100000, 1000000, 1000000},
  113. {1075000, 975000, 975000},
  114. {1050000, 950000, 950000},
  115. };
  116. static unsigned int exynos4x12_mif_step_50[][EX4x12_LV_NUM] = {
  117. /* 400 267 160 133 100 */
  118. {1050000, 950000, 900000, 900000, 900000}, /* ASV0 */
  119. {1050000, 950000, 900000, 900000, 900000}, /* ASV1 */
  120. {1050000, 950000, 900000, 900000, 900000}, /* ASV2 */
  121. {1050000, 900000, 900000, 900000, 900000}, /* ASV3 */
  122. {1050000, 900000, 900000, 900000, 850000}, /* ASV4 */
  123. {1050000, 900000, 900000, 850000, 850000}, /* ASV5 */
  124. {1050000, 900000, 850000, 850000, 850000}, /* ASV6 */
  125. {1050000, 900000, 850000, 850000, 850000}, /* ASV7 */
  126. {1050000, 900000, 850000, 850000, 850000}, /* ASV8 */
  127. };
  128. static unsigned int exynos4x12_int_volt[][EX4x12_LV_NUM] = {
  129. /* 200 160 133 100 */
  130. {1000000, 950000, 925000, 900000}, /* ASV0 */
  131. {975000, 925000, 925000, 900000}, /* ASV1 */
  132. {950000, 925000, 900000, 875000}, /* ASV2 */
  133. {950000, 900000, 900000, 875000}, /* ASV3 */
  134. {925000, 875000, 875000, 875000}, /* ASV4 */
  135. {900000, 850000, 850000, 850000}, /* ASV5 */
  136. {900000, 850000, 850000, 850000}, /* ASV6 */
  137. {900000, 850000, 850000, 850000}, /* ASV7 */
  138. {900000, 850000, 850000, 850000}, /* ASV8 */
  139. };
  140. /*** Clock Divider Data for Exynos4210 ***/
  141. static unsigned int exynos4210_clkdiv_dmc0[][8] = {
  142. /*
  143. * Clock divider value for following
  144. * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
  145. * DIVDMCP, DIVCOPY2, DIVCORE_TIMERS }
  146. */
  147. /* DMC L0: 400MHz */
  148. { 3, 1, 1, 1, 1, 1, 3, 1 },
  149. /* DMC L1: 266.7MHz */
  150. { 4, 1, 1, 2, 1, 1, 3, 1 },
  151. /* DMC L2: 133MHz */
  152. { 5, 1, 1, 5, 1, 1, 3, 1 },
  153. };
  154. static unsigned int exynos4210_clkdiv_top[][5] = {
  155. /*
  156. * Clock divider value for following
  157. * { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND }
  158. */
  159. /* ACLK200 L0: 200MHz */
  160. { 3, 7, 4, 5, 1 },
  161. /* ACLK200 L1: 160MHz */
  162. { 4, 7, 5, 6, 1 },
  163. /* ACLK200 L2: 133MHz */
  164. { 5, 7, 7, 7, 1 },
  165. };
  166. static unsigned int exynos4210_clkdiv_lr_bus[][2] = {
  167. /*
  168. * Clock divider value for following
  169. * { DIVGDL/R, DIVGPL/R }
  170. */
  171. /* ACLK_GDL/R L1: 200MHz */
  172. { 3, 1 },
  173. /* ACLK_GDL/R L2: 160MHz */
  174. { 4, 1 },
  175. /* ACLK_GDL/R L3: 133MHz */
  176. { 5, 1 },
  177. };
  178. /*** Clock Divider Data for Exynos4212/4412 ***/
  179. static unsigned int exynos4x12_clkdiv_dmc0[][6] = {
  180. /*
  181. * Clock divider value for following
  182. * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
  183. * DIVDMCP}
  184. */
  185. /* DMC L0: 400MHz */
  186. {3, 1, 1, 1, 1, 1},
  187. /* DMC L1: 266.7MHz */
  188. {4, 1, 1, 2, 1, 1},
  189. /* DMC L2: 160MHz */
  190. {5, 1, 1, 4, 1, 1},
  191. /* DMC L3: 133MHz */
  192. {5, 1, 1, 5, 1, 1},
  193. /* DMC L4: 100MHz */
  194. {7, 1, 1, 7, 1, 1},
  195. };
  196. static unsigned int exynos4x12_clkdiv_dmc1[][6] = {
  197. /*
  198. * Clock divider value for following
  199. * { G2DACP, DIVC2C, DIVC2C_ACLK }
  200. */
  201. /* DMC L0: 400MHz */
  202. {3, 1, 1},
  203. /* DMC L1: 266.7MHz */
  204. {4, 2, 1},
  205. /* DMC L2: 160MHz */
  206. {5, 4, 1},
  207. /* DMC L3: 133MHz */
  208. {5, 5, 1},
  209. /* DMC L4: 100MHz */
  210. {7, 7, 1},
  211. };
  212. static unsigned int exynos4x12_clkdiv_top[][5] = {
  213. /*
  214. * Clock divider value for following
  215. * { DIVACLK266_GPS, DIVACLK100, DIVACLK160,
  216. DIVACLK133, DIVONENAND }
  217. */
  218. /* ACLK_GDL/R L0: 200MHz */
  219. {2, 7, 4, 5, 1},
  220. /* ACLK_GDL/R L1: 200MHz */
  221. {2, 7, 4, 5, 1},
  222. /* ACLK_GDL/R L2: 160MHz */
  223. {4, 7, 5, 7, 1},
  224. /* ACLK_GDL/R L3: 133MHz */
  225. {4, 7, 5, 7, 1},
  226. /* ACLK_GDL/R L4: 100MHz */
  227. {7, 7, 7, 7, 1},
  228. };
  229. static unsigned int exynos4x12_clkdiv_lr_bus[][2] = {
  230. /*
  231. * Clock divider value for following
  232. * { DIVGDL/R, DIVGPL/R }
  233. */
  234. /* ACLK_GDL/R L0: 200MHz */
  235. {3, 1},
  236. /* ACLK_GDL/R L1: 200MHz */
  237. {3, 1},
  238. /* ACLK_GDL/R L2: 160MHz */
  239. {4, 1},
  240. /* ACLK_GDL/R L3: 133MHz */
  241. {5, 1},
  242. /* ACLK_GDL/R L4: 100MHz */
  243. {7, 1},
  244. };
  245. static unsigned int exynos4x12_clkdiv_sclkip[][3] = {
  246. /*
  247. * Clock divider value for following
  248. * { DIVMFC, DIVJPEG, DIVFIMC0~3}
  249. */
  250. /* SCLK_MFC: 200MHz */
  251. {3, 3, 4},
  252. /* SCLK_MFC: 200MHz */
  253. {3, 3, 4},
  254. /* SCLK_MFC: 160MHz */
  255. {4, 4, 5},
  256. /* SCLK_MFC: 133MHz */
  257. {5, 5, 5},
  258. /* SCLK_MFC: 100MHz */
  259. {7, 7, 7},
  260. };
  261. static int exynos4210_set_busclk(struct busfreq_data *data,
  262. struct busfreq_opp_info *oppi)
  263. {
  264. unsigned int index;
  265. unsigned int tmp;
  266. for (index = LV_0; index < EX4210_LV_NUM; index++)
  267. if (oppi->rate == exynos4210_busclk_table[index].clk)
  268. break;
  269. if (index == EX4210_LV_NUM)
  270. return -EINVAL;
  271. /* Change Divider - DMC0 */
  272. tmp = data->dmc_divtable[index];
  273. __raw_writel(tmp, EXYNOS4_CLKDIV_DMC0);
  274. do {
  275. tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0);
  276. } while (tmp & 0x11111111);
  277. /* Change Divider - TOP */
  278. tmp = data->top_divtable[index];
  279. __raw_writel(tmp, EXYNOS4_CLKDIV_TOP);
  280. do {
  281. tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_TOP);
  282. } while (tmp & 0x11111);
  283. /* Change Divider - LEFTBUS */
  284. tmp = __raw_readl(EXYNOS4_CLKDIV_LEFTBUS);
  285. tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
  286. tmp |= ((exynos4210_clkdiv_lr_bus[index][0] <<
  287. EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
  288. (exynos4210_clkdiv_lr_bus[index][1] <<
  289. EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
  290. __raw_writel(tmp, EXYNOS4_CLKDIV_LEFTBUS);
  291. do {
  292. tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_LEFTBUS);
  293. } while (tmp & 0x11);
  294. /* Change Divider - RIGHTBUS */
  295. tmp = __raw_readl(EXYNOS4_CLKDIV_RIGHTBUS);
  296. tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
  297. tmp |= ((exynos4210_clkdiv_lr_bus[index][0] <<
  298. EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
  299. (exynos4210_clkdiv_lr_bus[index][1] <<
  300. EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
  301. __raw_writel(tmp, EXYNOS4_CLKDIV_RIGHTBUS);
  302. do {
  303. tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_RIGHTBUS);
  304. } while (tmp & 0x11);
  305. return 0;
  306. }
  307. static int exynos4x12_set_busclk(struct busfreq_data *data,
  308. struct busfreq_opp_info *oppi)
  309. {
  310. unsigned int index;
  311. unsigned int tmp;
  312. for (index = LV_0; index < EX4x12_LV_NUM; index++)
  313. if (oppi->rate == exynos4x12_mifclk_table[index].clk)
  314. break;
  315. if (index == EX4x12_LV_NUM)
  316. return -EINVAL;
  317. /* Change Divider - DMC0 */
  318. tmp = data->dmc_divtable[index];
  319. __raw_writel(tmp, EXYNOS4_CLKDIV_DMC0);
  320. do {
  321. tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0);
  322. } while (tmp & 0x11111111);
  323. /* Change Divider - DMC1 */
  324. tmp = __raw_readl(EXYNOS4_CLKDIV_DMC1);
  325. tmp &= ~(EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK |
  326. EXYNOS4_CLKDIV_DMC1_C2C_MASK |
  327. EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK);
  328. tmp |= ((exynos4x12_clkdiv_dmc1[index][0] <<
  329. EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT) |
  330. (exynos4x12_clkdiv_dmc1[index][1] <<
  331. EXYNOS4_CLKDIV_DMC1_C2C_SHIFT) |
  332. (exynos4x12_clkdiv_dmc1[index][2] <<
  333. EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT));
  334. __raw_writel(tmp, EXYNOS4_CLKDIV_DMC1);
  335. do {
  336. tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC1);
  337. } while (tmp & 0x111111);
  338. /* Change Divider - TOP */
  339. tmp = __raw_readl(EXYNOS4_CLKDIV_TOP);
  340. tmp &= ~(EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK |
  341. EXYNOS4_CLKDIV_TOP_ACLK100_MASK |
  342. EXYNOS4_CLKDIV_TOP_ACLK160_MASK |
  343. EXYNOS4_CLKDIV_TOP_ACLK133_MASK |
  344. EXYNOS4_CLKDIV_TOP_ONENAND_MASK);
  345. tmp |= ((exynos4x12_clkdiv_top[index][0] <<
  346. EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT) |
  347. (exynos4x12_clkdiv_top[index][1] <<
  348. EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) |
  349. (exynos4x12_clkdiv_top[index][2] <<
  350. EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) |
  351. (exynos4x12_clkdiv_top[index][3] <<
  352. EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) |
  353. (exynos4x12_clkdiv_top[index][4] <<
  354. EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT));
  355. __raw_writel(tmp, EXYNOS4_CLKDIV_TOP);
  356. do {
  357. tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_TOP);
  358. } while (tmp & 0x11111);
  359. /* Change Divider - LEFTBUS */
  360. tmp = __raw_readl(EXYNOS4_CLKDIV_LEFTBUS);
  361. tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
  362. tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] <<
  363. EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
  364. (exynos4x12_clkdiv_lr_bus[index][1] <<
  365. EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
  366. __raw_writel(tmp, EXYNOS4_CLKDIV_LEFTBUS);
  367. do {
  368. tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_LEFTBUS);
  369. } while (tmp & 0x11);
  370. /* Change Divider - RIGHTBUS */
  371. tmp = __raw_readl(EXYNOS4_CLKDIV_RIGHTBUS);
  372. tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
  373. tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] <<
  374. EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
  375. (exynos4x12_clkdiv_lr_bus[index][1] <<
  376. EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
  377. __raw_writel(tmp, EXYNOS4_CLKDIV_RIGHTBUS);
  378. do {
  379. tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_RIGHTBUS);
  380. } while (tmp & 0x11);
  381. /* Change Divider - MFC */
  382. tmp = __raw_readl(EXYNOS4_CLKDIV_MFC);
  383. tmp &= ~(EXYNOS4_CLKDIV_MFC_MASK);
  384. tmp |= ((exynos4x12_clkdiv_sclkip[index][0] <<
  385. EXYNOS4_CLKDIV_MFC_SHIFT));
  386. __raw_writel(tmp, EXYNOS4_CLKDIV_MFC);
  387. do {
  388. tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_MFC);
  389. } while (tmp & 0x1);
  390. /* Change Divider - JPEG */
  391. tmp = __raw_readl(EXYNOS4_CLKDIV_CAM1);
  392. tmp &= ~(EXYNOS4_CLKDIV_CAM1_JPEG_MASK);
  393. tmp |= ((exynos4x12_clkdiv_sclkip[index][1] <<
  394. EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT));
  395. __raw_writel(tmp, EXYNOS4_CLKDIV_CAM1);
  396. do {
  397. tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_CAM1);
  398. } while (tmp & 0x1);
  399. /* Change Divider - FIMC0~3 */
  400. tmp = __raw_readl(EXYNOS4_CLKDIV_CAM);
  401. tmp &= ~(EXYNOS4_CLKDIV_CAM_FIMC0_MASK | EXYNOS4_CLKDIV_CAM_FIMC1_MASK |
  402. EXYNOS4_CLKDIV_CAM_FIMC2_MASK | EXYNOS4_CLKDIV_CAM_FIMC3_MASK);
  403. tmp |= ((exynos4x12_clkdiv_sclkip[index][2] <<
  404. EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT) |
  405. (exynos4x12_clkdiv_sclkip[index][2] <<
  406. EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT) |
  407. (exynos4x12_clkdiv_sclkip[index][2] <<
  408. EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT) |
  409. (exynos4x12_clkdiv_sclkip[index][2] <<
  410. EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT));
  411. __raw_writel(tmp, EXYNOS4_CLKDIV_CAM);
  412. do {
  413. tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_CAM1);
  414. } while (tmp & 0x1111);
  415. return 0;
  416. }
  417. static int exynos4x12_get_intspec(unsigned long mifclk)
  418. {
  419. int i = 0;
  420. while (exynos4x12_intclk_table[i].clk) {
  421. if (exynos4x12_intclk_table[i].clk <= mifclk)
  422. return i;
  423. i++;
  424. }
  425. return -EINVAL;
  426. }
  427. static int exynos4_bus_setvolt(struct busfreq_data *data,
  428. struct busfreq_opp_info *oppi,
  429. struct busfreq_opp_info *oldoppi)
  430. {
  431. int err = 0, tmp;
  432. unsigned long volt = oppi->volt;
  433. switch (data->type) {
  434. case TYPE_BUSF_EXYNOS4210:
  435. /* OPP represents DMC clock + INT voltage */
  436. err = regulator_set_voltage(data->vdd_int, volt,
  437. MAX_SAFEVOLT);
  438. break;
  439. case TYPE_BUSF_EXYNOS4x12:
  440. /* OPP represents MIF clock + MIF voltage */
  441. err = regulator_set_voltage(data->vdd_mif, volt,
  442. MAX_SAFEVOLT);
  443. if (err)
  444. break;
  445. tmp = exynos4x12_get_intspec(oppi->rate);
  446. if (tmp < 0) {
  447. err = tmp;
  448. regulator_set_voltage(data->vdd_mif,
  449. oldoppi->volt,
  450. MAX_SAFEVOLT);
  451. break;
  452. }
  453. err = regulator_set_voltage(data->vdd_int,
  454. exynos4x12_intclk_table[tmp].volt,
  455. MAX_SAFEVOLT);
  456. /* Try to recover */
  457. if (err)
  458. regulator_set_voltage(data->vdd_mif,
  459. oldoppi->volt,
  460. MAX_SAFEVOLT);
  461. break;
  462. default:
  463. err = -EINVAL;
  464. }
  465. return err;
  466. }
  467. static int exynos4_bus_target(struct device *dev, unsigned long *_freq,
  468. u32 flags)
  469. {
  470. int err = 0;
  471. struct platform_device *pdev = container_of(dev, struct platform_device,
  472. dev);
  473. struct busfreq_data *data = platform_get_drvdata(pdev);
  474. struct dev_pm_opp *opp;
  475. unsigned long freq;
  476. unsigned long old_freq = data->curr_oppinfo.rate;
  477. struct busfreq_opp_info new_oppinfo;
  478. rcu_read_lock();
  479. opp = devfreq_recommended_opp(dev, _freq, flags);
  480. if (IS_ERR(opp)) {
  481. rcu_read_unlock();
  482. return PTR_ERR(opp);
  483. }
  484. new_oppinfo.rate = dev_pm_opp_get_freq(opp);
  485. new_oppinfo.volt = dev_pm_opp_get_voltage(opp);
  486. rcu_read_unlock();
  487. freq = new_oppinfo.rate;
  488. if (old_freq == freq)
  489. return 0;
  490. dev_dbg(dev, "targeting %lukHz %luuV\n", freq, new_oppinfo.volt);
  491. mutex_lock(&data->lock);
  492. if (data->disabled)
  493. goto out;
  494. if (old_freq < freq)
  495. err = exynos4_bus_setvolt(data, &new_oppinfo,
  496. &data->curr_oppinfo);
  497. if (err)
  498. goto out;
  499. if (old_freq != freq) {
  500. switch (data->type) {
  501. case TYPE_BUSF_EXYNOS4210:
  502. err = exynos4210_set_busclk(data, &new_oppinfo);
  503. break;
  504. case TYPE_BUSF_EXYNOS4x12:
  505. err = exynos4x12_set_busclk(data, &new_oppinfo);
  506. break;
  507. default:
  508. err = -EINVAL;
  509. }
  510. }
  511. if (err)
  512. goto out;
  513. if (old_freq > freq)
  514. err = exynos4_bus_setvolt(data, &new_oppinfo,
  515. &data->curr_oppinfo);
  516. if (err)
  517. goto out;
  518. data->curr_oppinfo = new_oppinfo;
  519. out:
  520. mutex_unlock(&data->lock);
  521. return err;
  522. }
  523. static int exynos4_bus_get_dev_status(struct device *dev,
  524. struct devfreq_dev_status *stat)
  525. {
  526. struct busfreq_data *data = dev_get_drvdata(dev);
  527. struct busfreq_ppmu_data *ppmu_data = &data->ppmu_data;
  528. int busier;
  529. exynos_read_ppmu(ppmu_data);
  530. busier = exynos_get_busier_ppmu(ppmu_data);
  531. stat->current_frequency = data->curr_oppinfo.rate;
  532. /* Number of cycles spent on memory access */
  533. stat->busy_time = ppmu_data->ppmu[busier].count[PPMU_PMNCNT3];
  534. stat->busy_time *= 100 / BUS_SATURATION_RATIO;
  535. stat->total_time = ppmu_data->ppmu[busier].ccnt;
  536. /* If the counters have overflown, retry */
  537. if (ppmu_data->ppmu[busier].ccnt_overflow ||
  538. ppmu_data->ppmu[busier].count_overflow[0])
  539. return -EAGAIN;
  540. return 0;
  541. }
  542. static struct devfreq_dev_profile exynos4_devfreq_profile = {
  543. .initial_freq = 400000,
  544. .polling_ms = 50,
  545. .target = exynos4_bus_target,
  546. .get_dev_status = exynos4_bus_get_dev_status,
  547. };
  548. static int exynos4210_init_tables(struct busfreq_data *data)
  549. {
  550. u32 tmp;
  551. int mgrp;
  552. int i, err = 0;
  553. tmp = __raw_readl(EXYNOS4_CLKDIV_DMC0);
  554. for (i = LV_0; i < EX4210_LV_NUM; i++) {
  555. tmp &= ~(EXYNOS4_CLKDIV_DMC0_ACP_MASK |
  556. EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK |
  557. EXYNOS4_CLKDIV_DMC0_DPHY_MASK |
  558. EXYNOS4_CLKDIV_DMC0_DMC_MASK |
  559. EXYNOS4_CLKDIV_DMC0_DMCD_MASK |
  560. EXYNOS4_CLKDIV_DMC0_DMCP_MASK |
  561. EXYNOS4_CLKDIV_DMC0_COPY2_MASK |
  562. EXYNOS4_CLKDIV_DMC0_CORETI_MASK);
  563. tmp |= ((exynos4210_clkdiv_dmc0[i][0] <<
  564. EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) |
  565. (exynos4210_clkdiv_dmc0[i][1] <<
  566. EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) |
  567. (exynos4210_clkdiv_dmc0[i][2] <<
  568. EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) |
  569. (exynos4210_clkdiv_dmc0[i][3] <<
  570. EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) |
  571. (exynos4210_clkdiv_dmc0[i][4] <<
  572. EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) |
  573. (exynos4210_clkdiv_dmc0[i][5] <<
  574. EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT) |
  575. (exynos4210_clkdiv_dmc0[i][6] <<
  576. EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT) |
  577. (exynos4210_clkdiv_dmc0[i][7] <<
  578. EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT));
  579. data->dmc_divtable[i] = tmp;
  580. }
  581. tmp = __raw_readl(EXYNOS4_CLKDIV_TOP);
  582. for (i = LV_0; i < EX4210_LV_NUM; i++) {
  583. tmp &= ~(EXYNOS4_CLKDIV_TOP_ACLK200_MASK |
  584. EXYNOS4_CLKDIV_TOP_ACLK100_MASK |
  585. EXYNOS4_CLKDIV_TOP_ACLK160_MASK |
  586. EXYNOS4_CLKDIV_TOP_ACLK133_MASK |
  587. EXYNOS4_CLKDIV_TOP_ONENAND_MASK);
  588. tmp |= ((exynos4210_clkdiv_top[i][0] <<
  589. EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT) |
  590. (exynos4210_clkdiv_top[i][1] <<
  591. EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) |
  592. (exynos4210_clkdiv_top[i][2] <<
  593. EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) |
  594. (exynos4210_clkdiv_top[i][3] <<
  595. EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) |
  596. (exynos4210_clkdiv_top[i][4] <<
  597. EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT));
  598. data->top_divtable[i] = tmp;
  599. }
  600. /*
  601. * TODO: init tmp based on busfreq_data
  602. * (device-tree or platform-data)
  603. */
  604. tmp = 0; /* Max voltages for the reliability of the unknown */
  605. pr_debug("ASV Group of Exynos4 is %d\n", tmp);
  606. /* Use merged grouping for voltage */
  607. switch (tmp) {
  608. case 0:
  609. mgrp = 0;
  610. break;
  611. case 1:
  612. case 2:
  613. mgrp = 1;
  614. break;
  615. case 3:
  616. case 4:
  617. mgrp = 2;
  618. break;
  619. case 5:
  620. case 6:
  621. mgrp = 3;
  622. break;
  623. case 7:
  624. mgrp = 4;
  625. break;
  626. default:
  627. pr_warn("Unknown ASV Group. Use max voltage.\n");
  628. mgrp = 0;
  629. }
  630. for (i = LV_0; i < EX4210_LV_NUM; i++)
  631. exynos4210_busclk_table[i].volt = exynos4210_asv_volt[mgrp][i];
  632. for (i = LV_0; i < EX4210_LV_NUM; i++) {
  633. err = dev_pm_opp_add(data->dev, exynos4210_busclk_table[i].clk,
  634. exynos4210_busclk_table[i].volt);
  635. if (err) {
  636. dev_err(data->dev, "Cannot add opp entries.\n");
  637. return err;
  638. }
  639. }
  640. return 0;
  641. }
  642. static int exynos4x12_init_tables(struct busfreq_data *data)
  643. {
  644. unsigned int i;
  645. unsigned int tmp;
  646. int ret;
  647. /* Enable pause function for DREX2 DVFS */
  648. tmp = __raw_readl(EXYNOS4_DMC_PAUSE_CTRL);
  649. tmp |= EXYNOS4_DMC_PAUSE_ENABLE;
  650. __raw_writel(tmp, EXYNOS4_DMC_PAUSE_CTRL);
  651. tmp = __raw_readl(EXYNOS4_CLKDIV_DMC0);
  652. for (i = 0; i < EX4x12_LV_NUM; i++) {
  653. tmp &= ~(EXYNOS4_CLKDIV_DMC0_ACP_MASK |
  654. EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK |
  655. EXYNOS4_CLKDIV_DMC0_DPHY_MASK |
  656. EXYNOS4_CLKDIV_DMC0_DMC_MASK |
  657. EXYNOS4_CLKDIV_DMC0_DMCD_MASK |
  658. EXYNOS4_CLKDIV_DMC0_DMCP_MASK);
  659. tmp |= ((exynos4x12_clkdiv_dmc0[i][0] <<
  660. EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) |
  661. (exynos4x12_clkdiv_dmc0[i][1] <<
  662. EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) |
  663. (exynos4x12_clkdiv_dmc0[i][2] <<
  664. EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) |
  665. (exynos4x12_clkdiv_dmc0[i][3] <<
  666. EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) |
  667. (exynos4x12_clkdiv_dmc0[i][4] <<
  668. EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) |
  669. (exynos4x12_clkdiv_dmc0[i][5] <<
  670. EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT));
  671. data->dmc_divtable[i] = tmp;
  672. }
  673. tmp = 0; /* Max voltages for the reliability of the unknown */
  674. if (tmp > 8)
  675. tmp = 0;
  676. pr_debug("ASV Group of Exynos4x12 is %d\n", tmp);
  677. for (i = 0; i < EX4x12_LV_NUM; i++) {
  678. exynos4x12_mifclk_table[i].volt =
  679. exynos4x12_mif_step_50[tmp][i];
  680. exynos4x12_intclk_table[i].volt =
  681. exynos4x12_int_volt[tmp][i];
  682. }
  683. for (i = 0; i < EX4x12_LV_NUM; i++) {
  684. ret = dev_pm_opp_add(data->dev, exynos4x12_mifclk_table[i].clk,
  685. exynos4x12_mifclk_table[i].volt);
  686. if (ret) {
  687. dev_err(data->dev, "Fail to add opp entries.\n");
  688. return ret;
  689. }
  690. }
  691. return 0;
  692. }
  693. static int exynos4_busfreq_pm_notifier_event(struct notifier_block *this,
  694. unsigned long event, void *ptr)
  695. {
  696. struct busfreq_data *data = container_of(this, struct busfreq_data,
  697. pm_notifier);
  698. struct dev_pm_opp *opp;
  699. struct busfreq_opp_info new_oppinfo;
  700. unsigned long maxfreq = ULONG_MAX;
  701. int err = 0;
  702. switch (event) {
  703. case PM_SUSPEND_PREPARE:
  704. /* Set Fastest and Deactivate DVFS */
  705. mutex_lock(&data->lock);
  706. data->disabled = true;
  707. rcu_read_lock();
  708. opp = dev_pm_opp_find_freq_floor(data->dev, &maxfreq);
  709. if (IS_ERR(opp)) {
  710. rcu_read_unlock();
  711. dev_err(data->dev, "%s: unable to find a min freq\n",
  712. __func__);
  713. mutex_unlock(&data->lock);
  714. return PTR_ERR(opp);
  715. }
  716. new_oppinfo.rate = dev_pm_opp_get_freq(opp);
  717. new_oppinfo.volt = dev_pm_opp_get_voltage(opp);
  718. rcu_read_unlock();
  719. err = exynos4_bus_setvolt(data, &new_oppinfo,
  720. &data->curr_oppinfo);
  721. if (err)
  722. goto unlock;
  723. switch (data->type) {
  724. case TYPE_BUSF_EXYNOS4210:
  725. err = exynos4210_set_busclk(data, &new_oppinfo);
  726. break;
  727. case TYPE_BUSF_EXYNOS4x12:
  728. err = exynos4x12_set_busclk(data, &new_oppinfo);
  729. break;
  730. default:
  731. err = -EINVAL;
  732. }
  733. if (err)
  734. goto unlock;
  735. data->curr_oppinfo = new_oppinfo;
  736. unlock:
  737. mutex_unlock(&data->lock);
  738. if (err)
  739. return err;
  740. return NOTIFY_OK;
  741. case PM_POST_RESTORE:
  742. case PM_POST_SUSPEND:
  743. /* Reactivate */
  744. mutex_lock(&data->lock);
  745. data->disabled = false;
  746. mutex_unlock(&data->lock);
  747. return NOTIFY_OK;
  748. }
  749. return NOTIFY_DONE;
  750. }
  751. static int exynos4_busfreq_probe(struct platform_device *pdev)
  752. {
  753. struct busfreq_data *data;
  754. struct busfreq_ppmu_data *ppmu_data;
  755. struct dev_pm_opp *opp;
  756. struct device *dev = &pdev->dev;
  757. int err = 0;
  758. data = devm_kzalloc(&pdev->dev, sizeof(struct busfreq_data), GFP_KERNEL);
  759. if (data == NULL) {
  760. dev_err(dev, "Cannot allocate memory.\n");
  761. return -ENOMEM;
  762. }
  763. ppmu_data = &data->ppmu_data;
  764. ppmu_data->ppmu_end = PPMU_END;
  765. ppmu_data->ppmu = devm_kzalloc(dev,
  766. sizeof(struct exynos_ppmu) * PPMU_END,
  767. GFP_KERNEL);
  768. if (!ppmu_data->ppmu) {
  769. dev_err(dev, "Failed to allocate memory for exynos_ppmu\n");
  770. return -ENOMEM;
  771. }
  772. data->type = pdev->id_entry->driver_data;
  773. ppmu_data->ppmu[PPMU_DMC0].hw_base = S5P_VA_DMC0;
  774. ppmu_data->ppmu[PPMU_DMC1].hw_base = S5P_VA_DMC1;
  775. data->pm_notifier.notifier_call = exynos4_busfreq_pm_notifier_event;
  776. data->dev = dev;
  777. mutex_init(&data->lock);
  778. switch (data->type) {
  779. case TYPE_BUSF_EXYNOS4210:
  780. err = exynos4210_init_tables(data);
  781. break;
  782. case TYPE_BUSF_EXYNOS4x12:
  783. err = exynos4x12_init_tables(data);
  784. break;
  785. default:
  786. dev_err(dev, "Cannot determine the device id %d\n", data->type);
  787. err = -EINVAL;
  788. }
  789. if (err) {
  790. dev_err(dev, "Cannot initialize busfreq table %d\n",
  791. data->type);
  792. return err;
  793. }
  794. data->vdd_int = devm_regulator_get(dev, "vdd_int");
  795. if (IS_ERR(data->vdd_int)) {
  796. dev_err(dev, "Cannot get the regulator \"vdd_int\"\n");
  797. return PTR_ERR(data->vdd_int);
  798. }
  799. if (data->type == TYPE_BUSF_EXYNOS4x12) {
  800. data->vdd_mif = devm_regulator_get(dev, "vdd_mif");
  801. if (IS_ERR(data->vdd_mif)) {
  802. dev_err(dev, "Cannot get the regulator \"vdd_mif\"\n");
  803. return PTR_ERR(data->vdd_mif);
  804. }
  805. }
  806. rcu_read_lock();
  807. opp = dev_pm_opp_find_freq_floor(dev,
  808. &exynos4_devfreq_profile.initial_freq);
  809. if (IS_ERR(opp)) {
  810. rcu_read_unlock();
  811. dev_err(dev, "Invalid initial frequency %lu kHz.\n",
  812. exynos4_devfreq_profile.initial_freq);
  813. return PTR_ERR(opp);
  814. }
  815. data->curr_oppinfo.rate = dev_pm_opp_get_freq(opp);
  816. data->curr_oppinfo.volt = dev_pm_opp_get_voltage(opp);
  817. rcu_read_unlock();
  818. platform_set_drvdata(pdev, data);
  819. data->devfreq = devm_devfreq_add_device(dev, &exynos4_devfreq_profile,
  820. "simple_ondemand", NULL);
  821. if (IS_ERR(data->devfreq))
  822. return PTR_ERR(data->devfreq);
  823. /*
  824. * Start PPMU (Performance Profiling Monitoring Unit) to check
  825. * utilization of each IP in the Exynos4 SoC.
  826. */
  827. busfreq_mon_reset(ppmu_data);
  828. /* Register opp_notifier for Exynos4 busfreq */
  829. err = devm_devfreq_register_opp_notifier(dev, data->devfreq);
  830. if (err < 0) {
  831. dev_err(dev, "Failed to register opp notifier\n");
  832. return err;
  833. }
  834. /* Register pm_notifier for Exynos4 busfreq */
  835. err = register_pm_notifier(&data->pm_notifier);
  836. if (err) {
  837. dev_err(dev, "Failed to setup pm notifier\n");
  838. return err;
  839. }
  840. return 0;
  841. }
  842. static int exynos4_busfreq_remove(struct platform_device *pdev)
  843. {
  844. struct busfreq_data *data = platform_get_drvdata(pdev);
  845. /* Unregister all of notifier chain */
  846. unregister_pm_notifier(&data->pm_notifier);
  847. return 0;
  848. }
  849. #ifdef CONFIG_PM_SLEEP
  850. static int exynos4_busfreq_resume(struct device *dev)
  851. {
  852. struct busfreq_data *data = dev_get_drvdata(dev);
  853. struct busfreq_ppmu_data *ppmu_data = &data->ppmu_data;
  854. busfreq_mon_reset(ppmu_data);
  855. return 0;
  856. }
  857. #endif
  858. static SIMPLE_DEV_PM_OPS(exynos4_busfreq_pm_ops, NULL, exynos4_busfreq_resume);
  859. static const struct platform_device_id exynos4_busfreq_id[] = {
  860. { "exynos4210-busfreq", TYPE_BUSF_EXYNOS4210 },
  861. { "exynos4412-busfreq", TYPE_BUSF_EXYNOS4x12 },
  862. { "exynos4212-busfreq", TYPE_BUSF_EXYNOS4x12 },
  863. { },
  864. };
  865. static struct platform_driver exynos4_busfreq_driver = {
  866. .probe = exynos4_busfreq_probe,
  867. .remove = exynos4_busfreq_remove,
  868. .id_table = exynos4_busfreq_id,
  869. .driver = {
  870. .name = "exynos4-busfreq",
  871. .pm = &exynos4_busfreq_pm_ops,
  872. },
  873. };
  874. static int __init exynos4_busfreq_init(void)
  875. {
  876. return platform_driver_register(&exynos4_busfreq_driver);
  877. }
  878. late_initcall(exynos4_busfreq_init);
  879. static void __exit exynos4_busfreq_exit(void)
  880. {
  881. platform_driver_unregister(&exynos4_busfreq_driver);
  882. }
  883. module_exit(exynos4_busfreq_exit);
  884. MODULE_LICENSE("GPL");
  885. MODULE_DESCRIPTION("EXYNOS4 busfreq driver with devfreq framework");
  886. MODULE_AUTHOR("MyungJoo Ham <myungjoo.ham@samsung.com>");