ste_dma40_ll.h 13 KB

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  1. /*
  2. * Copyright (C) ST-Ericsson SA 2007-2010
  3. * Author: Per Friden <per.friden@stericsson.com> for ST-Ericsson SA
  4. * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson SA
  5. * License terms: GNU General Public License (GPL) version 2
  6. */
  7. #ifndef STE_DMA40_LL_H
  8. #define STE_DMA40_LL_H
  9. #define D40_DREG_PCBASE 0x400
  10. #define D40_DREG_PCDELTA (8 * 4)
  11. #define D40_LLI_ALIGN 16 /* LLI alignment must be 16 bytes. */
  12. #define D40_LCPA_CHAN_SIZE 32
  13. #define D40_LCPA_CHAN_DST_DELTA 16
  14. #define D40_TYPE_TO_GROUP(type) (type / 16)
  15. #define D40_TYPE_TO_EVENT(type) (type % 16)
  16. #define D40_GROUP_SIZE 8
  17. #define D40_PHYS_TO_GROUP(phys) ((phys & (D40_GROUP_SIZE - 1)) / 2)
  18. /* Most bits of the CFG register are the same in log as in phy mode */
  19. #define D40_SREG_CFG_MST_POS 15
  20. #define D40_SREG_CFG_TIM_POS 14
  21. #define D40_SREG_CFG_EIM_POS 13
  22. #define D40_SREG_CFG_LOG_INCR_POS 12
  23. #define D40_SREG_CFG_PHY_PEN_POS 12
  24. #define D40_SREG_CFG_PSIZE_POS 10
  25. #define D40_SREG_CFG_ESIZE_POS 8
  26. #define D40_SREG_CFG_PRI_POS 7
  27. #define D40_SREG_CFG_LBE_POS 6
  28. #define D40_SREG_CFG_LOG_GIM_POS 5
  29. #define D40_SREG_CFG_LOG_MFU_POS 4
  30. #define D40_SREG_CFG_PHY_TM_POS 4
  31. #define D40_SREG_CFG_PHY_EVTL_POS 0
  32. /* Standard channel parameters - basic mode (element register) */
  33. #define D40_SREG_ELEM_PHY_ECNT_POS 16
  34. #define D40_SREG_ELEM_PHY_EIDX_POS 0
  35. #define D40_SREG_ELEM_PHY_ECNT_MASK (0xFFFF << D40_SREG_ELEM_PHY_ECNT_POS)
  36. /* Standard channel parameters - basic mode (Link register) */
  37. #define D40_SREG_LNK_PHY_TCP_POS 0
  38. #define D40_SREG_LNK_PHY_LMP_POS 1
  39. #define D40_SREG_LNK_PHY_PRE_POS 2
  40. /*
  41. * Source destination link address. Contains the
  42. * 29-bit byte word aligned address of the reload area.
  43. */
  44. #define D40_SREG_LNK_PHYS_LNK_MASK 0xFFFFFFF8UL
  45. /* Standard basic channel logical mode */
  46. /* Element register */
  47. #define D40_SREG_ELEM_LOG_ECNT_POS 16
  48. #define D40_SREG_ELEM_LOG_LIDX_POS 8
  49. #define D40_SREG_ELEM_LOG_LOS_POS 1
  50. #define D40_SREG_ELEM_LOG_TCP_POS 0
  51. #define D40_SREG_ELEM_LOG_LIDX_MASK (0xFF << D40_SREG_ELEM_LOG_LIDX_POS)
  52. /* Link register */
  53. #define D40_EVENTLINE_POS(i) (2 * i)
  54. #define D40_EVENTLINE_MASK(i) (0x3 << D40_EVENTLINE_POS(i))
  55. /* Standard basic channel logical params in memory */
  56. /* LCSP0 */
  57. #define D40_MEM_LCSP0_ECNT_POS 16
  58. #define D40_MEM_LCSP0_SPTR_POS 0
  59. #define D40_MEM_LCSP0_ECNT_MASK (0xFFFF << D40_MEM_LCSP0_ECNT_POS)
  60. #define D40_MEM_LCSP0_SPTR_MASK (0xFFFF << D40_MEM_LCSP0_SPTR_POS)
  61. /* LCSP1 */
  62. #define D40_MEM_LCSP1_SPTR_POS 16
  63. #define D40_MEM_LCSP1_SCFG_MST_POS 15
  64. #define D40_MEM_LCSP1_SCFG_TIM_POS 14
  65. #define D40_MEM_LCSP1_SCFG_EIM_POS 13
  66. #define D40_MEM_LCSP1_SCFG_INCR_POS 12
  67. #define D40_MEM_LCSP1_SCFG_PSIZE_POS 10
  68. #define D40_MEM_LCSP1_SCFG_ESIZE_POS 8
  69. #define D40_MEM_LCSP1_SLOS_POS 1
  70. #define D40_MEM_LCSP1_STCP_POS 0
  71. #define D40_MEM_LCSP1_SPTR_MASK (0xFFFF << D40_MEM_LCSP1_SPTR_POS)
  72. #define D40_MEM_LCSP1_SCFG_TIM_MASK (0x1 << D40_MEM_LCSP1_SCFG_TIM_POS)
  73. #define D40_MEM_LCSP1_SCFG_INCR_MASK (0x1 << D40_MEM_LCSP1_SCFG_INCR_POS)
  74. #define D40_MEM_LCSP1_SCFG_PSIZE_MASK (0x3 << D40_MEM_LCSP1_SCFG_PSIZE_POS)
  75. #define D40_MEM_LCSP1_SLOS_MASK (0x7F << D40_MEM_LCSP1_SLOS_POS)
  76. #define D40_MEM_LCSP1_STCP_MASK (0x1 << D40_MEM_LCSP1_STCP_POS)
  77. /* LCSP2 */
  78. #define D40_MEM_LCSP2_ECNT_POS 16
  79. #define D40_MEM_LCSP2_ECNT_MASK (0xFFFF << D40_MEM_LCSP2_ECNT_POS)
  80. /* LCSP3 */
  81. #define D40_MEM_LCSP3_DCFG_MST_POS 15
  82. #define D40_MEM_LCSP3_DCFG_TIM_POS 14
  83. #define D40_MEM_LCSP3_DCFG_EIM_POS 13
  84. #define D40_MEM_LCSP3_DCFG_INCR_POS 12
  85. #define D40_MEM_LCSP3_DCFG_PSIZE_POS 10
  86. #define D40_MEM_LCSP3_DCFG_ESIZE_POS 8
  87. #define D40_MEM_LCSP3_DLOS_POS 1
  88. #define D40_MEM_LCSP3_DTCP_POS 0
  89. #define D40_MEM_LCSP3_DLOS_MASK (0x7F << D40_MEM_LCSP3_DLOS_POS)
  90. #define D40_MEM_LCSP3_DTCP_MASK (0x1 << D40_MEM_LCSP3_DTCP_POS)
  91. /* Standard channel parameter register offsets */
  92. #define D40_CHAN_REG_SSCFG 0x00
  93. #define D40_CHAN_REG_SSELT 0x04
  94. #define D40_CHAN_REG_SSPTR 0x08
  95. #define D40_CHAN_REG_SSLNK 0x0C
  96. #define D40_CHAN_REG_SDCFG 0x10
  97. #define D40_CHAN_REG_SDELT 0x14
  98. #define D40_CHAN_REG_SDPTR 0x18
  99. #define D40_CHAN_REG_SDLNK 0x1C
  100. /* DMA Register Offsets */
  101. #define D40_DREG_GCC 0x000
  102. #define D40_DREG_GCC_ENA 0x1
  103. /* This assumes that there are only 4 event groups */
  104. #define D40_DREG_GCC_ENABLE_ALL 0x3ff01
  105. #define D40_DREG_GCC_EVTGRP_POS 8
  106. #define D40_DREG_GCC_SRC 0
  107. #define D40_DREG_GCC_DST 1
  108. #define D40_DREG_GCC_EVTGRP_ENA(x, y) \
  109. (1 << (D40_DREG_GCC_EVTGRP_POS + 2 * x + y))
  110. #define D40_DREG_PRTYP 0x004
  111. #define D40_DREG_PRSME 0x008
  112. #define D40_DREG_PRSMO 0x00C
  113. #define D40_DREG_PRMSE 0x010
  114. #define D40_DREG_PRMSO 0x014
  115. #define D40_DREG_PRMOE 0x018
  116. #define D40_DREG_PRMOO 0x01C
  117. #define D40_DREG_PRMO_PCHAN_BASIC 0x1
  118. #define D40_DREG_PRMO_PCHAN_MODULO 0x2
  119. #define D40_DREG_PRMO_PCHAN_DOUBLE_DST 0x3
  120. #define D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG 0x1
  121. #define D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY 0x2
  122. #define D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG 0x3
  123. #define D40_DREG_LCPA 0x020
  124. #define D40_DREG_LCLA 0x024
  125. #define D40_DREG_SSEG1 0x030
  126. #define D40_DREG_SSEG2 0x034
  127. #define D40_DREG_SSEG3 0x038
  128. #define D40_DREG_SSEG4 0x03C
  129. #define D40_DREG_SCEG1 0x040
  130. #define D40_DREG_SCEG2 0x044
  131. #define D40_DREG_SCEG3 0x048
  132. #define D40_DREG_SCEG4 0x04C
  133. #define D40_DREG_ACTIVE 0x050
  134. #define D40_DREG_ACTIVO 0x054
  135. #define D40_DREG_CIDMOD 0x058
  136. #define D40_DREG_TCIDV 0x05C
  137. #define D40_DREG_PCMIS 0x060
  138. #define D40_DREG_PCICR 0x064
  139. #define D40_DREG_PCTIS 0x068
  140. #define D40_DREG_PCEIS 0x06C
  141. #define D40_DREG_SPCMIS 0x070
  142. #define D40_DREG_SPCICR 0x074
  143. #define D40_DREG_SPCTIS 0x078
  144. #define D40_DREG_SPCEIS 0x07C
  145. #define D40_DREG_LCMIS0 0x080
  146. #define D40_DREG_LCMIS1 0x084
  147. #define D40_DREG_LCMIS2 0x088
  148. #define D40_DREG_LCMIS3 0x08C
  149. #define D40_DREG_LCICR0 0x090
  150. #define D40_DREG_LCICR1 0x094
  151. #define D40_DREG_LCICR2 0x098
  152. #define D40_DREG_LCICR3 0x09C
  153. #define D40_DREG_LCTIS0 0x0A0
  154. #define D40_DREG_LCTIS1 0x0A4
  155. #define D40_DREG_LCTIS2 0x0A8
  156. #define D40_DREG_LCTIS3 0x0AC
  157. #define D40_DREG_LCEIS0 0x0B0
  158. #define D40_DREG_LCEIS1 0x0B4
  159. #define D40_DREG_LCEIS2 0x0B8
  160. #define D40_DREG_LCEIS3 0x0BC
  161. #define D40_DREG_SLCMIS1 0x0C0
  162. #define D40_DREG_SLCMIS2 0x0C4
  163. #define D40_DREG_SLCMIS3 0x0C8
  164. #define D40_DREG_SLCMIS4 0x0CC
  165. #define D40_DREG_SLCICR1 0x0D0
  166. #define D40_DREG_SLCICR2 0x0D4
  167. #define D40_DREG_SLCICR3 0x0D8
  168. #define D40_DREG_SLCICR4 0x0DC
  169. #define D40_DREG_SLCTIS1 0x0E0
  170. #define D40_DREG_SLCTIS2 0x0E4
  171. #define D40_DREG_SLCTIS3 0x0E8
  172. #define D40_DREG_SLCTIS4 0x0EC
  173. #define D40_DREG_SLCEIS1 0x0F0
  174. #define D40_DREG_SLCEIS2 0x0F4
  175. #define D40_DREG_SLCEIS3 0x0F8
  176. #define D40_DREG_SLCEIS4 0x0FC
  177. #define D40_DREG_FSESS1 0x100
  178. #define D40_DREG_FSESS2 0x104
  179. #define D40_DREG_FSEBS1 0x108
  180. #define D40_DREG_FSEBS2 0x10C
  181. #define D40_DREG_PSEG1 0x110
  182. #define D40_DREG_PSEG2 0x114
  183. #define D40_DREG_PSEG3 0x118
  184. #define D40_DREG_PSEG4 0x11C
  185. #define D40_DREG_PCEG1 0x120
  186. #define D40_DREG_PCEG2 0x124
  187. #define D40_DREG_PCEG3 0x128
  188. #define D40_DREG_PCEG4 0x12C
  189. #define D40_DREG_RSEG1 0x130
  190. #define D40_DREG_RSEG2 0x134
  191. #define D40_DREG_RSEG3 0x138
  192. #define D40_DREG_RSEG4 0x13C
  193. #define D40_DREG_RCEG1 0x140
  194. #define D40_DREG_RCEG2 0x144
  195. #define D40_DREG_RCEG3 0x148
  196. #define D40_DREG_RCEG4 0x14C
  197. #define D40_DREG_PREFOT 0x15C
  198. #define D40_DREG_EXTCFG 0x160
  199. #define D40_DREG_CPSEG1 0x200
  200. #define D40_DREG_CPSEG2 0x204
  201. #define D40_DREG_CPSEG3 0x208
  202. #define D40_DREG_CPSEG4 0x20C
  203. #define D40_DREG_CPSEG5 0x210
  204. #define D40_DREG_CPCEG1 0x220
  205. #define D40_DREG_CPCEG2 0x224
  206. #define D40_DREG_CPCEG3 0x228
  207. #define D40_DREG_CPCEG4 0x22C
  208. #define D40_DREG_CPCEG5 0x230
  209. #define D40_DREG_CRSEG1 0x240
  210. #define D40_DREG_CRSEG2 0x244
  211. #define D40_DREG_CRSEG3 0x248
  212. #define D40_DREG_CRSEG4 0x24C
  213. #define D40_DREG_CRSEG5 0x250
  214. #define D40_DREG_CRCEG1 0x260
  215. #define D40_DREG_CRCEG2 0x264
  216. #define D40_DREG_CRCEG3 0x268
  217. #define D40_DREG_CRCEG4 0x26C
  218. #define D40_DREG_CRCEG5 0x270
  219. #define D40_DREG_CFSESS1 0x280
  220. #define D40_DREG_CFSESS2 0x284
  221. #define D40_DREG_CFSESS3 0x288
  222. #define D40_DREG_CFSEBS1 0x290
  223. #define D40_DREG_CFSEBS2 0x294
  224. #define D40_DREG_CFSEBS3 0x298
  225. #define D40_DREG_CLCMIS1 0x300
  226. #define D40_DREG_CLCMIS2 0x304
  227. #define D40_DREG_CLCMIS3 0x308
  228. #define D40_DREG_CLCMIS4 0x30C
  229. #define D40_DREG_CLCMIS5 0x310
  230. #define D40_DREG_CLCICR1 0x320
  231. #define D40_DREG_CLCICR2 0x324
  232. #define D40_DREG_CLCICR3 0x328
  233. #define D40_DREG_CLCICR4 0x32C
  234. #define D40_DREG_CLCICR5 0x330
  235. #define D40_DREG_CLCTIS1 0x340
  236. #define D40_DREG_CLCTIS2 0x344
  237. #define D40_DREG_CLCTIS3 0x348
  238. #define D40_DREG_CLCTIS4 0x34C
  239. #define D40_DREG_CLCTIS5 0x350
  240. #define D40_DREG_CLCEIS1 0x360
  241. #define D40_DREG_CLCEIS2 0x364
  242. #define D40_DREG_CLCEIS3 0x368
  243. #define D40_DREG_CLCEIS4 0x36C
  244. #define D40_DREG_CLCEIS5 0x370
  245. #define D40_DREG_CPCMIS 0x380
  246. #define D40_DREG_CPCICR 0x384
  247. #define D40_DREG_CPCTIS 0x388
  248. #define D40_DREG_CPCEIS 0x38C
  249. #define D40_DREG_SCCIDA1 0xE80
  250. #define D40_DREG_SCCIDA2 0xE90
  251. #define D40_DREG_SCCIDA3 0xEA0
  252. #define D40_DREG_SCCIDA4 0xEB0
  253. #define D40_DREG_SCCIDA5 0xEC0
  254. #define D40_DREG_SCCIDB1 0xE84
  255. #define D40_DREG_SCCIDB2 0xE94
  256. #define D40_DREG_SCCIDB3 0xEA4
  257. #define D40_DREG_SCCIDB4 0xEB4
  258. #define D40_DREG_SCCIDB5 0xEC4
  259. #define D40_DREG_PRSCCIDA 0xF80
  260. #define D40_DREG_PRSCCIDB 0xF84
  261. #define D40_DREG_STFU 0xFC8
  262. #define D40_DREG_ICFG 0xFCC
  263. #define D40_DREG_PERIPHID0 0xFE0
  264. #define D40_DREG_PERIPHID1 0xFE4
  265. #define D40_DREG_PERIPHID2 0xFE8
  266. #define D40_DREG_PERIPHID3 0xFEC
  267. #define D40_DREG_CELLID0 0xFF0
  268. #define D40_DREG_CELLID1 0xFF4
  269. #define D40_DREG_CELLID2 0xFF8
  270. #define D40_DREG_CELLID3 0xFFC
  271. /* LLI related structures */
  272. /**
  273. * struct d40_phy_lli - The basic configuration register for each physical
  274. * channel.
  275. *
  276. * @reg_cfg: The configuration register.
  277. * @reg_elt: The element register.
  278. * @reg_ptr: The pointer register.
  279. * @reg_lnk: The link register.
  280. *
  281. * These registers are set up for both physical and logical transfers
  282. * Note that the bit in each register means differently in logical and
  283. * physical(standard) mode.
  284. *
  285. * This struct must be 16 bytes aligned, and only contain physical registers
  286. * since it will be directly accessed by the DMA.
  287. */
  288. struct d40_phy_lli {
  289. u32 reg_cfg;
  290. u32 reg_elt;
  291. u32 reg_ptr;
  292. u32 reg_lnk;
  293. };
  294. /**
  295. * struct d40_phy_lli_bidir - struct for a transfer.
  296. *
  297. * @src: Register settings for src channel.
  298. * @dst: Register settings for dst channel.
  299. *
  300. * All DMA transfers have a source and a destination.
  301. */
  302. struct d40_phy_lli_bidir {
  303. struct d40_phy_lli *src;
  304. struct d40_phy_lli *dst;
  305. };
  306. /**
  307. * struct d40_log_lli - logical lli configuration
  308. *
  309. * @lcsp02: Either maps to register lcsp0 if src or lcsp2 if dst.
  310. * @lcsp13: Either maps to register lcsp1 if src or lcsp3 if dst.
  311. *
  312. * This struct must be 8 bytes aligned since it will be accessed directy by
  313. * the DMA. Never add any none hw mapped registers to this struct.
  314. */
  315. struct d40_log_lli {
  316. u32 lcsp02;
  317. u32 lcsp13;
  318. };
  319. /**
  320. * struct d40_log_lli_bidir - For both src and dst
  321. *
  322. * @src: pointer to src lli configuration.
  323. * @dst: pointer to dst lli configuration.
  324. *
  325. * You always have a src and a dst when doing DMA transfers.
  326. */
  327. struct d40_log_lli_bidir {
  328. struct d40_log_lli *src;
  329. struct d40_log_lli *dst;
  330. };
  331. /**
  332. * struct d40_log_lli_full - LCPA layout
  333. *
  334. * @lcsp0: Logical Channel Standard Param 0 - Src.
  335. * @lcsp1: Logical Channel Standard Param 1 - Src.
  336. * @lcsp2: Logical Channel Standard Param 2 - Dst.
  337. * @lcsp3: Logical Channel Standard Param 3 - Dst.
  338. *
  339. * This struct maps to LCPA physical memory layout. Must map to
  340. * the hw.
  341. */
  342. struct d40_log_lli_full {
  343. u32 lcsp0;
  344. u32 lcsp1;
  345. u32 lcsp2;
  346. u32 lcsp3;
  347. };
  348. /**
  349. * struct d40_def_lcsp - Default LCSP1 and LCSP3 settings
  350. *
  351. * @lcsp3: The default configuration for dst.
  352. * @lcsp1: The default configuration for src.
  353. */
  354. struct d40_def_lcsp {
  355. u32 lcsp3;
  356. u32 lcsp1;
  357. };
  358. /* Physical channels */
  359. enum d40_lli_flags {
  360. LLI_ADDR_INC = 1 << 0,
  361. LLI_TERM_INT = 1 << 1,
  362. LLI_CYCLIC = 1 << 2,
  363. LLI_LAST_LINK = 1 << 3,
  364. };
  365. void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
  366. u32 *src_cfg,
  367. u32 *dst_cfg);
  368. void d40_log_cfg(struct stedma40_chan_cfg *cfg,
  369. u32 *lcsp1,
  370. u32 *lcsp2);
  371. int d40_phy_sg_to_lli(struct scatterlist *sg,
  372. int sg_len,
  373. dma_addr_t target,
  374. struct d40_phy_lli *lli,
  375. dma_addr_t lli_phys,
  376. u32 reg_cfg,
  377. struct stedma40_half_channel_info *info,
  378. struct stedma40_half_channel_info *otherinfo,
  379. unsigned long flags);
  380. /* Logical channels */
  381. int d40_log_sg_to_lli(struct scatterlist *sg,
  382. int sg_len,
  383. dma_addr_t dev_addr,
  384. struct d40_log_lli *lli_sg,
  385. u32 lcsp13, /* src or dst*/
  386. u32 data_width1, u32 data_width2);
  387. void d40_log_lli_lcpa_write(struct d40_log_lli_full *lcpa,
  388. struct d40_log_lli *lli_dst,
  389. struct d40_log_lli *lli_src,
  390. int next, unsigned int flags);
  391. void d40_log_lli_lcla_write(struct d40_log_lli *lcla,
  392. struct d40_log_lli *lli_dst,
  393. struct d40_log_lli *lli_src,
  394. int next, unsigned int flags);
  395. #endif /* STE_DMA40_LLI_H */