ohci.h 7.0 KB

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  1. #ifndef _FIREWIRE_OHCI_H
  2. #define _FIREWIRE_OHCI_H
  3. /* OHCI register map */
  4. #define OHCI1394_Version 0x000
  5. #define OHCI1394_GUID_ROM 0x004
  6. #define OHCI1394_ATRetries 0x008
  7. #define OHCI1394_CSRData 0x00C
  8. #define OHCI1394_CSRCompareData 0x010
  9. #define OHCI1394_CSRControl 0x014
  10. #define OHCI1394_ConfigROMhdr 0x018
  11. #define OHCI1394_BusID 0x01C
  12. #define OHCI1394_BusOptions 0x020
  13. #define OHCI1394_GUIDHi 0x024
  14. #define OHCI1394_GUIDLo 0x028
  15. #define OHCI1394_ConfigROMmap 0x034
  16. #define OHCI1394_PostedWriteAddressLo 0x038
  17. #define OHCI1394_PostedWriteAddressHi 0x03C
  18. #define OHCI1394_VendorID 0x040
  19. #define OHCI1394_HCControlSet 0x050
  20. #define OHCI1394_HCControlClear 0x054
  21. #define OHCI1394_HCControl_BIBimageValid 0x80000000
  22. #define OHCI1394_HCControl_noByteSwapData 0x40000000
  23. #define OHCI1394_HCControl_programPhyEnable 0x00800000
  24. #define OHCI1394_HCControl_aPhyEnhanceEnable 0x00400000
  25. #define OHCI1394_HCControl_LPS 0x00080000
  26. #define OHCI1394_HCControl_postedWriteEnable 0x00040000
  27. #define OHCI1394_HCControl_linkEnable 0x00020000
  28. #define OHCI1394_HCControl_softReset 0x00010000
  29. #define OHCI1394_SelfIDBuffer 0x064
  30. #define OHCI1394_SelfIDCount 0x068
  31. #define OHCI1394_SelfIDCount_selfIDError 0x80000000
  32. #define OHCI1394_IRMultiChanMaskHiSet 0x070
  33. #define OHCI1394_IRMultiChanMaskHiClear 0x074
  34. #define OHCI1394_IRMultiChanMaskLoSet 0x078
  35. #define OHCI1394_IRMultiChanMaskLoClear 0x07C
  36. #define OHCI1394_IntEventSet 0x080
  37. #define OHCI1394_IntEventClear 0x084
  38. #define OHCI1394_IntMaskSet 0x088
  39. #define OHCI1394_IntMaskClear 0x08C
  40. #define OHCI1394_IsoXmitIntEventSet 0x090
  41. #define OHCI1394_IsoXmitIntEventClear 0x094
  42. #define OHCI1394_IsoXmitIntMaskSet 0x098
  43. #define OHCI1394_IsoXmitIntMaskClear 0x09C
  44. #define OHCI1394_IsoRecvIntEventSet 0x0A0
  45. #define OHCI1394_IsoRecvIntEventClear 0x0A4
  46. #define OHCI1394_IsoRecvIntMaskSet 0x0A8
  47. #define OHCI1394_IsoRecvIntMaskClear 0x0AC
  48. #define OHCI1394_InitialBandwidthAvailable 0x0B0
  49. #define OHCI1394_InitialChannelsAvailableHi 0x0B4
  50. #define OHCI1394_InitialChannelsAvailableLo 0x0B8
  51. #define OHCI1394_FairnessControl 0x0DC
  52. #define OHCI1394_LinkControlSet 0x0E0
  53. #define OHCI1394_LinkControlClear 0x0E4
  54. #define OHCI1394_LinkControl_rcvSelfID (1 << 9)
  55. #define OHCI1394_LinkControl_rcvPhyPkt (1 << 10)
  56. #define OHCI1394_LinkControl_cycleTimerEnable (1 << 20)
  57. #define OHCI1394_LinkControl_cycleMaster (1 << 21)
  58. #define OHCI1394_LinkControl_cycleSource (1 << 22)
  59. #define OHCI1394_NodeID 0x0E8
  60. #define OHCI1394_NodeID_idValid 0x80000000
  61. #define OHCI1394_NodeID_root 0x40000000
  62. #define OHCI1394_NodeID_nodeNumber 0x0000003f
  63. #define OHCI1394_NodeID_busNumber 0x0000ffc0
  64. #define OHCI1394_PhyControl 0x0EC
  65. #define OHCI1394_PhyControl_Read(addr) (((addr) << 8) | 0x00008000)
  66. #define OHCI1394_PhyControl_ReadDone 0x80000000
  67. #define OHCI1394_PhyControl_ReadData(r) (((r) & 0x00ff0000) >> 16)
  68. #define OHCI1394_PhyControl_Write(addr, data) (((addr) << 8) | (data) | 0x00004000)
  69. #define OHCI1394_PhyControl_WritePending 0x00004000
  70. #define OHCI1394_IsochronousCycleTimer 0x0F0
  71. #define OHCI1394_AsReqFilterHiSet 0x100
  72. #define OHCI1394_AsReqFilterHiClear 0x104
  73. #define OHCI1394_AsReqFilterLoSet 0x108
  74. #define OHCI1394_AsReqFilterLoClear 0x10C
  75. #define OHCI1394_PhyReqFilterHiSet 0x110
  76. #define OHCI1394_PhyReqFilterHiClear 0x114
  77. #define OHCI1394_PhyReqFilterLoSet 0x118
  78. #define OHCI1394_PhyReqFilterLoClear 0x11C
  79. #define OHCI1394_PhyUpperBound 0x120
  80. #define OHCI1394_AsReqTrContextBase 0x180
  81. #define OHCI1394_AsReqTrContextControlSet 0x180
  82. #define OHCI1394_AsReqTrContextControlClear 0x184
  83. #define OHCI1394_AsReqTrCommandPtr 0x18C
  84. #define OHCI1394_AsRspTrContextBase 0x1A0
  85. #define OHCI1394_AsRspTrContextControlSet 0x1A0
  86. #define OHCI1394_AsRspTrContextControlClear 0x1A4
  87. #define OHCI1394_AsRspTrCommandPtr 0x1AC
  88. #define OHCI1394_AsReqRcvContextBase 0x1C0
  89. #define OHCI1394_AsReqRcvContextControlSet 0x1C0
  90. #define OHCI1394_AsReqRcvContextControlClear 0x1C4
  91. #define OHCI1394_AsReqRcvCommandPtr 0x1CC
  92. #define OHCI1394_AsRspRcvContextBase 0x1E0
  93. #define OHCI1394_AsRspRcvContextControlSet 0x1E0
  94. #define OHCI1394_AsRspRcvContextControlClear 0x1E4
  95. #define OHCI1394_AsRspRcvCommandPtr 0x1EC
  96. /* Isochronous transmit registers */
  97. #define OHCI1394_IsoXmitContextBase(n) (0x200 + 16 * (n))
  98. #define OHCI1394_IsoXmitContextControlSet(n) (0x200 + 16 * (n))
  99. #define OHCI1394_IsoXmitContextControlClear(n) (0x204 + 16 * (n))
  100. #define OHCI1394_IsoXmitCommandPtr(n) (0x20C + 16 * (n))
  101. /* Isochronous receive registers */
  102. #define OHCI1394_IsoRcvContextBase(n) (0x400 + 32 * (n))
  103. #define OHCI1394_IsoRcvContextControlSet(n) (0x400 + 32 * (n))
  104. #define OHCI1394_IsoRcvContextControlClear(n) (0x404 + 32 * (n))
  105. #define OHCI1394_IsoRcvCommandPtr(n) (0x40C + 32 * (n))
  106. #define OHCI1394_IsoRcvContextMatch(n) (0x410 + 32 * (n))
  107. /* Interrupts Mask/Events */
  108. #define OHCI1394_reqTxComplete 0x00000001
  109. #define OHCI1394_respTxComplete 0x00000002
  110. #define OHCI1394_ARRQ 0x00000004
  111. #define OHCI1394_ARRS 0x00000008
  112. #define OHCI1394_RQPkt 0x00000010
  113. #define OHCI1394_RSPkt 0x00000020
  114. #define OHCI1394_isochTx 0x00000040
  115. #define OHCI1394_isochRx 0x00000080
  116. #define OHCI1394_postedWriteErr 0x00000100
  117. #define OHCI1394_lockRespErr 0x00000200
  118. #define OHCI1394_selfIDComplete 0x00010000
  119. #define OHCI1394_busReset 0x00020000
  120. #define OHCI1394_regAccessFail 0x00040000
  121. #define OHCI1394_phy 0x00080000
  122. #define OHCI1394_cycleSynch 0x00100000
  123. #define OHCI1394_cycle64Seconds 0x00200000
  124. #define OHCI1394_cycleLost 0x00400000
  125. #define OHCI1394_cycleInconsistent 0x00800000
  126. #define OHCI1394_unrecoverableError 0x01000000
  127. #define OHCI1394_cycleTooLong 0x02000000
  128. #define OHCI1394_phyRegRcvd 0x04000000
  129. #define OHCI1394_masterIntEnable 0x80000000
  130. #define OHCI1394_evt_no_status 0x0
  131. #define OHCI1394_evt_long_packet 0x2
  132. #define OHCI1394_evt_missing_ack 0x3
  133. #define OHCI1394_evt_underrun 0x4
  134. #define OHCI1394_evt_overrun 0x5
  135. #define OHCI1394_evt_descriptor_read 0x6
  136. #define OHCI1394_evt_data_read 0x7
  137. #define OHCI1394_evt_data_write 0x8
  138. #define OHCI1394_evt_bus_reset 0x9
  139. #define OHCI1394_evt_timeout 0xa
  140. #define OHCI1394_evt_tcode_err 0xb
  141. #define OHCI1394_evt_reserved_b 0xc
  142. #define OHCI1394_evt_reserved_c 0xd
  143. #define OHCI1394_evt_unknown 0xe
  144. #define OHCI1394_evt_flushed 0xf
  145. #define OHCI1394_phy_tcode 0xe
  146. #endif /* _FIREWIRE_OHCI_H */