gpio-dwapb.c 17 KB

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  1. /*
  2. * Copyright (c) 2011 Jamie Iles
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. *
  8. * All enquiries to support@picochip.com
  9. */
  10. #include <linux/basic_mmio_gpio.h>
  11. #include <linux/err.h>
  12. #include <linux/init.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/io.h>
  15. #include <linux/ioport.h>
  16. #include <linux/irq.h>
  17. #include <linux/irqdomain.h>
  18. #include <linux/module.h>
  19. #include <linux/of.h>
  20. #include <linux/of_address.h>
  21. #include <linux/of_irq.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/spinlock.h>
  24. #include <linux/platform_data/gpio-dwapb.h>
  25. #include <linux/slab.h>
  26. #define GPIO_SWPORTA_DR 0x00
  27. #define GPIO_SWPORTA_DDR 0x04
  28. #define GPIO_SWPORTB_DR 0x0c
  29. #define GPIO_SWPORTB_DDR 0x10
  30. #define GPIO_SWPORTC_DR 0x18
  31. #define GPIO_SWPORTC_DDR 0x1c
  32. #define GPIO_SWPORTD_DR 0x24
  33. #define GPIO_SWPORTD_DDR 0x28
  34. #define GPIO_INTEN 0x30
  35. #define GPIO_INTMASK 0x34
  36. #define GPIO_INTTYPE_LEVEL 0x38
  37. #define GPIO_INT_POLARITY 0x3c
  38. #define GPIO_INTSTATUS 0x40
  39. #define GPIO_PORTA_DEBOUNCE 0x48
  40. #define GPIO_PORTA_EOI 0x4c
  41. #define GPIO_EXT_PORTA 0x50
  42. #define GPIO_EXT_PORTB 0x54
  43. #define GPIO_EXT_PORTC 0x58
  44. #define GPIO_EXT_PORTD 0x5c
  45. #define DWAPB_MAX_PORTS 4
  46. #define GPIO_EXT_PORT_SIZE (GPIO_EXT_PORTB - GPIO_EXT_PORTA)
  47. #define GPIO_SWPORT_DR_SIZE (GPIO_SWPORTB_DR - GPIO_SWPORTA_DR)
  48. #define GPIO_SWPORT_DDR_SIZE (GPIO_SWPORTB_DDR - GPIO_SWPORTA_DDR)
  49. struct dwapb_gpio;
  50. #ifdef CONFIG_PM_SLEEP
  51. /* Store GPIO context across system-wide suspend/resume transitions */
  52. struct dwapb_context {
  53. u32 data;
  54. u32 dir;
  55. u32 ext;
  56. u32 int_en;
  57. u32 int_mask;
  58. u32 int_type;
  59. u32 int_pol;
  60. u32 int_deb;
  61. };
  62. #endif
  63. struct dwapb_gpio_port {
  64. struct bgpio_chip bgc;
  65. bool is_registered;
  66. struct dwapb_gpio *gpio;
  67. #ifdef CONFIG_PM_SLEEP
  68. struct dwapb_context *ctx;
  69. #endif
  70. unsigned int idx;
  71. };
  72. struct dwapb_gpio {
  73. struct device *dev;
  74. void __iomem *regs;
  75. struct dwapb_gpio_port *ports;
  76. unsigned int nr_ports;
  77. struct irq_domain *domain;
  78. };
  79. static inline struct dwapb_gpio_port *
  80. to_dwapb_gpio_port(struct bgpio_chip *bgc)
  81. {
  82. return container_of(bgc, struct dwapb_gpio_port, bgc);
  83. }
  84. static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
  85. {
  86. struct bgpio_chip *bgc = &gpio->ports[0].bgc;
  87. void __iomem *reg_base = gpio->regs;
  88. return bgc->read_reg(reg_base + offset);
  89. }
  90. static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
  91. u32 val)
  92. {
  93. struct bgpio_chip *bgc = &gpio->ports[0].bgc;
  94. void __iomem *reg_base = gpio->regs;
  95. bgc->write_reg(reg_base + offset, val);
  96. }
  97. static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
  98. {
  99. struct bgpio_chip *bgc = to_bgpio_chip(gc);
  100. struct dwapb_gpio_port *port = to_dwapb_gpio_port(bgc);
  101. struct dwapb_gpio *gpio = port->gpio;
  102. return irq_find_mapping(gpio->domain, offset);
  103. }
  104. static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
  105. {
  106. u32 v = dwapb_read(gpio, GPIO_INT_POLARITY);
  107. if (gpio_get_value(gpio->ports[0].bgc.gc.base + offs))
  108. v &= ~BIT(offs);
  109. else
  110. v |= BIT(offs);
  111. dwapb_write(gpio, GPIO_INT_POLARITY, v);
  112. }
  113. static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
  114. {
  115. u32 irq_status = readl_relaxed(gpio->regs + GPIO_INTSTATUS);
  116. u32 ret = irq_status;
  117. while (irq_status) {
  118. int hwirq = fls(irq_status) - 1;
  119. int gpio_irq = irq_find_mapping(gpio->domain, hwirq);
  120. generic_handle_irq(gpio_irq);
  121. irq_status &= ~BIT(hwirq);
  122. if ((irq_get_trigger_type(gpio_irq) & IRQ_TYPE_SENSE_MASK)
  123. == IRQ_TYPE_EDGE_BOTH)
  124. dwapb_toggle_trigger(gpio, hwirq);
  125. }
  126. return ret;
  127. }
  128. static void dwapb_irq_handler(struct irq_desc *desc)
  129. {
  130. struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
  131. struct irq_chip *chip = irq_desc_get_chip(desc);
  132. dwapb_do_irq(gpio);
  133. if (chip->irq_eoi)
  134. chip->irq_eoi(irq_desc_get_irq_data(desc));
  135. }
  136. static void dwapb_irq_enable(struct irq_data *d)
  137. {
  138. struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
  139. struct dwapb_gpio *gpio = igc->private;
  140. struct bgpio_chip *bgc = &gpio->ports[0].bgc;
  141. unsigned long flags;
  142. u32 val;
  143. spin_lock_irqsave(&bgc->lock, flags);
  144. val = dwapb_read(gpio, GPIO_INTEN);
  145. val |= BIT(d->hwirq);
  146. dwapb_write(gpio, GPIO_INTEN, val);
  147. spin_unlock_irqrestore(&bgc->lock, flags);
  148. }
  149. static void dwapb_irq_disable(struct irq_data *d)
  150. {
  151. struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
  152. struct dwapb_gpio *gpio = igc->private;
  153. struct bgpio_chip *bgc = &gpio->ports[0].bgc;
  154. unsigned long flags;
  155. u32 val;
  156. spin_lock_irqsave(&bgc->lock, flags);
  157. val = dwapb_read(gpio, GPIO_INTEN);
  158. val &= ~BIT(d->hwirq);
  159. dwapb_write(gpio, GPIO_INTEN, val);
  160. spin_unlock_irqrestore(&bgc->lock, flags);
  161. }
  162. static int dwapb_irq_reqres(struct irq_data *d)
  163. {
  164. struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
  165. struct dwapb_gpio *gpio = igc->private;
  166. struct bgpio_chip *bgc = &gpio->ports[0].bgc;
  167. if (gpiochip_lock_as_irq(&bgc->gc, irqd_to_hwirq(d))) {
  168. dev_err(gpio->dev, "unable to lock HW IRQ %lu for IRQ\n",
  169. irqd_to_hwirq(d));
  170. return -EINVAL;
  171. }
  172. return 0;
  173. }
  174. static void dwapb_irq_relres(struct irq_data *d)
  175. {
  176. struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
  177. struct dwapb_gpio *gpio = igc->private;
  178. struct bgpio_chip *bgc = &gpio->ports[0].bgc;
  179. gpiochip_unlock_as_irq(&bgc->gc, irqd_to_hwirq(d));
  180. }
  181. static int dwapb_irq_set_type(struct irq_data *d, u32 type)
  182. {
  183. struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
  184. struct dwapb_gpio *gpio = igc->private;
  185. struct bgpio_chip *bgc = &gpio->ports[0].bgc;
  186. int bit = d->hwirq;
  187. unsigned long level, polarity, flags;
  188. if (type & ~(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
  189. IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
  190. return -EINVAL;
  191. spin_lock_irqsave(&bgc->lock, flags);
  192. level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
  193. polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
  194. switch (type) {
  195. case IRQ_TYPE_EDGE_BOTH:
  196. level |= BIT(bit);
  197. dwapb_toggle_trigger(gpio, bit);
  198. break;
  199. case IRQ_TYPE_EDGE_RISING:
  200. level |= BIT(bit);
  201. polarity |= BIT(bit);
  202. break;
  203. case IRQ_TYPE_EDGE_FALLING:
  204. level |= BIT(bit);
  205. polarity &= ~BIT(bit);
  206. break;
  207. case IRQ_TYPE_LEVEL_HIGH:
  208. level &= ~BIT(bit);
  209. polarity |= BIT(bit);
  210. break;
  211. case IRQ_TYPE_LEVEL_LOW:
  212. level &= ~BIT(bit);
  213. polarity &= ~BIT(bit);
  214. break;
  215. }
  216. irq_setup_alt_chip(d, type);
  217. dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
  218. dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
  219. spin_unlock_irqrestore(&bgc->lock, flags);
  220. return 0;
  221. }
  222. static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
  223. unsigned offset, unsigned debounce)
  224. {
  225. struct bgpio_chip *bgc = to_bgpio_chip(gc);
  226. struct dwapb_gpio_port *port = to_dwapb_gpio_port(bgc);
  227. struct dwapb_gpio *gpio = port->gpio;
  228. unsigned long flags, val_deb;
  229. unsigned long mask = bgc->pin2mask(bgc, offset);
  230. spin_lock_irqsave(&bgc->lock, flags);
  231. val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
  232. if (debounce)
  233. dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb | mask);
  234. else
  235. dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb & ~mask);
  236. spin_unlock_irqrestore(&bgc->lock, flags);
  237. return 0;
  238. }
  239. static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
  240. {
  241. u32 worked;
  242. struct dwapb_gpio *gpio = dev_id;
  243. worked = dwapb_do_irq(gpio);
  244. return worked ? IRQ_HANDLED : IRQ_NONE;
  245. }
  246. static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
  247. struct dwapb_gpio_port *port,
  248. struct dwapb_port_property *pp)
  249. {
  250. struct gpio_chip *gc = &port->bgc.gc;
  251. struct device_node *node = pp->node;
  252. struct irq_chip_generic *irq_gc = NULL;
  253. unsigned int hwirq, ngpio = gc->ngpio;
  254. struct irq_chip_type *ct;
  255. int err, i;
  256. gpio->domain = irq_domain_add_linear(node, ngpio,
  257. &irq_generic_chip_ops, gpio);
  258. if (!gpio->domain)
  259. return;
  260. err = irq_alloc_domain_generic_chips(gpio->domain, ngpio, 2,
  261. "gpio-dwapb", handle_level_irq,
  262. IRQ_NOREQUEST, 0,
  263. IRQ_GC_INIT_NESTED_LOCK);
  264. if (err) {
  265. dev_info(gpio->dev, "irq_alloc_domain_generic_chips failed\n");
  266. irq_domain_remove(gpio->domain);
  267. gpio->domain = NULL;
  268. return;
  269. }
  270. irq_gc = irq_get_domain_generic_chip(gpio->domain, 0);
  271. if (!irq_gc) {
  272. irq_domain_remove(gpio->domain);
  273. gpio->domain = NULL;
  274. return;
  275. }
  276. irq_gc->reg_base = gpio->regs;
  277. irq_gc->private = gpio;
  278. for (i = 0; i < 2; i++) {
  279. ct = &irq_gc->chip_types[i];
  280. ct->chip.irq_ack = irq_gc_ack_set_bit;
  281. ct->chip.irq_mask = irq_gc_mask_set_bit;
  282. ct->chip.irq_unmask = irq_gc_mask_clr_bit;
  283. ct->chip.irq_set_type = dwapb_irq_set_type;
  284. ct->chip.irq_enable = dwapb_irq_enable;
  285. ct->chip.irq_disable = dwapb_irq_disable;
  286. ct->chip.irq_request_resources = dwapb_irq_reqres;
  287. ct->chip.irq_release_resources = dwapb_irq_relres;
  288. ct->regs.ack = GPIO_PORTA_EOI;
  289. ct->regs.mask = GPIO_INTMASK;
  290. ct->type = IRQ_TYPE_LEVEL_MASK;
  291. }
  292. irq_gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
  293. irq_gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
  294. irq_gc->chip_types[1].handler = handle_edge_irq;
  295. if (!pp->irq_shared) {
  296. irq_set_chained_handler_and_data(pp->irq, dwapb_irq_handler,
  297. gpio);
  298. } else {
  299. /*
  300. * Request a shared IRQ since where MFD would have devices
  301. * using the same irq pin
  302. */
  303. err = devm_request_irq(gpio->dev, pp->irq,
  304. dwapb_irq_handler_mfd,
  305. IRQF_SHARED, "gpio-dwapb-mfd", gpio);
  306. if (err) {
  307. dev_err(gpio->dev, "error requesting IRQ\n");
  308. irq_domain_remove(gpio->domain);
  309. gpio->domain = NULL;
  310. return;
  311. }
  312. }
  313. for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
  314. irq_create_mapping(gpio->domain, hwirq);
  315. port->bgc.gc.to_irq = dwapb_gpio_to_irq;
  316. }
  317. static void dwapb_irq_teardown(struct dwapb_gpio *gpio)
  318. {
  319. struct dwapb_gpio_port *port = &gpio->ports[0];
  320. struct gpio_chip *gc = &port->bgc.gc;
  321. unsigned int ngpio = gc->ngpio;
  322. irq_hw_number_t hwirq;
  323. if (!gpio->domain)
  324. return;
  325. for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
  326. irq_dispose_mapping(irq_find_mapping(gpio->domain, hwirq));
  327. irq_domain_remove(gpio->domain);
  328. gpio->domain = NULL;
  329. }
  330. static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
  331. struct dwapb_port_property *pp,
  332. unsigned int offs)
  333. {
  334. struct dwapb_gpio_port *port;
  335. void __iomem *dat, *set, *dirout;
  336. int err;
  337. port = &gpio->ports[offs];
  338. port->gpio = gpio;
  339. port->idx = pp->idx;
  340. #ifdef CONFIG_PM_SLEEP
  341. port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);
  342. if (!port->ctx)
  343. return -ENOMEM;
  344. #endif
  345. dat = gpio->regs + GPIO_EXT_PORTA + (pp->idx * GPIO_EXT_PORT_SIZE);
  346. set = gpio->regs + GPIO_SWPORTA_DR + (pp->idx * GPIO_SWPORT_DR_SIZE);
  347. dirout = gpio->regs + GPIO_SWPORTA_DDR +
  348. (pp->idx * GPIO_SWPORT_DDR_SIZE);
  349. err = bgpio_init(&port->bgc, gpio->dev, 4, dat, set, NULL, dirout,
  350. NULL, false);
  351. if (err) {
  352. dev_err(gpio->dev, "failed to init gpio chip for %s\n",
  353. pp->name);
  354. return err;
  355. }
  356. #ifdef CONFIG_OF_GPIO
  357. port->bgc.gc.of_node = pp->node;
  358. #endif
  359. port->bgc.gc.ngpio = pp->ngpio;
  360. port->bgc.gc.base = pp->gpio_base;
  361. /* Only port A support debounce */
  362. if (pp->idx == 0)
  363. port->bgc.gc.set_debounce = dwapb_gpio_set_debounce;
  364. if (pp->irq)
  365. dwapb_configure_irqs(gpio, port, pp);
  366. err = gpiochip_add(&port->bgc.gc);
  367. if (err)
  368. dev_err(gpio->dev, "failed to register gpiochip for %s\n",
  369. pp->name);
  370. else
  371. port->is_registered = true;
  372. return err;
  373. }
  374. static void dwapb_gpio_unregister(struct dwapb_gpio *gpio)
  375. {
  376. unsigned int m;
  377. for (m = 0; m < gpio->nr_ports; ++m)
  378. if (gpio->ports[m].is_registered)
  379. gpiochip_remove(&gpio->ports[m].bgc.gc);
  380. }
  381. static struct dwapb_platform_data *
  382. dwapb_gpio_get_pdata_of(struct device *dev)
  383. {
  384. struct device_node *node, *port_np;
  385. struct dwapb_platform_data *pdata;
  386. struct dwapb_port_property *pp;
  387. int nports;
  388. int i;
  389. node = dev->of_node;
  390. if (!IS_ENABLED(CONFIG_OF_GPIO) || !node)
  391. return ERR_PTR(-ENODEV);
  392. nports = of_get_child_count(node);
  393. if (nports == 0)
  394. return ERR_PTR(-ENODEV);
  395. pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
  396. if (!pdata)
  397. return ERR_PTR(-ENOMEM);
  398. pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL);
  399. if (!pdata->properties)
  400. return ERR_PTR(-ENOMEM);
  401. pdata->nports = nports;
  402. i = 0;
  403. for_each_child_of_node(node, port_np) {
  404. pp = &pdata->properties[i++];
  405. pp->node = port_np;
  406. if (of_property_read_u32(port_np, "reg", &pp->idx) ||
  407. pp->idx >= DWAPB_MAX_PORTS) {
  408. dev_err(dev, "missing/invalid port index for %s\n",
  409. port_np->full_name);
  410. return ERR_PTR(-EINVAL);
  411. }
  412. if (of_property_read_u32(port_np, "snps,nr-gpios",
  413. &pp->ngpio)) {
  414. dev_info(dev, "failed to get number of gpios for %s\n",
  415. port_np->full_name);
  416. pp->ngpio = 32;
  417. }
  418. /*
  419. * Only port A can provide interrupts in all configurations of
  420. * the IP.
  421. */
  422. if (pp->idx == 0 &&
  423. of_property_read_bool(port_np, "interrupt-controller")) {
  424. pp->irq = irq_of_parse_and_map(port_np, 0);
  425. if (!pp->irq) {
  426. dev_warn(dev, "no irq for bank %s\n",
  427. port_np->full_name);
  428. }
  429. }
  430. pp->irq_shared = false;
  431. pp->gpio_base = -1;
  432. pp->name = port_np->full_name;
  433. }
  434. return pdata;
  435. }
  436. static int dwapb_gpio_probe(struct platform_device *pdev)
  437. {
  438. unsigned int i;
  439. struct resource *res;
  440. struct dwapb_gpio *gpio;
  441. int err;
  442. struct device *dev = &pdev->dev;
  443. struct dwapb_platform_data *pdata = dev_get_platdata(dev);
  444. if (!pdata) {
  445. pdata = dwapb_gpio_get_pdata_of(dev);
  446. if (IS_ERR(pdata))
  447. return PTR_ERR(pdata);
  448. }
  449. if (!pdata->nports)
  450. return -ENODEV;
  451. gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
  452. if (!gpio)
  453. return -ENOMEM;
  454. gpio->dev = &pdev->dev;
  455. gpio->nr_ports = pdata->nports;
  456. gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
  457. sizeof(*gpio->ports), GFP_KERNEL);
  458. if (!gpio->ports)
  459. return -ENOMEM;
  460. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  461. gpio->regs = devm_ioremap_resource(&pdev->dev, res);
  462. if (IS_ERR(gpio->regs))
  463. return PTR_ERR(gpio->regs);
  464. for (i = 0; i < gpio->nr_ports; i++) {
  465. err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
  466. if (err)
  467. goto out_unregister;
  468. }
  469. platform_set_drvdata(pdev, gpio);
  470. return 0;
  471. out_unregister:
  472. dwapb_gpio_unregister(gpio);
  473. dwapb_irq_teardown(gpio);
  474. return err;
  475. }
  476. static int dwapb_gpio_remove(struct platform_device *pdev)
  477. {
  478. struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
  479. dwapb_gpio_unregister(gpio);
  480. dwapb_irq_teardown(gpio);
  481. return 0;
  482. }
  483. static const struct of_device_id dwapb_of_match[] = {
  484. { .compatible = "snps,dw-apb-gpio" },
  485. { /* Sentinel */ }
  486. };
  487. MODULE_DEVICE_TABLE(of, dwapb_of_match);
  488. #ifdef CONFIG_PM_SLEEP
  489. static int dwapb_gpio_suspend(struct device *dev)
  490. {
  491. struct platform_device *pdev = to_platform_device(dev);
  492. struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
  493. struct bgpio_chip *bgc = &gpio->ports[0].bgc;
  494. unsigned long flags;
  495. int i;
  496. spin_lock_irqsave(&bgc->lock, flags);
  497. for (i = 0; i < gpio->nr_ports; i++) {
  498. unsigned int offset;
  499. unsigned int idx = gpio->ports[i].idx;
  500. struct dwapb_context *ctx = gpio->ports[i].ctx;
  501. BUG_ON(!ctx);
  502. offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_SIZE;
  503. ctx->dir = dwapb_read(gpio, offset);
  504. offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_SIZE;
  505. ctx->data = dwapb_read(gpio, offset);
  506. offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_SIZE;
  507. ctx->ext = dwapb_read(gpio, offset);
  508. /* Only port A can provide interrupts */
  509. if (idx == 0) {
  510. ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK);
  511. ctx->int_en = dwapb_read(gpio, GPIO_INTEN);
  512. ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
  513. ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
  514. ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
  515. /* Mask out interrupts */
  516. dwapb_write(gpio, GPIO_INTMASK, 0xffffffff);
  517. }
  518. }
  519. spin_unlock_irqrestore(&bgc->lock, flags);
  520. return 0;
  521. }
  522. static int dwapb_gpio_resume(struct device *dev)
  523. {
  524. struct platform_device *pdev = to_platform_device(dev);
  525. struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
  526. struct bgpio_chip *bgc = &gpio->ports[0].bgc;
  527. unsigned long flags;
  528. int i;
  529. spin_lock_irqsave(&bgc->lock, flags);
  530. for (i = 0; i < gpio->nr_ports; i++) {
  531. unsigned int offset;
  532. unsigned int idx = gpio->ports[i].idx;
  533. struct dwapb_context *ctx = gpio->ports[i].ctx;
  534. BUG_ON(!ctx);
  535. offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_SIZE;
  536. dwapb_write(gpio, offset, ctx->data);
  537. offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_SIZE;
  538. dwapb_write(gpio, offset, ctx->dir);
  539. offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_SIZE;
  540. dwapb_write(gpio, offset, ctx->ext);
  541. /* Only port A can provide interrupts */
  542. if (idx == 0) {
  543. dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);
  544. dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);
  545. dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);
  546. dwapb_write(gpio, GPIO_INTEN, ctx->int_en);
  547. dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);
  548. /* Clear out spurious interrupts */
  549. dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
  550. }
  551. }
  552. spin_unlock_irqrestore(&bgc->lock, flags);
  553. return 0;
  554. }
  555. #endif
  556. static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend,
  557. dwapb_gpio_resume);
  558. static struct platform_driver dwapb_gpio_driver = {
  559. .driver = {
  560. .name = "gpio-dwapb",
  561. .pm = &dwapb_gpio_pm_ops,
  562. .of_match_table = of_match_ptr(dwapb_of_match),
  563. },
  564. .probe = dwapb_gpio_probe,
  565. .remove = dwapb_gpio_remove,
  566. };
  567. module_platform_driver(dwapb_gpio_driver);
  568. MODULE_LICENSE("GPL");
  569. MODULE_AUTHOR("Jamie Iles");
  570. MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");