gpio-sx150x.c 16 KB

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  1. /* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. *
  12. * You should have received a copy of the GNU General Public License
  13. * along with this program; if not, write to the Free Software
  14. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  15. * 02110-1301, USA.
  16. */
  17. #include <linux/gpio.h>
  18. #include <linux/i2c.h>
  19. #include <linux/init.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/irq.h>
  22. #include <linux/module.h>
  23. #include <linux/mutex.h>
  24. #include <linux/slab.h>
  25. #include <linux/i2c/sx150x.h>
  26. #include <linux/of.h>
  27. #include <linux/of_address.h>
  28. #include <linux/of_irq.h>
  29. #include <linux/of_gpio.h>
  30. #include <linux/of_device.h>
  31. #define NO_UPDATE_PENDING -1
  32. /* The chip models of sx150x */
  33. #define SX150X_456 0
  34. #define SX150X_789 1
  35. struct sx150x_456_pri {
  36. u8 reg_pld_mode;
  37. u8 reg_pld_table0;
  38. u8 reg_pld_table1;
  39. u8 reg_pld_table2;
  40. u8 reg_pld_table3;
  41. u8 reg_pld_table4;
  42. u8 reg_advance;
  43. };
  44. struct sx150x_789_pri {
  45. u8 reg_drain;
  46. u8 reg_polarity;
  47. u8 reg_clock;
  48. u8 reg_misc;
  49. u8 reg_reset;
  50. u8 ngpios;
  51. };
  52. struct sx150x_device_data {
  53. u8 model;
  54. u8 reg_pullup;
  55. u8 reg_pulldn;
  56. u8 reg_dir;
  57. u8 reg_data;
  58. u8 reg_irq_mask;
  59. u8 reg_irq_src;
  60. u8 reg_sense;
  61. u8 ngpios;
  62. union {
  63. struct sx150x_456_pri x456;
  64. struct sx150x_789_pri x789;
  65. } pri;
  66. };
  67. struct sx150x_chip {
  68. struct gpio_chip gpio_chip;
  69. struct i2c_client *client;
  70. const struct sx150x_device_data *dev_cfg;
  71. int irq_summary;
  72. int irq_base;
  73. int irq_update;
  74. u32 irq_sense;
  75. u32 irq_masked;
  76. u32 dev_sense;
  77. u32 dev_masked;
  78. struct irq_chip irq_chip;
  79. struct mutex lock;
  80. };
  81. static const struct sx150x_device_data sx150x_devices[] = {
  82. [0] = { /* sx1508q */
  83. .model = SX150X_789,
  84. .reg_pullup = 0x03,
  85. .reg_pulldn = 0x04,
  86. .reg_dir = 0x07,
  87. .reg_data = 0x08,
  88. .reg_irq_mask = 0x09,
  89. .reg_irq_src = 0x0c,
  90. .reg_sense = 0x0b,
  91. .pri.x789 = {
  92. .reg_drain = 0x05,
  93. .reg_polarity = 0x06,
  94. .reg_clock = 0x0f,
  95. .reg_misc = 0x10,
  96. .reg_reset = 0x7d,
  97. },
  98. .ngpios = 8,
  99. },
  100. [1] = { /* sx1509q */
  101. .model = SX150X_789,
  102. .reg_pullup = 0x07,
  103. .reg_pulldn = 0x09,
  104. .reg_dir = 0x0f,
  105. .reg_data = 0x11,
  106. .reg_irq_mask = 0x13,
  107. .reg_irq_src = 0x19,
  108. .reg_sense = 0x17,
  109. .pri.x789 = {
  110. .reg_drain = 0x0b,
  111. .reg_polarity = 0x0d,
  112. .reg_clock = 0x1e,
  113. .reg_misc = 0x1f,
  114. .reg_reset = 0x7d,
  115. },
  116. .ngpios = 16
  117. },
  118. [2] = { /* sx1506q */
  119. .model = SX150X_456,
  120. .reg_pullup = 0x05,
  121. .reg_pulldn = 0x07,
  122. .reg_dir = 0x03,
  123. .reg_data = 0x01,
  124. .reg_irq_mask = 0x09,
  125. .reg_irq_src = 0x0f,
  126. .reg_sense = 0x0d,
  127. .pri.x456 = {
  128. .reg_pld_mode = 0x21,
  129. .reg_pld_table0 = 0x23,
  130. .reg_pld_table1 = 0x25,
  131. .reg_pld_table2 = 0x27,
  132. .reg_pld_table3 = 0x29,
  133. .reg_pld_table4 = 0x2b,
  134. .reg_advance = 0xad,
  135. },
  136. .ngpios = 16
  137. },
  138. };
  139. static const struct i2c_device_id sx150x_id[] = {
  140. {"sx1508q", 0},
  141. {"sx1509q", 1},
  142. {"sx1506q", 2},
  143. {}
  144. };
  145. MODULE_DEVICE_TABLE(i2c, sx150x_id);
  146. static const struct of_device_id sx150x_of_match[] = {
  147. { .compatible = "semtech,sx1508q" },
  148. { .compatible = "semtech,sx1509q" },
  149. { .compatible = "semtech,sx1506q" },
  150. {},
  151. };
  152. MODULE_DEVICE_TABLE(of, sx150x_of_match);
  153. struct sx150x_chip *to_sx150x(struct gpio_chip *gc)
  154. {
  155. return container_of(gc, struct sx150x_chip, gpio_chip);
  156. }
  157. static s32 sx150x_i2c_write(struct i2c_client *client, u8 reg, u8 val)
  158. {
  159. s32 err = i2c_smbus_write_byte_data(client, reg, val);
  160. if (err < 0)
  161. dev_warn(&client->dev,
  162. "i2c write fail: can't write %02x to %02x: %d\n",
  163. val, reg, err);
  164. return err;
  165. }
  166. static s32 sx150x_i2c_read(struct i2c_client *client, u8 reg, u8 *val)
  167. {
  168. s32 err = i2c_smbus_read_byte_data(client, reg);
  169. if (err >= 0)
  170. *val = err;
  171. else
  172. dev_warn(&client->dev,
  173. "i2c read fail: can't read from %02x: %d\n",
  174. reg, err);
  175. return err;
  176. }
  177. static inline bool offset_is_oscio(struct sx150x_chip *chip, unsigned offset)
  178. {
  179. return (chip->dev_cfg->ngpios == offset);
  180. }
  181. /*
  182. * These utility functions solve the common problem of locating and setting
  183. * configuration bits. Configuration bits are grouped into registers
  184. * whose indexes increase downwards. For example, with eight-bit registers,
  185. * sixteen gpios would have their config bits grouped in the following order:
  186. * REGISTER N-1 [ f e d c b a 9 8 ]
  187. * N [ 7 6 5 4 3 2 1 0 ]
  188. *
  189. * For multi-bit configurations, the pattern gets wider:
  190. * REGISTER N-3 [ f f e e d d c c ]
  191. * N-2 [ b b a a 9 9 8 8 ]
  192. * N-1 [ 7 7 6 6 5 5 4 4 ]
  193. * N [ 3 3 2 2 1 1 0 0 ]
  194. *
  195. * Given the address of the starting register 'N', the index of the gpio
  196. * whose configuration we seek to change, and the width in bits of that
  197. * configuration, these functions allow us to locate the correct
  198. * register and mask the correct bits.
  199. */
  200. static inline void sx150x_find_cfg(u8 offset, u8 width,
  201. u8 *reg, u8 *mask, u8 *shift)
  202. {
  203. *reg -= offset * width / 8;
  204. *mask = (1 << width) - 1;
  205. *shift = (offset * width) % 8;
  206. *mask <<= *shift;
  207. }
  208. static s32 sx150x_write_cfg(struct sx150x_chip *chip,
  209. u8 offset, u8 width, u8 reg, u8 val)
  210. {
  211. u8 mask;
  212. u8 data;
  213. u8 shift;
  214. s32 err;
  215. sx150x_find_cfg(offset, width, &reg, &mask, &shift);
  216. err = sx150x_i2c_read(chip->client, reg, &data);
  217. if (err < 0)
  218. return err;
  219. data &= ~mask;
  220. data |= (val << shift) & mask;
  221. return sx150x_i2c_write(chip->client, reg, data);
  222. }
  223. static int sx150x_get_io(struct sx150x_chip *chip, unsigned offset)
  224. {
  225. u8 reg = chip->dev_cfg->reg_data;
  226. u8 mask;
  227. u8 data;
  228. u8 shift;
  229. s32 err;
  230. sx150x_find_cfg(offset, 1, &reg, &mask, &shift);
  231. err = sx150x_i2c_read(chip->client, reg, &data);
  232. if (err >= 0)
  233. err = (data & mask) != 0 ? 1 : 0;
  234. return err;
  235. }
  236. static void sx150x_set_oscio(struct sx150x_chip *chip, int val)
  237. {
  238. sx150x_i2c_write(chip->client,
  239. chip->dev_cfg->pri.x789.reg_clock,
  240. (val ? 0x1f : 0x10));
  241. }
  242. static void sx150x_set_io(struct sx150x_chip *chip, unsigned offset, int val)
  243. {
  244. sx150x_write_cfg(chip,
  245. offset,
  246. 1,
  247. chip->dev_cfg->reg_data,
  248. (val ? 1 : 0));
  249. }
  250. static int sx150x_io_input(struct sx150x_chip *chip, unsigned offset)
  251. {
  252. return sx150x_write_cfg(chip,
  253. offset,
  254. 1,
  255. chip->dev_cfg->reg_dir,
  256. 1);
  257. }
  258. static int sx150x_io_output(struct sx150x_chip *chip, unsigned offset, int val)
  259. {
  260. int err;
  261. err = sx150x_write_cfg(chip,
  262. offset,
  263. 1,
  264. chip->dev_cfg->reg_data,
  265. (val ? 1 : 0));
  266. if (err >= 0)
  267. err = sx150x_write_cfg(chip,
  268. offset,
  269. 1,
  270. chip->dev_cfg->reg_dir,
  271. 0);
  272. return err;
  273. }
  274. static int sx150x_gpio_get(struct gpio_chip *gc, unsigned offset)
  275. {
  276. struct sx150x_chip *chip = to_sx150x(gc);
  277. int status = -EINVAL;
  278. if (!offset_is_oscio(chip, offset)) {
  279. mutex_lock(&chip->lock);
  280. status = sx150x_get_io(chip, offset);
  281. mutex_unlock(&chip->lock);
  282. }
  283. return status;
  284. }
  285. static void sx150x_gpio_set(struct gpio_chip *gc, unsigned offset, int val)
  286. {
  287. struct sx150x_chip *chip = to_sx150x(gc);
  288. mutex_lock(&chip->lock);
  289. if (offset_is_oscio(chip, offset))
  290. sx150x_set_oscio(chip, val);
  291. else
  292. sx150x_set_io(chip, offset, val);
  293. mutex_unlock(&chip->lock);
  294. }
  295. static int sx150x_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
  296. {
  297. struct sx150x_chip *chip = to_sx150x(gc);
  298. int status = -EINVAL;
  299. if (!offset_is_oscio(chip, offset)) {
  300. mutex_lock(&chip->lock);
  301. status = sx150x_io_input(chip, offset);
  302. mutex_unlock(&chip->lock);
  303. }
  304. return status;
  305. }
  306. static int sx150x_gpio_direction_output(struct gpio_chip *gc,
  307. unsigned offset,
  308. int val)
  309. {
  310. struct sx150x_chip *chip = to_sx150x(gc);
  311. int status = 0;
  312. if (!offset_is_oscio(chip, offset)) {
  313. mutex_lock(&chip->lock);
  314. status = sx150x_io_output(chip, offset, val);
  315. mutex_unlock(&chip->lock);
  316. }
  317. return status;
  318. }
  319. static void sx150x_irq_mask(struct irq_data *d)
  320. {
  321. struct sx150x_chip *chip = to_sx150x(irq_data_get_irq_chip_data(d));
  322. unsigned n = d->hwirq;
  323. chip->irq_masked |= (1 << n);
  324. chip->irq_update = n;
  325. }
  326. static void sx150x_irq_unmask(struct irq_data *d)
  327. {
  328. struct sx150x_chip *chip = to_sx150x(irq_data_get_irq_chip_data(d));
  329. unsigned n = d->hwirq;
  330. chip->irq_masked &= ~(1 << n);
  331. chip->irq_update = n;
  332. }
  333. static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type)
  334. {
  335. struct sx150x_chip *chip = to_sx150x(irq_data_get_irq_chip_data(d));
  336. unsigned n, val = 0;
  337. if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
  338. return -EINVAL;
  339. n = d->hwirq;
  340. if (flow_type & IRQ_TYPE_EDGE_RISING)
  341. val |= 0x1;
  342. if (flow_type & IRQ_TYPE_EDGE_FALLING)
  343. val |= 0x2;
  344. chip->irq_sense &= ~(3UL << (n * 2));
  345. chip->irq_sense |= val << (n * 2);
  346. chip->irq_update = n;
  347. return 0;
  348. }
  349. static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id)
  350. {
  351. struct sx150x_chip *chip = (struct sx150x_chip *)dev_id;
  352. unsigned nhandled = 0;
  353. unsigned sub_irq;
  354. unsigned n;
  355. s32 err;
  356. u8 val;
  357. int i;
  358. for (i = (chip->dev_cfg->ngpios / 8) - 1; i >= 0; --i) {
  359. err = sx150x_i2c_read(chip->client,
  360. chip->dev_cfg->reg_irq_src - i,
  361. &val);
  362. if (err < 0)
  363. continue;
  364. sx150x_i2c_write(chip->client,
  365. chip->dev_cfg->reg_irq_src - i,
  366. val);
  367. for (n = 0; n < 8; ++n) {
  368. if (val & (1 << n)) {
  369. sub_irq = irq_find_mapping(
  370. chip->gpio_chip.irqdomain,
  371. (i * 8) + n);
  372. handle_nested_irq(sub_irq);
  373. ++nhandled;
  374. }
  375. }
  376. }
  377. return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
  378. }
  379. static void sx150x_irq_bus_lock(struct irq_data *d)
  380. {
  381. struct sx150x_chip *chip = to_sx150x(irq_data_get_irq_chip_data(d));
  382. mutex_lock(&chip->lock);
  383. }
  384. static void sx150x_irq_bus_sync_unlock(struct irq_data *d)
  385. {
  386. struct sx150x_chip *chip = to_sx150x(irq_data_get_irq_chip_data(d));
  387. unsigned n;
  388. if (chip->irq_update == NO_UPDATE_PENDING)
  389. goto out;
  390. n = chip->irq_update;
  391. chip->irq_update = NO_UPDATE_PENDING;
  392. /* Avoid updates if nothing changed */
  393. if (chip->dev_sense == chip->irq_sense &&
  394. chip->dev_masked == chip->irq_masked)
  395. goto out;
  396. chip->dev_sense = chip->irq_sense;
  397. chip->dev_masked = chip->irq_masked;
  398. if (chip->irq_masked & (1 << n)) {
  399. sx150x_write_cfg(chip, n, 1, chip->dev_cfg->reg_irq_mask, 1);
  400. sx150x_write_cfg(chip, n, 2, chip->dev_cfg->reg_sense, 0);
  401. } else {
  402. sx150x_write_cfg(chip, n, 1, chip->dev_cfg->reg_irq_mask, 0);
  403. sx150x_write_cfg(chip, n, 2, chip->dev_cfg->reg_sense,
  404. chip->irq_sense >> (n * 2));
  405. }
  406. out:
  407. mutex_unlock(&chip->lock);
  408. }
  409. static void sx150x_init_chip(struct sx150x_chip *chip,
  410. struct i2c_client *client,
  411. kernel_ulong_t driver_data,
  412. struct sx150x_platform_data *pdata)
  413. {
  414. mutex_init(&chip->lock);
  415. chip->client = client;
  416. chip->dev_cfg = &sx150x_devices[driver_data];
  417. chip->gpio_chip.dev = &client->dev;
  418. chip->gpio_chip.label = client->name;
  419. chip->gpio_chip.direction_input = sx150x_gpio_direction_input;
  420. chip->gpio_chip.direction_output = sx150x_gpio_direction_output;
  421. chip->gpio_chip.get = sx150x_gpio_get;
  422. chip->gpio_chip.set = sx150x_gpio_set;
  423. chip->gpio_chip.base = pdata->gpio_base;
  424. chip->gpio_chip.can_sleep = true;
  425. chip->gpio_chip.ngpio = chip->dev_cfg->ngpios;
  426. #ifdef CONFIG_OF_GPIO
  427. chip->gpio_chip.of_node = client->dev.of_node;
  428. chip->gpio_chip.of_gpio_n_cells = 2;
  429. #endif
  430. if (pdata->oscio_is_gpo)
  431. ++chip->gpio_chip.ngpio;
  432. chip->irq_chip.name = client->name;
  433. chip->irq_chip.irq_mask = sx150x_irq_mask;
  434. chip->irq_chip.irq_unmask = sx150x_irq_unmask;
  435. chip->irq_chip.irq_set_type = sx150x_irq_set_type;
  436. chip->irq_chip.irq_bus_lock = sx150x_irq_bus_lock;
  437. chip->irq_chip.irq_bus_sync_unlock = sx150x_irq_bus_sync_unlock;
  438. chip->irq_summary = -1;
  439. chip->irq_base = -1;
  440. chip->irq_masked = ~0;
  441. chip->irq_sense = 0;
  442. chip->dev_masked = ~0;
  443. chip->dev_sense = 0;
  444. chip->irq_update = NO_UPDATE_PENDING;
  445. }
  446. static int sx150x_init_io(struct sx150x_chip *chip, u8 base, u16 cfg)
  447. {
  448. int err = 0;
  449. unsigned n;
  450. for (n = 0; err >= 0 && n < (chip->dev_cfg->ngpios / 8); ++n)
  451. err = sx150x_i2c_write(chip->client, base - n, cfg >> (n * 8));
  452. return err;
  453. }
  454. static int sx150x_reset(struct sx150x_chip *chip)
  455. {
  456. int err;
  457. err = i2c_smbus_write_byte_data(chip->client,
  458. chip->dev_cfg->pri.x789.reg_reset,
  459. 0x12);
  460. if (err < 0)
  461. return err;
  462. err = i2c_smbus_write_byte_data(chip->client,
  463. chip->dev_cfg->pri.x789.reg_reset,
  464. 0x34);
  465. return err;
  466. }
  467. static int sx150x_init_hw(struct sx150x_chip *chip,
  468. struct sx150x_platform_data *pdata)
  469. {
  470. int err = 0;
  471. if (pdata->reset_during_probe) {
  472. err = sx150x_reset(chip);
  473. if (err < 0)
  474. return err;
  475. }
  476. if (chip->dev_cfg->model == SX150X_789)
  477. err = sx150x_i2c_write(chip->client,
  478. chip->dev_cfg->pri.x789.reg_misc,
  479. 0x01);
  480. else
  481. err = sx150x_i2c_write(chip->client,
  482. chip->dev_cfg->pri.x456.reg_advance,
  483. 0x04);
  484. if (err < 0)
  485. return err;
  486. err = sx150x_init_io(chip, chip->dev_cfg->reg_pullup,
  487. pdata->io_pullup_ena);
  488. if (err < 0)
  489. return err;
  490. err = sx150x_init_io(chip, chip->dev_cfg->reg_pulldn,
  491. pdata->io_pulldn_ena);
  492. if (err < 0)
  493. return err;
  494. if (chip->dev_cfg->model == SX150X_789) {
  495. err = sx150x_init_io(chip,
  496. chip->dev_cfg->pri.x789.reg_drain,
  497. pdata->io_open_drain_ena);
  498. if (err < 0)
  499. return err;
  500. err = sx150x_init_io(chip,
  501. chip->dev_cfg->pri.x789.reg_polarity,
  502. pdata->io_polarity);
  503. if (err < 0)
  504. return err;
  505. } else {
  506. /* Set all pins to work in normal mode */
  507. err = sx150x_init_io(chip,
  508. chip->dev_cfg->pri.x456.reg_pld_mode,
  509. 0);
  510. if (err < 0)
  511. return err;
  512. }
  513. if (pdata->oscio_is_gpo)
  514. sx150x_set_oscio(chip, 0);
  515. return err;
  516. }
  517. static int sx150x_install_irq_chip(struct sx150x_chip *chip,
  518. int irq_summary,
  519. int irq_base)
  520. {
  521. int err;
  522. chip->irq_summary = irq_summary;
  523. chip->irq_base = irq_base;
  524. /* Add gpio chip to irq subsystem */
  525. err = gpiochip_irqchip_add(&chip->gpio_chip,
  526. &chip->irq_chip, chip->irq_base,
  527. handle_edge_irq, IRQ_TYPE_EDGE_BOTH);
  528. if (err) {
  529. dev_err(&chip->client->dev,
  530. "could not connect irqchip to gpiochip\n");
  531. return err;
  532. }
  533. err = devm_request_threaded_irq(&chip->client->dev,
  534. irq_summary, NULL, sx150x_irq_thread_fn,
  535. IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_FALLING,
  536. chip->irq_chip.name, chip);
  537. if (err < 0) {
  538. chip->irq_summary = -1;
  539. chip->irq_base = -1;
  540. }
  541. return err;
  542. }
  543. static int sx150x_probe(struct i2c_client *client,
  544. const struct i2c_device_id *id)
  545. {
  546. static const u32 i2c_funcs = I2C_FUNC_SMBUS_BYTE_DATA |
  547. I2C_FUNC_SMBUS_WRITE_WORD_DATA;
  548. struct sx150x_platform_data *pdata;
  549. struct sx150x_chip *chip;
  550. int rc;
  551. pdata = dev_get_platdata(&client->dev);
  552. if (!pdata)
  553. return -EINVAL;
  554. if (!i2c_check_functionality(client->adapter, i2c_funcs))
  555. return -ENOSYS;
  556. chip = devm_kzalloc(&client->dev,
  557. sizeof(struct sx150x_chip), GFP_KERNEL);
  558. if (!chip)
  559. return -ENOMEM;
  560. sx150x_init_chip(chip, client, id->driver_data, pdata);
  561. rc = sx150x_init_hw(chip, pdata);
  562. if (rc < 0)
  563. return rc;
  564. rc = gpiochip_add(&chip->gpio_chip);
  565. if (rc)
  566. return rc;
  567. if (pdata->irq_summary >= 0) {
  568. rc = sx150x_install_irq_chip(chip,
  569. pdata->irq_summary,
  570. pdata->irq_base);
  571. if (rc < 0)
  572. goto probe_fail_post_gpiochip_add;
  573. }
  574. i2c_set_clientdata(client, chip);
  575. return 0;
  576. probe_fail_post_gpiochip_add:
  577. gpiochip_remove(&chip->gpio_chip);
  578. return rc;
  579. }
  580. static int sx150x_remove(struct i2c_client *client)
  581. {
  582. struct sx150x_chip *chip;
  583. chip = i2c_get_clientdata(client);
  584. gpiochip_remove(&chip->gpio_chip);
  585. return 0;
  586. }
  587. static struct i2c_driver sx150x_driver = {
  588. .driver = {
  589. .name = "sx150x",
  590. .owner = THIS_MODULE,
  591. .of_match_table = of_match_ptr(sx150x_of_match),
  592. },
  593. .probe = sx150x_probe,
  594. .remove = sx150x_remove,
  595. .id_table = sx150x_id,
  596. };
  597. static int __init sx150x_init(void)
  598. {
  599. return i2c_add_driver(&sx150x_driver);
  600. }
  601. subsys_initcall(sx150x_init);
  602. static void __exit sx150x_exit(void)
  603. {
  604. return i2c_del_driver(&sx150x_driver);
  605. }
  606. module_exit(sx150x_exit);
  607. MODULE_AUTHOR("Gregory Bean <gbean@codeaurora.org>");
  608. MODULE_DESCRIPTION("Driver for Semtech SX150X I2C GPIO Expanders");
  609. MODULE_LICENSE("GPL v2");