gpio-xgene.c 6.2 KB

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  1. /*
  2. * AppliedMicro X-Gene SoC GPIO Driver
  3. *
  4. * Copyright (c) 2014, Applied Micro Circuits Corporation
  5. * Author: Feng Kan <fkan@apm.com>.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include <linux/module.h>
  20. #include <linux/kernel.h>
  21. #include <linux/init.h>
  22. #include <linux/io.h>
  23. #include <linux/spinlock.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/gpio/driver.h>
  26. #include <linux/types.h>
  27. #include <linux/bitops.h>
  28. #define GPIO_SET_DR_OFFSET 0x0C
  29. #define GPIO_DATA_OFFSET 0x14
  30. #define GPIO_BANK_STRIDE 0x0C
  31. #define XGENE_GPIOS_PER_BANK 16
  32. #define XGENE_MAX_GPIO_BANKS 3
  33. #define XGENE_MAX_GPIOS (XGENE_GPIOS_PER_BANK * XGENE_MAX_GPIO_BANKS)
  34. #define GPIO_BIT_OFFSET(x) (x % XGENE_GPIOS_PER_BANK)
  35. #define GPIO_BANK_OFFSET(x) ((x / XGENE_GPIOS_PER_BANK) * GPIO_BANK_STRIDE)
  36. struct xgene_gpio {
  37. struct gpio_chip chip;
  38. void __iomem *base;
  39. spinlock_t lock;
  40. u32 set_dr_val[XGENE_MAX_GPIO_BANKS];
  41. };
  42. static inline struct xgene_gpio *to_xgene_gpio(struct gpio_chip *chip)
  43. {
  44. return container_of(chip, struct xgene_gpio, chip);
  45. }
  46. static int xgene_gpio_get(struct gpio_chip *gc, unsigned int offset)
  47. {
  48. struct xgene_gpio *chip = to_xgene_gpio(gc);
  49. unsigned long bank_offset;
  50. u32 bit_offset;
  51. bank_offset = GPIO_DATA_OFFSET + GPIO_BANK_OFFSET(offset);
  52. bit_offset = GPIO_BIT_OFFSET(offset);
  53. return !!(ioread32(chip->base + bank_offset) & BIT(bit_offset));
  54. }
  55. static void __xgene_gpio_set(struct gpio_chip *gc, unsigned int offset, int val)
  56. {
  57. struct xgene_gpio *chip = to_xgene_gpio(gc);
  58. unsigned long bank_offset;
  59. u32 setval, bit_offset;
  60. bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
  61. bit_offset = GPIO_BIT_OFFSET(offset) + XGENE_GPIOS_PER_BANK;
  62. setval = ioread32(chip->base + bank_offset);
  63. if (val)
  64. setval |= BIT(bit_offset);
  65. else
  66. setval &= ~BIT(bit_offset);
  67. iowrite32(setval, chip->base + bank_offset);
  68. }
  69. static void xgene_gpio_set(struct gpio_chip *gc, unsigned int offset, int val)
  70. {
  71. struct xgene_gpio *chip = to_xgene_gpio(gc);
  72. unsigned long flags;
  73. spin_lock_irqsave(&chip->lock, flags);
  74. __xgene_gpio_set(gc, offset, val);
  75. spin_unlock_irqrestore(&chip->lock, flags);
  76. }
  77. static int xgene_gpio_dir_in(struct gpio_chip *gc, unsigned int offset)
  78. {
  79. struct xgene_gpio *chip = to_xgene_gpio(gc);
  80. unsigned long flags, bank_offset;
  81. u32 dirval, bit_offset;
  82. bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
  83. bit_offset = GPIO_BIT_OFFSET(offset);
  84. spin_lock_irqsave(&chip->lock, flags);
  85. dirval = ioread32(chip->base + bank_offset);
  86. dirval |= BIT(bit_offset);
  87. iowrite32(dirval, chip->base + bank_offset);
  88. spin_unlock_irqrestore(&chip->lock, flags);
  89. return 0;
  90. }
  91. static int xgene_gpio_dir_out(struct gpio_chip *gc,
  92. unsigned int offset, int val)
  93. {
  94. struct xgene_gpio *chip = to_xgene_gpio(gc);
  95. unsigned long flags, bank_offset;
  96. u32 dirval, bit_offset;
  97. bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
  98. bit_offset = GPIO_BIT_OFFSET(offset);
  99. spin_lock_irqsave(&chip->lock, flags);
  100. dirval = ioread32(chip->base + bank_offset);
  101. dirval &= ~BIT(bit_offset);
  102. iowrite32(dirval, chip->base + bank_offset);
  103. __xgene_gpio_set(gc, offset, val);
  104. spin_unlock_irqrestore(&chip->lock, flags);
  105. return 0;
  106. }
  107. static __maybe_unused int xgene_gpio_suspend(struct device *dev)
  108. {
  109. struct xgene_gpio *gpio = dev_get_drvdata(dev);
  110. unsigned long bank_offset;
  111. unsigned int bank;
  112. for (bank = 0; bank < XGENE_MAX_GPIO_BANKS; bank++) {
  113. bank_offset = GPIO_SET_DR_OFFSET + bank * GPIO_BANK_STRIDE;
  114. gpio->set_dr_val[bank] = ioread32(gpio->base + bank_offset);
  115. }
  116. return 0;
  117. }
  118. static __maybe_unused int xgene_gpio_resume(struct device *dev)
  119. {
  120. struct xgene_gpio *gpio = dev_get_drvdata(dev);
  121. unsigned long bank_offset;
  122. unsigned int bank;
  123. for (bank = 0; bank < XGENE_MAX_GPIO_BANKS; bank++) {
  124. bank_offset = GPIO_SET_DR_OFFSET + bank * GPIO_BANK_STRIDE;
  125. iowrite32(gpio->set_dr_val[bank], gpio->base + bank_offset);
  126. }
  127. return 0;
  128. }
  129. static SIMPLE_DEV_PM_OPS(xgene_gpio_pm, xgene_gpio_suspend, xgene_gpio_resume);
  130. static int xgene_gpio_probe(struct platform_device *pdev)
  131. {
  132. struct resource *res;
  133. struct xgene_gpio *gpio;
  134. int err = 0;
  135. gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
  136. if (!gpio) {
  137. err = -ENOMEM;
  138. goto err;
  139. }
  140. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  141. gpio->base = devm_ioremap_nocache(&pdev->dev, res->start,
  142. resource_size(res));
  143. if (!gpio->base) {
  144. err = -ENOMEM;
  145. goto err;
  146. }
  147. gpio->chip.ngpio = XGENE_MAX_GPIOS;
  148. spin_lock_init(&gpio->lock);
  149. gpio->chip.dev = &pdev->dev;
  150. gpio->chip.direction_input = xgene_gpio_dir_in;
  151. gpio->chip.direction_output = xgene_gpio_dir_out;
  152. gpio->chip.get = xgene_gpio_get;
  153. gpio->chip.set = xgene_gpio_set;
  154. gpio->chip.label = dev_name(&pdev->dev);
  155. gpio->chip.base = -1;
  156. platform_set_drvdata(pdev, gpio);
  157. err = gpiochip_add(&gpio->chip);
  158. if (err) {
  159. dev_err(&pdev->dev,
  160. "failed to register gpiochip.\n");
  161. goto err;
  162. }
  163. dev_info(&pdev->dev, "X-Gene GPIO driver registered.\n");
  164. return 0;
  165. err:
  166. dev_err(&pdev->dev, "X-Gene GPIO driver registration failed.\n");
  167. return err;
  168. }
  169. static int xgene_gpio_remove(struct platform_device *pdev)
  170. {
  171. struct xgene_gpio *gpio = platform_get_drvdata(pdev);
  172. gpiochip_remove(&gpio->chip);
  173. return 0;
  174. }
  175. static const struct of_device_id xgene_gpio_of_match[] = {
  176. { .compatible = "apm,xgene-gpio", },
  177. {},
  178. };
  179. MODULE_DEVICE_TABLE(of, xgene_gpio_of_match);
  180. static struct platform_driver xgene_gpio_driver = {
  181. .driver = {
  182. .name = "xgene-gpio",
  183. .of_match_table = xgene_gpio_of_match,
  184. .pm = &xgene_gpio_pm,
  185. },
  186. .probe = xgene_gpio_probe,
  187. .remove = xgene_gpio_remove,
  188. };
  189. module_platform_driver(xgene_gpio_driver);
  190. MODULE_AUTHOR("Feng Kan <fkan@apm.com>");
  191. MODULE_DESCRIPTION("APM X-Gene GPIO driver");
  192. MODULE_LICENSE("GPL");