amdgpu_object.h 6.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204
  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #ifndef __AMDGPU_OBJECT_H__
  29. #define __AMDGPU_OBJECT_H__
  30. #include <drm/amdgpu_drm.h>
  31. #include "amdgpu.h"
  32. /**
  33. * amdgpu_mem_type_to_domain - return domain corresponding to mem_type
  34. * @mem_type: ttm memory type
  35. *
  36. * Returns corresponding domain of the ttm mem_type
  37. */
  38. static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type)
  39. {
  40. switch (mem_type) {
  41. case TTM_PL_VRAM:
  42. return AMDGPU_GEM_DOMAIN_VRAM;
  43. case TTM_PL_TT:
  44. return AMDGPU_GEM_DOMAIN_GTT;
  45. case TTM_PL_SYSTEM:
  46. return AMDGPU_GEM_DOMAIN_CPU;
  47. case AMDGPU_PL_GDS:
  48. return AMDGPU_GEM_DOMAIN_GDS;
  49. case AMDGPU_PL_GWS:
  50. return AMDGPU_GEM_DOMAIN_GWS;
  51. case AMDGPU_PL_OA:
  52. return AMDGPU_GEM_DOMAIN_OA;
  53. default:
  54. break;
  55. }
  56. return 0;
  57. }
  58. /**
  59. * amdgpu_bo_reserve - reserve bo
  60. * @bo: bo structure
  61. * @no_intr: don't return -ERESTARTSYS on pending signal
  62. *
  63. * Returns:
  64. * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
  65. * a signal. Release all buffer reservations and return to user-space.
  66. */
  67. static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr)
  68. {
  69. int r;
  70. r = ttm_bo_reserve(&bo->tbo, !no_intr, false, false, 0);
  71. if (unlikely(r != 0)) {
  72. if (r != -ERESTARTSYS)
  73. dev_err(bo->adev->dev, "%p reserve failed\n", bo);
  74. return r;
  75. }
  76. return 0;
  77. }
  78. static inline void amdgpu_bo_unreserve(struct amdgpu_bo *bo)
  79. {
  80. ttm_bo_unreserve(&bo->tbo);
  81. }
  82. /**
  83. * amdgpu_bo_gpu_offset - return GPU offset of bo
  84. * @bo: amdgpu object for which we query the offset
  85. *
  86. * Returns current GPU offset of the object.
  87. *
  88. * Note: object should either be pinned or reserved when calling this
  89. * function, it might be useful to add check for this for debugging.
  90. */
  91. static inline u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
  92. {
  93. return bo->tbo.offset;
  94. }
  95. static inline unsigned long amdgpu_bo_size(struct amdgpu_bo *bo)
  96. {
  97. return bo->tbo.num_pages << PAGE_SHIFT;
  98. }
  99. static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo)
  100. {
  101. return (bo->tbo.num_pages << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
  102. }
  103. static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo)
  104. {
  105. return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
  106. }
  107. /**
  108. * amdgpu_bo_mmap_offset - return mmap offset of bo
  109. * @bo: amdgpu object for which we query the offset
  110. *
  111. * Returns mmap offset of the object.
  112. */
  113. static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo)
  114. {
  115. return drm_vma_node_offset_addr(&bo->tbo.vma_node);
  116. }
  117. int amdgpu_bo_create(struct amdgpu_device *adev,
  118. unsigned long size, int byte_align,
  119. bool kernel, u32 domain, u64 flags,
  120. struct sg_table *sg,
  121. struct reservation_object *resv,
  122. struct amdgpu_bo **bo_ptr);
  123. int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
  124. unsigned long size, int byte_align,
  125. bool kernel, u32 domain, u64 flags,
  126. struct sg_table *sg,
  127. struct ttm_placement *placement,
  128. struct reservation_object *resv,
  129. struct amdgpu_bo **bo_ptr);
  130. int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr);
  131. void amdgpu_bo_kunmap(struct amdgpu_bo *bo);
  132. struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo);
  133. void amdgpu_bo_unref(struct amdgpu_bo **bo);
  134. int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr);
  135. int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
  136. u64 min_offset, u64 max_offset,
  137. u64 *gpu_addr);
  138. int amdgpu_bo_unpin(struct amdgpu_bo *bo);
  139. int amdgpu_bo_evict_vram(struct amdgpu_device *adev);
  140. void amdgpu_bo_force_delete(struct amdgpu_device *adev);
  141. int amdgpu_bo_init(struct amdgpu_device *adev);
  142. void amdgpu_bo_fini(struct amdgpu_device *adev);
  143. int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
  144. struct vm_area_struct *vma);
  145. int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);
  146. void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);
  147. int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
  148. uint32_t metadata_size, uint64_t flags);
  149. int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
  150. size_t buffer_size, uint32_t *metadata_size,
  151. uint64_t *flags);
  152. void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
  153. struct ttm_mem_reg *new_mem);
  154. int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
  155. void amdgpu_bo_fence(struct amdgpu_bo *bo, struct fence *fence,
  156. bool shared);
  157. /*
  158. * sub allocation
  159. */
  160. static inline uint64_t amdgpu_sa_bo_gpu_addr(struct amdgpu_sa_bo *sa_bo)
  161. {
  162. return sa_bo->manager->gpu_addr + sa_bo->soffset;
  163. }
  164. static inline void * amdgpu_sa_bo_cpu_addr(struct amdgpu_sa_bo *sa_bo)
  165. {
  166. return sa_bo->manager->cpu_ptr + sa_bo->soffset;
  167. }
  168. int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
  169. struct amdgpu_sa_manager *sa_manager,
  170. unsigned size, u32 align, u32 domain);
  171. void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
  172. struct amdgpu_sa_manager *sa_manager);
  173. int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev,
  174. struct amdgpu_sa_manager *sa_manager);
  175. int amdgpu_sa_bo_manager_suspend(struct amdgpu_device *adev,
  176. struct amdgpu_sa_manager *sa_manager);
  177. int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
  178. struct amdgpu_sa_bo **sa_bo,
  179. unsigned size, unsigned align);
  180. void amdgpu_sa_bo_free(struct amdgpu_device *adev,
  181. struct amdgpu_sa_bo **sa_bo,
  182. struct fence *fence);
  183. #if defined(CONFIG_DEBUG_FS)
  184. void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
  185. struct seq_file *m);
  186. #endif
  187. #endif