sdma_v3_0.c 44 KB

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  1. /*
  2. * Copyright 2014 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Alex Deucher
  23. */
  24. #include <linux/firmware.h>
  25. #include <drm/drmP.h>
  26. #include "amdgpu.h"
  27. #include "amdgpu_ucode.h"
  28. #include "amdgpu_trace.h"
  29. #include "vi.h"
  30. #include "vid.h"
  31. #include "oss/oss_3_0_d.h"
  32. #include "oss/oss_3_0_sh_mask.h"
  33. #include "gmc/gmc_8_1_d.h"
  34. #include "gmc/gmc_8_1_sh_mask.h"
  35. #include "gca/gfx_8_0_d.h"
  36. #include "gca/gfx_8_0_enum.h"
  37. #include "gca/gfx_8_0_sh_mask.h"
  38. #include "bif/bif_5_0_d.h"
  39. #include "bif/bif_5_0_sh_mask.h"
  40. #include "tonga_sdma_pkt_open.h"
  41. static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev);
  42. static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev);
  43. static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  44. static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev);
  45. MODULE_FIRMWARE("amdgpu/tonga_sdma.bin");
  46. MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin");
  47. MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin");
  48. MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");
  49. MODULE_FIRMWARE("amdgpu/fiji_sdma.bin");
  50. MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin");
  51. MODULE_FIRMWARE("amdgpu/stoney_sdma.bin");
  52. static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  53. {
  54. SDMA0_REGISTER_OFFSET,
  55. SDMA1_REGISTER_OFFSET
  56. };
  57. static const u32 golden_settings_tonga_a11[] =
  58. {
  59. mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  60. mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
  61. mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  62. mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  63. mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  64. mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  65. mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
  66. mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  67. mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  68. mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  69. };
  70. static const u32 tonga_mgcg_cgcg_init[] =
  71. {
  72. mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  73. mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
  74. };
  75. static const u32 golden_settings_fiji_a10[] =
  76. {
  77. mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  78. mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  79. mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  80. mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  81. mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  82. mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  83. mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  84. mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  85. };
  86. static const u32 fiji_mgcg_cgcg_init[] =
  87. {
  88. mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  89. mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
  90. };
  91. static const u32 cz_golden_settings_a11[] =
  92. {
  93. mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  94. mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
  95. mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
  96. mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
  97. mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
  98. mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
  99. mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  100. mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
  101. mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100,
  102. mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800,
  103. mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
  104. mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
  105. };
  106. static const u32 cz_mgcg_cgcg_init[] =
  107. {
  108. mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  109. mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
  110. };
  111. static const u32 stoney_golden_settings_a11[] =
  112. {
  113. mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
  114. mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
  115. mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
  116. mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
  117. };
  118. static const u32 stoney_mgcg_cgcg_init[] =
  119. {
  120. mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
  121. };
  122. /*
  123. * sDMA - System DMA
  124. * Starting with CIK, the GPU has new asynchronous
  125. * DMA engines. These engines are used for compute
  126. * and gfx. There are two DMA engines (SDMA0, SDMA1)
  127. * and each one supports 1 ring buffer used for gfx
  128. * and 2 queues used for compute.
  129. *
  130. * The programming model is very similar to the CP
  131. * (ring buffer, IBs, etc.), but sDMA has it's own
  132. * packet format that is different from the PM4 format
  133. * used by the CP. sDMA supports copying data, writing
  134. * embedded data, solid fills, and a number of other
  135. * things. It also has support for tiling/detiling of
  136. * buffers.
  137. */
  138. static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
  139. {
  140. switch (adev->asic_type) {
  141. case CHIP_FIJI:
  142. amdgpu_program_register_sequence(adev,
  143. fiji_mgcg_cgcg_init,
  144. (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
  145. amdgpu_program_register_sequence(adev,
  146. golden_settings_fiji_a10,
  147. (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
  148. break;
  149. case CHIP_TONGA:
  150. amdgpu_program_register_sequence(adev,
  151. tonga_mgcg_cgcg_init,
  152. (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
  153. amdgpu_program_register_sequence(adev,
  154. golden_settings_tonga_a11,
  155. (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
  156. break;
  157. case CHIP_CARRIZO:
  158. amdgpu_program_register_sequence(adev,
  159. cz_mgcg_cgcg_init,
  160. (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
  161. amdgpu_program_register_sequence(adev,
  162. cz_golden_settings_a11,
  163. (const u32)ARRAY_SIZE(cz_golden_settings_a11));
  164. break;
  165. case CHIP_STONEY:
  166. amdgpu_program_register_sequence(adev,
  167. stoney_mgcg_cgcg_init,
  168. (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
  169. amdgpu_program_register_sequence(adev,
  170. stoney_golden_settings_a11,
  171. (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
  172. break;
  173. default:
  174. break;
  175. }
  176. }
  177. /**
  178. * sdma_v3_0_init_microcode - load ucode images from disk
  179. *
  180. * @adev: amdgpu_device pointer
  181. *
  182. * Use the firmware interface to load the ucode images into
  183. * the driver (not loaded into hw).
  184. * Returns 0 on success, error on failure.
  185. */
  186. static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
  187. {
  188. const char *chip_name;
  189. char fw_name[30];
  190. int err = 0, i;
  191. struct amdgpu_firmware_info *info = NULL;
  192. const struct common_firmware_header *header = NULL;
  193. const struct sdma_firmware_header_v1_0 *hdr;
  194. DRM_DEBUG("\n");
  195. switch (adev->asic_type) {
  196. case CHIP_TONGA:
  197. chip_name = "tonga";
  198. break;
  199. case CHIP_FIJI:
  200. chip_name = "fiji";
  201. break;
  202. case CHIP_CARRIZO:
  203. chip_name = "carrizo";
  204. break;
  205. case CHIP_STONEY:
  206. chip_name = "stoney";
  207. break;
  208. default: BUG();
  209. }
  210. for (i = 0; i < adev->sdma.num_instances; i++) {
  211. if (i == 0)
  212. snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
  213. else
  214. snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
  215. err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
  216. if (err)
  217. goto out;
  218. err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
  219. if (err)
  220. goto out;
  221. hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
  222. adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
  223. adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
  224. if (adev->sdma.instance[i].feature_version >= 20)
  225. adev->sdma.instance[i].burst_nop = true;
  226. if (adev->firmware.smu_load) {
  227. info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
  228. info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
  229. info->fw = adev->sdma.instance[i].fw;
  230. header = (const struct common_firmware_header *)info->fw->data;
  231. adev->firmware.fw_size +=
  232. ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
  233. }
  234. }
  235. out:
  236. if (err) {
  237. printk(KERN_ERR
  238. "sdma_v3_0: Failed to load firmware \"%s\"\n",
  239. fw_name);
  240. for (i = 0; i < adev->sdma.num_instances; i++) {
  241. release_firmware(adev->sdma.instance[i].fw);
  242. adev->sdma.instance[i].fw = NULL;
  243. }
  244. }
  245. return err;
  246. }
  247. /**
  248. * sdma_v3_0_ring_get_rptr - get the current read pointer
  249. *
  250. * @ring: amdgpu ring pointer
  251. *
  252. * Get the current rptr from the hardware (VI+).
  253. */
  254. static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
  255. {
  256. u32 rptr;
  257. /* XXX check if swapping is necessary on BE */
  258. rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2;
  259. return rptr;
  260. }
  261. /**
  262. * sdma_v3_0_ring_get_wptr - get the current write pointer
  263. *
  264. * @ring: amdgpu ring pointer
  265. *
  266. * Get the current wptr from the hardware (VI+).
  267. */
  268. static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
  269. {
  270. struct amdgpu_device *adev = ring->adev;
  271. u32 wptr;
  272. if (ring->use_doorbell) {
  273. /* XXX check if swapping is necessary on BE */
  274. wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
  275. } else {
  276. int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
  277. wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
  278. }
  279. return wptr;
  280. }
  281. /**
  282. * sdma_v3_0_ring_set_wptr - commit the write pointer
  283. *
  284. * @ring: amdgpu ring pointer
  285. *
  286. * Write the wptr back to the hardware (VI+).
  287. */
  288. static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
  289. {
  290. struct amdgpu_device *adev = ring->adev;
  291. if (ring->use_doorbell) {
  292. /* XXX check if swapping is necessary on BE */
  293. adev->wb.wb[ring->wptr_offs] = ring->wptr << 2;
  294. WDOORBELL32(ring->doorbell_index, ring->wptr << 2);
  295. } else {
  296. int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
  297. WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
  298. }
  299. }
  300. static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
  301. {
  302. struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
  303. int i;
  304. for (i = 0; i < count; i++)
  305. if (sdma && sdma->burst_nop && (i == 0))
  306. amdgpu_ring_write(ring, ring->nop |
  307. SDMA_PKT_NOP_HEADER_COUNT(count - 1));
  308. else
  309. amdgpu_ring_write(ring, ring->nop);
  310. }
  311. /**
  312. * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
  313. *
  314. * @ring: amdgpu ring pointer
  315. * @ib: IB object to schedule
  316. *
  317. * Schedule an IB in the DMA ring (VI).
  318. */
  319. static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
  320. struct amdgpu_ib *ib)
  321. {
  322. u32 vmid = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf;
  323. u32 next_rptr = ring->wptr + 5;
  324. while ((next_rptr & 7) != 2)
  325. next_rptr++;
  326. next_rptr += 6;
  327. amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
  328. SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
  329. amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc);
  330. amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
  331. amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
  332. amdgpu_ring_write(ring, next_rptr);
  333. /* IB packet must end on a 8 DW boundary */
  334. sdma_v3_0_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8);
  335. amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
  336. SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
  337. /* base must be 32 byte aligned */
  338. amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
  339. amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
  340. amdgpu_ring_write(ring, ib->length_dw);
  341. amdgpu_ring_write(ring, 0);
  342. amdgpu_ring_write(ring, 0);
  343. }
  344. /**
  345. * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
  346. *
  347. * @ring: amdgpu ring pointer
  348. *
  349. * Emit an hdp flush packet on the requested DMA ring.
  350. */
  351. static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
  352. {
  353. u32 ref_and_mask = 0;
  354. if (ring == &ring->adev->sdma.instance[0].ring)
  355. ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
  356. else
  357. ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
  358. amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
  359. SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
  360. SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
  361. amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
  362. amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
  363. amdgpu_ring_write(ring, ref_and_mask); /* reference */
  364. amdgpu_ring_write(ring, ref_and_mask); /* mask */
  365. amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
  366. SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
  367. }
  368. /**
  369. * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
  370. *
  371. * @ring: amdgpu ring pointer
  372. * @fence: amdgpu fence object
  373. *
  374. * Add a DMA fence packet to the ring to write
  375. * the fence seq number and DMA trap packet to generate
  376. * an interrupt if needed (VI).
  377. */
  378. static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
  379. unsigned flags)
  380. {
  381. bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
  382. /* write the fence */
  383. amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
  384. amdgpu_ring_write(ring, lower_32_bits(addr));
  385. amdgpu_ring_write(ring, upper_32_bits(addr));
  386. amdgpu_ring_write(ring, lower_32_bits(seq));
  387. /* optionally write high bits as well */
  388. if (write64bit) {
  389. addr += 4;
  390. amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
  391. amdgpu_ring_write(ring, lower_32_bits(addr));
  392. amdgpu_ring_write(ring, upper_32_bits(addr));
  393. amdgpu_ring_write(ring, upper_32_bits(seq));
  394. }
  395. /* generate an interrupt */
  396. amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
  397. amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
  398. }
  399. /**
  400. * sdma_v3_0_ring_emit_semaphore - emit a semaphore on the dma ring
  401. *
  402. * @ring: amdgpu_ring structure holding ring information
  403. * @semaphore: amdgpu semaphore object
  404. * @emit_wait: wait or signal semaphore
  405. *
  406. * Add a DMA semaphore packet to the ring wait on or signal
  407. * other rings (VI).
  408. */
  409. static bool sdma_v3_0_ring_emit_semaphore(struct amdgpu_ring *ring,
  410. struct amdgpu_semaphore *semaphore,
  411. bool emit_wait)
  412. {
  413. u64 addr = semaphore->gpu_addr;
  414. u32 sig = emit_wait ? 0 : 1;
  415. amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SEM) |
  416. SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(sig));
  417. amdgpu_ring_write(ring, lower_32_bits(addr) & 0xfffffff8);
  418. amdgpu_ring_write(ring, upper_32_bits(addr));
  419. return true;
  420. }
  421. /**
  422. * sdma_v3_0_gfx_stop - stop the gfx async dma engines
  423. *
  424. * @adev: amdgpu_device pointer
  425. *
  426. * Stop the gfx async dma ring buffers (VI).
  427. */
  428. static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
  429. {
  430. struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
  431. struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
  432. u32 rb_cntl, ib_cntl;
  433. int i;
  434. if ((adev->mman.buffer_funcs_ring == sdma0) ||
  435. (adev->mman.buffer_funcs_ring == sdma1))
  436. amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
  437. for (i = 0; i < adev->sdma.num_instances; i++) {
  438. rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
  439. rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
  440. WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
  441. ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
  442. ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
  443. WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
  444. }
  445. sdma0->ready = false;
  446. sdma1->ready = false;
  447. }
  448. /**
  449. * sdma_v3_0_rlc_stop - stop the compute async dma engines
  450. *
  451. * @adev: amdgpu_device pointer
  452. *
  453. * Stop the compute async dma queues (VI).
  454. */
  455. static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
  456. {
  457. /* XXX todo */
  458. }
  459. /**
  460. * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
  461. *
  462. * @adev: amdgpu_device pointer
  463. * @enable: enable/disable the DMA MEs context switch.
  464. *
  465. * Halt or unhalt the async dma engines context switch (VI).
  466. */
  467. static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
  468. {
  469. u32 f32_cntl;
  470. int i;
  471. for (i = 0; i < adev->sdma.num_instances; i++) {
  472. f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
  473. if (enable)
  474. f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
  475. AUTO_CTXSW_ENABLE, 1);
  476. else
  477. f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
  478. AUTO_CTXSW_ENABLE, 0);
  479. WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
  480. }
  481. }
  482. /**
  483. * sdma_v3_0_enable - stop the async dma engines
  484. *
  485. * @adev: amdgpu_device pointer
  486. * @enable: enable/disable the DMA MEs.
  487. *
  488. * Halt or unhalt the async dma engines (VI).
  489. */
  490. static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
  491. {
  492. u32 f32_cntl;
  493. int i;
  494. if (enable == false) {
  495. sdma_v3_0_gfx_stop(adev);
  496. sdma_v3_0_rlc_stop(adev);
  497. }
  498. for (i = 0; i < adev->sdma.num_instances; i++) {
  499. f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
  500. if (enable)
  501. f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
  502. else
  503. f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
  504. WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
  505. }
  506. }
  507. /**
  508. * sdma_v3_0_gfx_resume - setup and start the async dma engines
  509. *
  510. * @adev: amdgpu_device pointer
  511. *
  512. * Set up the gfx DMA ring buffers and enable them (VI).
  513. * Returns 0 for success, error for failure.
  514. */
  515. static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
  516. {
  517. struct amdgpu_ring *ring;
  518. u32 rb_cntl, ib_cntl;
  519. u32 rb_bufsz;
  520. u32 wb_offset;
  521. u32 doorbell;
  522. int i, j, r;
  523. for (i = 0; i < adev->sdma.num_instances; i++) {
  524. ring = &adev->sdma.instance[i].ring;
  525. wb_offset = (ring->rptr_offs * 4);
  526. mutex_lock(&adev->srbm_mutex);
  527. for (j = 0; j < 16; j++) {
  528. vi_srbm_select(adev, 0, 0, 0, j);
  529. /* SDMA GFX */
  530. WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
  531. WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
  532. }
  533. vi_srbm_select(adev, 0, 0, 0, 0);
  534. mutex_unlock(&adev->srbm_mutex);
  535. WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
  536. /* Set ring buffer size in dwords */
  537. rb_bufsz = order_base_2(ring->ring_size / 4);
  538. rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
  539. rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
  540. #ifdef __BIG_ENDIAN
  541. rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
  542. rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
  543. RPTR_WRITEBACK_SWAP_ENABLE, 1);
  544. #endif
  545. WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
  546. /* Initialize the ring buffer's read and write pointers */
  547. WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
  548. WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
  549. /* set the wb address whether it's enabled or not */
  550. WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
  551. upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
  552. WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
  553. lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
  554. rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
  555. WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
  556. WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
  557. ring->wptr = 0;
  558. WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
  559. doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
  560. if (ring->use_doorbell) {
  561. doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
  562. OFFSET, ring->doorbell_index);
  563. doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
  564. } else {
  565. doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
  566. }
  567. WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
  568. /* enable DMA RB */
  569. rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
  570. WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
  571. ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
  572. ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
  573. #ifdef __BIG_ENDIAN
  574. ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
  575. #endif
  576. /* enable DMA IBs */
  577. WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
  578. ring->ready = true;
  579. r = amdgpu_ring_test_ring(ring);
  580. if (r) {
  581. ring->ready = false;
  582. return r;
  583. }
  584. if (adev->mman.buffer_funcs_ring == ring)
  585. amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
  586. }
  587. return 0;
  588. }
  589. /**
  590. * sdma_v3_0_rlc_resume - setup and start the async dma engines
  591. *
  592. * @adev: amdgpu_device pointer
  593. *
  594. * Set up the compute DMA queues and enable them (VI).
  595. * Returns 0 for success, error for failure.
  596. */
  597. static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
  598. {
  599. /* XXX todo */
  600. return 0;
  601. }
  602. /**
  603. * sdma_v3_0_load_microcode - load the sDMA ME ucode
  604. *
  605. * @adev: amdgpu_device pointer
  606. *
  607. * Loads the sDMA0/1 ucode.
  608. * Returns 0 for success, -EINVAL if the ucode is not available.
  609. */
  610. static int sdma_v3_0_load_microcode(struct amdgpu_device *adev)
  611. {
  612. const struct sdma_firmware_header_v1_0 *hdr;
  613. const __le32 *fw_data;
  614. u32 fw_size;
  615. int i, j;
  616. /* halt the MEs */
  617. sdma_v3_0_enable(adev, false);
  618. for (i = 0; i < adev->sdma.num_instances; i++) {
  619. if (!adev->sdma.instance[i].fw)
  620. return -EINVAL;
  621. hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
  622. amdgpu_ucode_print_sdma_hdr(&hdr->header);
  623. fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
  624. fw_data = (const __le32 *)
  625. (adev->sdma.instance[i].fw->data +
  626. le32_to_cpu(hdr->header.ucode_array_offset_bytes));
  627. WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
  628. for (j = 0; j < fw_size; j++)
  629. WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
  630. WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
  631. }
  632. return 0;
  633. }
  634. /**
  635. * sdma_v3_0_start - setup and start the async dma engines
  636. *
  637. * @adev: amdgpu_device pointer
  638. *
  639. * Set up the DMA engines and enable them (VI).
  640. * Returns 0 for success, error for failure.
  641. */
  642. static int sdma_v3_0_start(struct amdgpu_device *adev)
  643. {
  644. int r, i;
  645. if (!adev->firmware.smu_load) {
  646. r = sdma_v3_0_load_microcode(adev);
  647. if (r)
  648. return r;
  649. } else {
  650. for (i = 0; i < adev->sdma.num_instances; i++) {
  651. r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
  652. (i == 0) ?
  653. AMDGPU_UCODE_ID_SDMA0 :
  654. AMDGPU_UCODE_ID_SDMA1);
  655. if (r)
  656. return -EINVAL;
  657. }
  658. }
  659. /* unhalt the MEs */
  660. sdma_v3_0_enable(adev, true);
  661. /* enable sdma ring preemption */
  662. sdma_v3_0_ctx_switch_enable(adev, true);
  663. /* start the gfx rings and rlc compute queues */
  664. r = sdma_v3_0_gfx_resume(adev);
  665. if (r)
  666. return r;
  667. r = sdma_v3_0_rlc_resume(adev);
  668. if (r)
  669. return r;
  670. return 0;
  671. }
  672. /**
  673. * sdma_v3_0_ring_test_ring - simple async dma engine test
  674. *
  675. * @ring: amdgpu_ring structure holding ring information
  676. *
  677. * Test the DMA engine by writing using it to write an
  678. * value to memory. (VI).
  679. * Returns 0 for success, error for failure.
  680. */
  681. static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
  682. {
  683. struct amdgpu_device *adev = ring->adev;
  684. unsigned i;
  685. unsigned index;
  686. int r;
  687. u32 tmp;
  688. u64 gpu_addr;
  689. r = amdgpu_wb_get(adev, &index);
  690. if (r) {
  691. dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
  692. return r;
  693. }
  694. gpu_addr = adev->wb.gpu_addr + (index * 4);
  695. tmp = 0xCAFEDEAD;
  696. adev->wb.wb[index] = cpu_to_le32(tmp);
  697. r = amdgpu_ring_lock(ring, 5);
  698. if (r) {
  699. DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
  700. amdgpu_wb_free(adev, index);
  701. return r;
  702. }
  703. amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
  704. SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
  705. amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
  706. amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
  707. amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
  708. amdgpu_ring_write(ring, 0xDEADBEEF);
  709. amdgpu_ring_unlock_commit(ring);
  710. for (i = 0; i < adev->usec_timeout; i++) {
  711. tmp = le32_to_cpu(adev->wb.wb[index]);
  712. if (tmp == 0xDEADBEEF)
  713. break;
  714. DRM_UDELAY(1);
  715. }
  716. if (i < adev->usec_timeout) {
  717. DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
  718. } else {
  719. DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
  720. ring->idx, tmp);
  721. r = -EINVAL;
  722. }
  723. amdgpu_wb_free(adev, index);
  724. return r;
  725. }
  726. /**
  727. * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
  728. *
  729. * @ring: amdgpu_ring structure holding ring information
  730. *
  731. * Test a simple IB in the DMA ring (VI).
  732. * Returns 0 on success, error on failure.
  733. */
  734. static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring)
  735. {
  736. struct amdgpu_device *adev = ring->adev;
  737. struct amdgpu_ib ib;
  738. struct fence *f = NULL;
  739. unsigned i;
  740. unsigned index;
  741. int r;
  742. u32 tmp = 0;
  743. u64 gpu_addr;
  744. r = amdgpu_wb_get(adev, &index);
  745. if (r) {
  746. dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
  747. return r;
  748. }
  749. gpu_addr = adev->wb.gpu_addr + (index * 4);
  750. tmp = 0xCAFEDEAD;
  751. adev->wb.wb[index] = cpu_to_le32(tmp);
  752. memset(&ib, 0, sizeof(ib));
  753. r = amdgpu_ib_get(ring, NULL, 256, &ib);
  754. if (r) {
  755. DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
  756. goto err0;
  757. }
  758. ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
  759. SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
  760. ib.ptr[1] = lower_32_bits(gpu_addr);
  761. ib.ptr[2] = upper_32_bits(gpu_addr);
  762. ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
  763. ib.ptr[4] = 0xDEADBEEF;
  764. ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
  765. ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
  766. ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
  767. ib.length_dw = 8;
  768. r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL,
  769. AMDGPU_FENCE_OWNER_UNDEFINED,
  770. &f);
  771. if (r)
  772. goto err1;
  773. r = fence_wait(f, false);
  774. if (r) {
  775. DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
  776. goto err1;
  777. }
  778. for (i = 0; i < adev->usec_timeout; i++) {
  779. tmp = le32_to_cpu(adev->wb.wb[index]);
  780. if (tmp == 0xDEADBEEF)
  781. break;
  782. DRM_UDELAY(1);
  783. }
  784. if (i < adev->usec_timeout) {
  785. DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
  786. ring->idx, i);
  787. goto err1;
  788. } else {
  789. DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
  790. r = -EINVAL;
  791. }
  792. err1:
  793. fence_put(f);
  794. amdgpu_ib_free(adev, &ib);
  795. err0:
  796. amdgpu_wb_free(adev, index);
  797. return r;
  798. }
  799. /**
  800. * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
  801. *
  802. * @ib: indirect buffer to fill with commands
  803. * @pe: addr of the page entry
  804. * @src: src addr to copy from
  805. * @count: number of page entries to update
  806. *
  807. * Update PTEs by copying them from the GART using sDMA (CIK).
  808. */
  809. static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
  810. uint64_t pe, uint64_t src,
  811. unsigned count)
  812. {
  813. while (count) {
  814. unsigned bytes = count * 8;
  815. if (bytes > 0x1FFFF8)
  816. bytes = 0x1FFFF8;
  817. ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
  818. SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
  819. ib->ptr[ib->length_dw++] = bytes;
  820. ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
  821. ib->ptr[ib->length_dw++] = lower_32_bits(src);
  822. ib->ptr[ib->length_dw++] = upper_32_bits(src);
  823. ib->ptr[ib->length_dw++] = lower_32_bits(pe);
  824. ib->ptr[ib->length_dw++] = upper_32_bits(pe);
  825. pe += bytes;
  826. src += bytes;
  827. count -= bytes / 8;
  828. }
  829. }
  830. /**
  831. * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
  832. *
  833. * @ib: indirect buffer to fill with commands
  834. * @pe: addr of the page entry
  835. * @addr: dst addr to write into pe
  836. * @count: number of page entries to update
  837. * @incr: increase next addr by incr bytes
  838. * @flags: access flags
  839. *
  840. * Update PTEs by writing them manually using sDMA (CIK).
  841. */
  842. static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib,
  843. uint64_t pe,
  844. uint64_t addr, unsigned count,
  845. uint32_t incr, uint32_t flags)
  846. {
  847. uint64_t value;
  848. unsigned ndw;
  849. while (count) {
  850. ndw = count * 2;
  851. if (ndw > 0xFFFFE)
  852. ndw = 0xFFFFE;
  853. /* for non-physically contiguous pages (system) */
  854. ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
  855. SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
  856. ib->ptr[ib->length_dw++] = pe;
  857. ib->ptr[ib->length_dw++] = upper_32_bits(pe);
  858. ib->ptr[ib->length_dw++] = ndw;
  859. for (; ndw > 0; ndw -= 2, --count, pe += 8) {
  860. if (flags & AMDGPU_PTE_SYSTEM) {
  861. value = amdgpu_vm_map_gart(ib->ring->adev, addr);
  862. value &= 0xFFFFFFFFFFFFF000ULL;
  863. } else if (flags & AMDGPU_PTE_VALID) {
  864. value = addr;
  865. } else {
  866. value = 0;
  867. }
  868. addr += incr;
  869. value |= flags;
  870. ib->ptr[ib->length_dw++] = value;
  871. ib->ptr[ib->length_dw++] = upper_32_bits(value);
  872. }
  873. }
  874. }
  875. /**
  876. * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
  877. *
  878. * @ib: indirect buffer to fill with commands
  879. * @pe: addr of the page entry
  880. * @addr: dst addr to write into pe
  881. * @count: number of page entries to update
  882. * @incr: increase next addr by incr bytes
  883. * @flags: access flags
  884. *
  885. * Update the page tables using sDMA (CIK).
  886. */
  887. static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib,
  888. uint64_t pe,
  889. uint64_t addr, unsigned count,
  890. uint32_t incr, uint32_t flags)
  891. {
  892. uint64_t value;
  893. unsigned ndw;
  894. while (count) {
  895. ndw = count;
  896. if (ndw > 0x7FFFF)
  897. ndw = 0x7FFFF;
  898. if (flags & AMDGPU_PTE_VALID)
  899. value = addr;
  900. else
  901. value = 0;
  902. /* for physically contiguous pages (vram) */
  903. ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
  904. ib->ptr[ib->length_dw++] = pe; /* dst addr */
  905. ib->ptr[ib->length_dw++] = upper_32_bits(pe);
  906. ib->ptr[ib->length_dw++] = flags; /* mask */
  907. ib->ptr[ib->length_dw++] = 0;
  908. ib->ptr[ib->length_dw++] = value; /* value */
  909. ib->ptr[ib->length_dw++] = upper_32_bits(value);
  910. ib->ptr[ib->length_dw++] = incr; /* increment size */
  911. ib->ptr[ib->length_dw++] = 0;
  912. ib->ptr[ib->length_dw++] = ndw; /* number of entries */
  913. pe += ndw * 8;
  914. addr += ndw * incr;
  915. count -= ndw;
  916. }
  917. }
  918. /**
  919. * sdma_v3_0_vm_pad_ib - pad the IB to the required number of dw
  920. *
  921. * @ib: indirect buffer to fill with padding
  922. *
  923. */
  924. static void sdma_v3_0_vm_pad_ib(struct amdgpu_ib *ib)
  925. {
  926. struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ib->ring);
  927. u32 pad_count;
  928. int i;
  929. pad_count = (8 - (ib->length_dw & 0x7)) % 8;
  930. for (i = 0; i < pad_count; i++)
  931. if (sdma && sdma->burst_nop && (i == 0))
  932. ib->ptr[ib->length_dw++] =
  933. SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
  934. SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
  935. else
  936. ib->ptr[ib->length_dw++] =
  937. SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
  938. }
  939. /**
  940. * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
  941. *
  942. * @ring: amdgpu_ring pointer
  943. * @vm: amdgpu_vm pointer
  944. *
  945. * Update the page table base and flush the VM TLB
  946. * using sDMA (VI).
  947. */
  948. static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
  949. unsigned vm_id, uint64_t pd_addr)
  950. {
  951. amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
  952. SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
  953. if (vm_id < 8) {
  954. amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
  955. } else {
  956. amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
  957. }
  958. amdgpu_ring_write(ring, pd_addr >> 12);
  959. /* flush TLB */
  960. amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
  961. SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
  962. amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
  963. amdgpu_ring_write(ring, 1 << vm_id);
  964. /* wait for flush */
  965. amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
  966. SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
  967. SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
  968. amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
  969. amdgpu_ring_write(ring, 0);
  970. amdgpu_ring_write(ring, 0); /* reference */
  971. amdgpu_ring_write(ring, 0); /* mask */
  972. amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
  973. SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
  974. }
  975. static int sdma_v3_0_early_init(void *handle)
  976. {
  977. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  978. switch (adev->asic_type) {
  979. case CHIP_STONEY:
  980. adev->sdma.num_instances = 1;
  981. break;
  982. default:
  983. adev->sdma.num_instances = SDMA_MAX_INSTANCE;
  984. break;
  985. }
  986. sdma_v3_0_set_ring_funcs(adev);
  987. sdma_v3_0_set_buffer_funcs(adev);
  988. sdma_v3_0_set_vm_pte_funcs(adev);
  989. sdma_v3_0_set_irq_funcs(adev);
  990. return 0;
  991. }
  992. static int sdma_v3_0_sw_init(void *handle)
  993. {
  994. struct amdgpu_ring *ring;
  995. int r, i;
  996. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  997. /* SDMA trap event */
  998. r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
  999. if (r)
  1000. return r;
  1001. /* SDMA Privileged inst */
  1002. r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
  1003. if (r)
  1004. return r;
  1005. /* SDMA Privileged inst */
  1006. r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
  1007. if (r)
  1008. return r;
  1009. r = sdma_v3_0_init_microcode(adev);
  1010. if (r) {
  1011. DRM_ERROR("Failed to load sdma firmware!\n");
  1012. return r;
  1013. }
  1014. for (i = 0; i < adev->sdma.num_instances; i++) {
  1015. ring = &adev->sdma.instance[i].ring;
  1016. ring->ring_obj = NULL;
  1017. ring->use_doorbell = true;
  1018. ring->doorbell_index = (i == 0) ?
  1019. AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1;
  1020. sprintf(ring->name, "sdma%d", i);
  1021. r = amdgpu_ring_init(adev, ring, 256 * 1024,
  1022. SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
  1023. &adev->sdma.trap_irq,
  1024. (i == 0) ?
  1025. AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
  1026. AMDGPU_RING_TYPE_SDMA);
  1027. if (r)
  1028. return r;
  1029. }
  1030. return r;
  1031. }
  1032. static int sdma_v3_0_sw_fini(void *handle)
  1033. {
  1034. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  1035. int i;
  1036. for (i = 0; i < adev->sdma.num_instances; i++)
  1037. amdgpu_ring_fini(&adev->sdma.instance[i].ring);
  1038. return 0;
  1039. }
  1040. static int sdma_v3_0_hw_init(void *handle)
  1041. {
  1042. int r;
  1043. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  1044. sdma_v3_0_init_golden_registers(adev);
  1045. r = sdma_v3_0_start(adev);
  1046. if (r)
  1047. return r;
  1048. return r;
  1049. }
  1050. static int sdma_v3_0_hw_fini(void *handle)
  1051. {
  1052. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  1053. sdma_v3_0_ctx_switch_enable(adev, false);
  1054. sdma_v3_0_enable(adev, false);
  1055. return 0;
  1056. }
  1057. static int sdma_v3_0_suspend(void *handle)
  1058. {
  1059. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  1060. return sdma_v3_0_hw_fini(adev);
  1061. }
  1062. static int sdma_v3_0_resume(void *handle)
  1063. {
  1064. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  1065. return sdma_v3_0_hw_init(adev);
  1066. }
  1067. static bool sdma_v3_0_is_idle(void *handle)
  1068. {
  1069. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  1070. u32 tmp = RREG32(mmSRBM_STATUS2);
  1071. if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
  1072. SRBM_STATUS2__SDMA1_BUSY_MASK))
  1073. return false;
  1074. return true;
  1075. }
  1076. static int sdma_v3_0_wait_for_idle(void *handle)
  1077. {
  1078. unsigned i;
  1079. u32 tmp;
  1080. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  1081. for (i = 0; i < adev->usec_timeout; i++) {
  1082. tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
  1083. SRBM_STATUS2__SDMA1_BUSY_MASK);
  1084. if (!tmp)
  1085. return 0;
  1086. udelay(1);
  1087. }
  1088. return -ETIMEDOUT;
  1089. }
  1090. static void sdma_v3_0_print_status(void *handle)
  1091. {
  1092. int i, j;
  1093. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  1094. dev_info(adev->dev, "VI SDMA registers\n");
  1095. dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
  1096. RREG32(mmSRBM_STATUS2));
  1097. for (i = 0; i < adev->sdma.num_instances; i++) {
  1098. dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n",
  1099. i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
  1100. dev_info(adev->dev, " SDMA%d_F32_CNTL=0x%08X\n",
  1101. i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
  1102. dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n",
  1103. i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
  1104. dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
  1105. i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
  1106. dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n",
  1107. i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
  1108. dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n",
  1109. i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
  1110. dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n",
  1111. i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
  1112. dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n",
  1113. i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
  1114. dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
  1115. i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
  1116. dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
  1117. i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
  1118. dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n",
  1119. i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
  1120. dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
  1121. i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
  1122. dev_info(adev->dev, " SDMA%d_GFX_DOORBELL=0x%08X\n",
  1123. i, RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]));
  1124. mutex_lock(&adev->srbm_mutex);
  1125. for (j = 0; j < 16; j++) {
  1126. vi_srbm_select(adev, 0, 0, 0, j);
  1127. dev_info(adev->dev, " VM %d:\n", j);
  1128. dev_info(adev->dev, " SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n",
  1129. i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
  1130. dev_info(adev->dev, " SDMA%d_GFX_APE1_CNTL=0x%08X\n",
  1131. i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
  1132. }
  1133. vi_srbm_select(adev, 0, 0, 0, 0);
  1134. mutex_unlock(&adev->srbm_mutex);
  1135. }
  1136. }
  1137. static int sdma_v3_0_soft_reset(void *handle)
  1138. {
  1139. u32 srbm_soft_reset = 0;
  1140. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  1141. u32 tmp = RREG32(mmSRBM_STATUS2);
  1142. if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
  1143. /* sdma0 */
  1144. tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
  1145. tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
  1146. WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
  1147. srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
  1148. }
  1149. if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
  1150. /* sdma1 */
  1151. tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
  1152. tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
  1153. WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
  1154. srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
  1155. }
  1156. if (srbm_soft_reset) {
  1157. sdma_v3_0_print_status((void *)adev);
  1158. tmp = RREG32(mmSRBM_SOFT_RESET);
  1159. tmp |= srbm_soft_reset;
  1160. dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
  1161. WREG32(mmSRBM_SOFT_RESET, tmp);
  1162. tmp = RREG32(mmSRBM_SOFT_RESET);
  1163. udelay(50);
  1164. tmp &= ~srbm_soft_reset;
  1165. WREG32(mmSRBM_SOFT_RESET, tmp);
  1166. tmp = RREG32(mmSRBM_SOFT_RESET);
  1167. /* Wait a little for things to settle down */
  1168. udelay(50);
  1169. sdma_v3_0_print_status((void *)adev);
  1170. }
  1171. return 0;
  1172. }
  1173. static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
  1174. struct amdgpu_irq_src *source,
  1175. unsigned type,
  1176. enum amdgpu_interrupt_state state)
  1177. {
  1178. u32 sdma_cntl;
  1179. switch (type) {
  1180. case AMDGPU_SDMA_IRQ_TRAP0:
  1181. switch (state) {
  1182. case AMDGPU_IRQ_STATE_DISABLE:
  1183. sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
  1184. sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
  1185. WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
  1186. break;
  1187. case AMDGPU_IRQ_STATE_ENABLE:
  1188. sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
  1189. sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
  1190. WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
  1191. break;
  1192. default:
  1193. break;
  1194. }
  1195. break;
  1196. case AMDGPU_SDMA_IRQ_TRAP1:
  1197. switch (state) {
  1198. case AMDGPU_IRQ_STATE_DISABLE:
  1199. sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
  1200. sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
  1201. WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
  1202. break;
  1203. case AMDGPU_IRQ_STATE_ENABLE:
  1204. sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
  1205. sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
  1206. WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
  1207. break;
  1208. default:
  1209. break;
  1210. }
  1211. break;
  1212. default:
  1213. break;
  1214. }
  1215. return 0;
  1216. }
  1217. static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
  1218. struct amdgpu_irq_src *source,
  1219. struct amdgpu_iv_entry *entry)
  1220. {
  1221. u8 instance_id, queue_id;
  1222. instance_id = (entry->ring_id & 0x3) >> 0;
  1223. queue_id = (entry->ring_id & 0xc) >> 2;
  1224. DRM_DEBUG("IH: SDMA trap\n");
  1225. switch (instance_id) {
  1226. case 0:
  1227. switch (queue_id) {
  1228. case 0:
  1229. amdgpu_fence_process(&adev->sdma.instance[0].ring);
  1230. break;
  1231. case 1:
  1232. /* XXX compute */
  1233. break;
  1234. case 2:
  1235. /* XXX compute */
  1236. break;
  1237. }
  1238. break;
  1239. case 1:
  1240. switch (queue_id) {
  1241. case 0:
  1242. amdgpu_fence_process(&adev->sdma.instance[1].ring);
  1243. break;
  1244. case 1:
  1245. /* XXX compute */
  1246. break;
  1247. case 2:
  1248. /* XXX compute */
  1249. break;
  1250. }
  1251. break;
  1252. }
  1253. return 0;
  1254. }
  1255. static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
  1256. struct amdgpu_irq_src *source,
  1257. struct amdgpu_iv_entry *entry)
  1258. {
  1259. DRM_ERROR("Illegal instruction in SDMA command stream\n");
  1260. schedule_work(&adev->reset_work);
  1261. return 0;
  1262. }
  1263. static int sdma_v3_0_set_clockgating_state(void *handle,
  1264. enum amd_clockgating_state state)
  1265. {
  1266. return 0;
  1267. }
  1268. static int sdma_v3_0_set_powergating_state(void *handle,
  1269. enum amd_powergating_state state)
  1270. {
  1271. return 0;
  1272. }
  1273. const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
  1274. .early_init = sdma_v3_0_early_init,
  1275. .late_init = NULL,
  1276. .sw_init = sdma_v3_0_sw_init,
  1277. .sw_fini = sdma_v3_0_sw_fini,
  1278. .hw_init = sdma_v3_0_hw_init,
  1279. .hw_fini = sdma_v3_0_hw_fini,
  1280. .suspend = sdma_v3_0_suspend,
  1281. .resume = sdma_v3_0_resume,
  1282. .is_idle = sdma_v3_0_is_idle,
  1283. .wait_for_idle = sdma_v3_0_wait_for_idle,
  1284. .soft_reset = sdma_v3_0_soft_reset,
  1285. .print_status = sdma_v3_0_print_status,
  1286. .set_clockgating_state = sdma_v3_0_set_clockgating_state,
  1287. .set_powergating_state = sdma_v3_0_set_powergating_state,
  1288. };
  1289. static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
  1290. .get_rptr = sdma_v3_0_ring_get_rptr,
  1291. .get_wptr = sdma_v3_0_ring_get_wptr,
  1292. .set_wptr = sdma_v3_0_ring_set_wptr,
  1293. .parse_cs = NULL,
  1294. .emit_ib = sdma_v3_0_ring_emit_ib,
  1295. .emit_fence = sdma_v3_0_ring_emit_fence,
  1296. .emit_semaphore = sdma_v3_0_ring_emit_semaphore,
  1297. .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
  1298. .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
  1299. .test_ring = sdma_v3_0_ring_test_ring,
  1300. .test_ib = sdma_v3_0_ring_test_ib,
  1301. .insert_nop = sdma_v3_0_ring_insert_nop,
  1302. };
  1303. static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
  1304. {
  1305. int i;
  1306. for (i = 0; i < adev->sdma.num_instances; i++)
  1307. adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
  1308. }
  1309. static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
  1310. .set = sdma_v3_0_set_trap_irq_state,
  1311. .process = sdma_v3_0_process_trap_irq,
  1312. };
  1313. static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = {
  1314. .process = sdma_v3_0_process_illegal_inst_irq,
  1315. };
  1316. static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
  1317. {
  1318. adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
  1319. adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
  1320. adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
  1321. }
  1322. /**
  1323. * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
  1324. *
  1325. * @ring: amdgpu_ring structure holding ring information
  1326. * @src_offset: src GPU address
  1327. * @dst_offset: dst GPU address
  1328. * @byte_count: number of bytes to xfer
  1329. *
  1330. * Copy GPU buffers using the DMA engine (VI).
  1331. * Used by the amdgpu ttm implementation to move pages if
  1332. * registered as the asic copy callback.
  1333. */
  1334. static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib,
  1335. uint64_t src_offset,
  1336. uint64_t dst_offset,
  1337. uint32_t byte_count)
  1338. {
  1339. ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
  1340. SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
  1341. ib->ptr[ib->length_dw++] = byte_count;
  1342. ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
  1343. ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
  1344. ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
  1345. ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
  1346. ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
  1347. }
  1348. /**
  1349. * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
  1350. *
  1351. * @ring: amdgpu_ring structure holding ring information
  1352. * @src_data: value to write to buffer
  1353. * @dst_offset: dst GPU address
  1354. * @byte_count: number of bytes to xfer
  1355. *
  1356. * Fill GPU buffers using the DMA engine (VI).
  1357. */
  1358. static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib,
  1359. uint32_t src_data,
  1360. uint64_t dst_offset,
  1361. uint32_t byte_count)
  1362. {
  1363. ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
  1364. ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
  1365. ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
  1366. ib->ptr[ib->length_dw++] = src_data;
  1367. ib->ptr[ib->length_dw++] = byte_count;
  1368. }
  1369. static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
  1370. .copy_max_bytes = 0x1fffff,
  1371. .copy_num_dw = 7,
  1372. .emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
  1373. .fill_max_bytes = 0x1fffff,
  1374. .fill_num_dw = 5,
  1375. .emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
  1376. };
  1377. static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
  1378. {
  1379. if (adev->mman.buffer_funcs == NULL) {
  1380. adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
  1381. adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
  1382. }
  1383. }
  1384. static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
  1385. .copy_pte = sdma_v3_0_vm_copy_pte,
  1386. .write_pte = sdma_v3_0_vm_write_pte,
  1387. .set_pte_pde = sdma_v3_0_vm_set_pte_pde,
  1388. .pad_ib = sdma_v3_0_vm_pad_ib,
  1389. };
  1390. static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
  1391. {
  1392. if (adev->vm_manager.vm_pte_funcs == NULL) {
  1393. adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
  1394. adev->vm_manager.vm_pte_funcs_ring = &adev->sdma.instance[0].ring;
  1395. adev->vm_manager.vm_pte_funcs_ring->is_pte_ring = true;
  1396. }
  1397. }