fsl_dcu_drm_plane.c 6.6 KB

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  1. /*
  2. * Copyright 2015 Freescale Semiconductor, Inc.
  3. *
  4. * Freescale DCU drm device driver
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. */
  11. #include <linux/regmap.h>
  12. #include <drm/drmP.h>
  13. #include <drm/drm_atomic_helper.h>
  14. #include <drm/drm_crtc.h>
  15. #include <drm/drm_crtc_helper.h>
  16. #include <drm/drm_fb_cma_helper.h>
  17. #include <drm/drm_gem_cma_helper.h>
  18. #include <drm/drm_plane_helper.h>
  19. #include "fsl_dcu_drm_drv.h"
  20. #include "fsl_dcu_drm_plane.h"
  21. static int fsl_dcu_drm_plane_index(struct drm_plane *plane)
  22. {
  23. struct fsl_dcu_drm_device *fsl_dev = plane->dev->dev_private;
  24. unsigned int total_layer = fsl_dev->soc->total_layer;
  25. unsigned int index;
  26. index = drm_plane_index(plane);
  27. if (index < total_layer)
  28. return total_layer - index - 1;
  29. dev_err(fsl_dev->dev, "No more layer left\n");
  30. return -EINVAL;
  31. }
  32. static int fsl_dcu_drm_plane_atomic_check(struct drm_plane *plane,
  33. struct drm_plane_state *state)
  34. {
  35. struct drm_framebuffer *fb = state->fb;
  36. switch (fb->pixel_format) {
  37. case DRM_FORMAT_RGB565:
  38. case DRM_FORMAT_RGB888:
  39. case DRM_FORMAT_ARGB8888:
  40. case DRM_FORMAT_BGRA4444:
  41. case DRM_FORMAT_ARGB1555:
  42. case DRM_FORMAT_YUV422:
  43. return 0;
  44. default:
  45. return -EINVAL;
  46. }
  47. }
  48. static void fsl_dcu_drm_plane_atomic_disable(struct drm_plane *plane,
  49. struct drm_plane_state *old_state)
  50. {
  51. struct fsl_dcu_drm_device *fsl_dev = plane->dev->dev_private;
  52. unsigned int value;
  53. int index, ret;
  54. index = fsl_dcu_drm_plane_index(plane);
  55. if (index < 0)
  56. return;
  57. ret = regmap_read(fsl_dev->regmap, DCU_CTRLDESCLN(index, 4), &value);
  58. if (ret)
  59. dev_err(fsl_dev->dev, "read DCU_INT_MASK failed\n");
  60. value &= ~DCU_LAYER_EN;
  61. ret = regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 4), value);
  62. if (ret)
  63. dev_err(fsl_dev->dev, "set DCU register failed\n");
  64. }
  65. static void fsl_dcu_drm_plane_atomic_update(struct drm_plane *plane,
  66. struct drm_plane_state *old_state)
  67. {
  68. struct fsl_dcu_drm_device *fsl_dev = plane->dev->dev_private;
  69. struct drm_plane_state *state = plane->state;
  70. struct drm_framebuffer *fb = plane->state->fb;
  71. struct drm_gem_cma_object *gem;
  72. unsigned int alpha, bpp;
  73. int index, ret;
  74. if (!fb)
  75. return;
  76. index = fsl_dcu_drm_plane_index(plane);
  77. if (index < 0)
  78. return;
  79. gem = drm_fb_cma_get_gem_obj(fb, 0);
  80. switch (fb->pixel_format) {
  81. case DRM_FORMAT_RGB565:
  82. bpp = FSL_DCU_RGB565;
  83. alpha = 0xff;
  84. break;
  85. case DRM_FORMAT_RGB888:
  86. bpp = FSL_DCU_RGB888;
  87. alpha = 0xff;
  88. break;
  89. case DRM_FORMAT_ARGB8888:
  90. bpp = FSL_DCU_ARGB8888;
  91. alpha = 0xff;
  92. break;
  93. case DRM_FORMAT_BGRA4444:
  94. bpp = FSL_DCU_ARGB4444;
  95. alpha = 0xff;
  96. break;
  97. case DRM_FORMAT_ARGB1555:
  98. bpp = FSL_DCU_ARGB1555;
  99. alpha = 0xff;
  100. break;
  101. case DRM_FORMAT_YUV422:
  102. bpp = FSL_DCU_YUV422;
  103. alpha = 0xff;
  104. break;
  105. default:
  106. return;
  107. }
  108. ret = regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 1),
  109. DCU_LAYER_HEIGHT(state->crtc_h) |
  110. DCU_LAYER_WIDTH(state->crtc_w));
  111. if (ret)
  112. goto set_failed;
  113. ret = regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 2),
  114. DCU_LAYER_POSY(state->crtc_y) |
  115. DCU_LAYER_POSX(state->crtc_x));
  116. if (ret)
  117. goto set_failed;
  118. ret = regmap_write(fsl_dev->regmap,
  119. DCU_CTRLDESCLN(index, 3), gem->paddr);
  120. if (ret)
  121. goto set_failed;
  122. ret = regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 4),
  123. DCU_LAYER_EN |
  124. DCU_LAYER_TRANS(alpha) |
  125. DCU_LAYER_BPP(bpp) |
  126. DCU_LAYER_AB(0));
  127. if (ret)
  128. goto set_failed;
  129. ret = regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 5),
  130. DCU_LAYER_CKMAX_R(0xFF) |
  131. DCU_LAYER_CKMAX_G(0xFF) |
  132. DCU_LAYER_CKMAX_B(0xFF));
  133. if (ret)
  134. goto set_failed;
  135. ret = regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 6),
  136. DCU_LAYER_CKMIN_R(0) |
  137. DCU_LAYER_CKMIN_G(0) |
  138. DCU_LAYER_CKMIN_B(0));
  139. if (ret)
  140. goto set_failed;
  141. ret = regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 7), 0);
  142. if (ret)
  143. goto set_failed;
  144. ret = regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 8),
  145. DCU_LAYER_FG_FCOLOR(0));
  146. if (ret)
  147. goto set_failed;
  148. ret = regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 9),
  149. DCU_LAYER_BG_BCOLOR(0));
  150. if (ret)
  151. goto set_failed;
  152. if (!strcmp(fsl_dev->soc->name, "ls1021a")) {
  153. ret = regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 10),
  154. DCU_LAYER_POST_SKIP(0) |
  155. DCU_LAYER_PRE_SKIP(0));
  156. if (ret)
  157. goto set_failed;
  158. }
  159. ret = regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
  160. DCU_MODE_DCU_MODE_MASK,
  161. DCU_MODE_DCU_MODE(DCU_MODE_NORMAL));
  162. if (ret)
  163. goto set_failed;
  164. ret = regmap_write(fsl_dev->regmap,
  165. DCU_UPDATE_MODE, DCU_UPDATE_MODE_READREG);
  166. if (ret)
  167. goto set_failed;
  168. return;
  169. set_failed:
  170. dev_err(fsl_dev->dev, "set DCU register failed\n");
  171. }
  172. static void
  173. fsl_dcu_drm_plane_cleanup_fb(struct drm_plane *plane,
  174. const struct drm_plane_state *new_state)
  175. {
  176. }
  177. static int
  178. fsl_dcu_drm_plane_prepare_fb(struct drm_plane *plane,
  179. const struct drm_plane_state *new_state)
  180. {
  181. return 0;
  182. }
  183. static const struct drm_plane_helper_funcs fsl_dcu_drm_plane_helper_funcs = {
  184. .atomic_check = fsl_dcu_drm_plane_atomic_check,
  185. .atomic_disable = fsl_dcu_drm_plane_atomic_disable,
  186. .atomic_update = fsl_dcu_drm_plane_atomic_update,
  187. .cleanup_fb = fsl_dcu_drm_plane_cleanup_fb,
  188. .prepare_fb = fsl_dcu_drm_plane_prepare_fb,
  189. };
  190. static void fsl_dcu_drm_plane_destroy(struct drm_plane *plane)
  191. {
  192. drm_plane_cleanup(plane);
  193. }
  194. static const struct drm_plane_funcs fsl_dcu_drm_plane_funcs = {
  195. .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
  196. .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
  197. .destroy = fsl_dcu_drm_plane_destroy,
  198. .disable_plane = drm_atomic_helper_disable_plane,
  199. .reset = drm_atomic_helper_plane_reset,
  200. .update_plane = drm_atomic_helper_update_plane,
  201. };
  202. static const u32 fsl_dcu_drm_plane_formats[] = {
  203. DRM_FORMAT_RGB565,
  204. DRM_FORMAT_RGB888,
  205. DRM_FORMAT_ARGB8888,
  206. DRM_FORMAT_ARGB4444,
  207. DRM_FORMAT_ARGB1555,
  208. DRM_FORMAT_YUV422,
  209. };
  210. struct drm_plane *fsl_dcu_drm_primary_create_plane(struct drm_device *dev)
  211. {
  212. struct drm_plane *primary;
  213. int ret;
  214. primary = kzalloc(sizeof(*primary), GFP_KERNEL);
  215. if (!primary) {
  216. DRM_DEBUG_KMS("Failed to allocate primary plane\n");
  217. return NULL;
  218. }
  219. /* possible_crtc's will be filled in later by crtc_init */
  220. ret = drm_universal_plane_init(dev, primary, 0,
  221. &fsl_dcu_drm_plane_funcs,
  222. fsl_dcu_drm_plane_formats,
  223. ARRAY_SIZE(fsl_dcu_drm_plane_formats),
  224. DRM_PLANE_TYPE_PRIMARY);
  225. if (ret) {
  226. kfree(primary);
  227. primary = NULL;
  228. }
  229. drm_plane_helper_add(primary, &fsl_dcu_drm_plane_helper_funcs);
  230. return primary;
  231. }