hdmi_audio.c 8.4 KB

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  1. /*
  2. * Copyright (C) 2013 Red Hat
  3. * Author: Rob Clark <robdclark@gmail.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published by
  7. * the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program. If not, see <http://www.gnu.org/licenses/>.
  16. */
  17. #include <linux/hdmi.h>
  18. #include "hdmi.h"
  19. /* Supported HDMI Audio channels */
  20. #define MSM_HDMI_AUDIO_CHANNEL_2 0
  21. #define MSM_HDMI_AUDIO_CHANNEL_4 1
  22. #define MSM_HDMI_AUDIO_CHANNEL_6 2
  23. #define MSM_HDMI_AUDIO_CHANNEL_8 3
  24. /* maps MSM_HDMI_AUDIO_CHANNEL_n consts used by audio driver to # of channels: */
  25. static int nchannels[] = { 2, 4, 6, 8 };
  26. /* Supported HDMI Audio sample rates */
  27. #define MSM_HDMI_SAMPLE_RATE_32KHZ 0
  28. #define MSM_HDMI_SAMPLE_RATE_44_1KHZ 1
  29. #define MSM_HDMI_SAMPLE_RATE_48KHZ 2
  30. #define MSM_HDMI_SAMPLE_RATE_88_2KHZ 3
  31. #define MSM_HDMI_SAMPLE_RATE_96KHZ 4
  32. #define MSM_HDMI_SAMPLE_RATE_176_4KHZ 5
  33. #define MSM_HDMI_SAMPLE_RATE_192KHZ 6
  34. #define MSM_HDMI_SAMPLE_RATE_MAX 7
  35. struct hdmi_msm_audio_acr {
  36. uint32_t n; /* N parameter for clock regeneration */
  37. uint32_t cts; /* CTS parameter for clock regeneration */
  38. };
  39. struct hdmi_msm_audio_arcs {
  40. unsigned long int pixclock;
  41. struct hdmi_msm_audio_acr lut[MSM_HDMI_SAMPLE_RATE_MAX];
  42. };
  43. #define HDMI_MSM_AUDIO_ARCS(pclk, ...) { (1000 * (pclk)), __VA_ARGS__ }
  44. /* Audio constants lookup table for hdmi_msm_audio_acr_setup */
  45. /* Valid Pixel-Clock rates: 25.2MHz, 27MHz, 27.03MHz, 74.25MHz, 148.5MHz */
  46. static const struct hdmi_msm_audio_arcs acr_lut[] = {
  47. /* 25.200MHz */
  48. HDMI_MSM_AUDIO_ARCS(25200, {
  49. {4096, 25200}, {6272, 28000}, {6144, 25200}, {12544, 28000},
  50. {12288, 25200}, {25088, 28000}, {24576, 25200} }),
  51. /* 27.000MHz */
  52. HDMI_MSM_AUDIO_ARCS(27000, {
  53. {4096, 27000}, {6272, 30000}, {6144, 27000}, {12544, 30000},
  54. {12288, 27000}, {25088, 30000}, {24576, 27000} }),
  55. /* 27.027MHz */
  56. HDMI_MSM_AUDIO_ARCS(27030, {
  57. {4096, 27027}, {6272, 30030}, {6144, 27027}, {12544, 30030},
  58. {12288, 27027}, {25088, 30030}, {24576, 27027} }),
  59. /* 74.250MHz */
  60. HDMI_MSM_AUDIO_ARCS(74250, {
  61. {4096, 74250}, {6272, 82500}, {6144, 74250}, {12544, 82500},
  62. {12288, 74250}, {25088, 82500}, {24576, 74250} }),
  63. /* 148.500MHz */
  64. HDMI_MSM_AUDIO_ARCS(148500, {
  65. {4096, 148500}, {6272, 165000}, {6144, 148500}, {12544, 165000},
  66. {12288, 148500}, {25088, 165000}, {24576, 148500} }),
  67. };
  68. static const struct hdmi_msm_audio_arcs *get_arcs(unsigned long int pixclock)
  69. {
  70. int i;
  71. for (i = 0; i < ARRAY_SIZE(acr_lut); i++) {
  72. const struct hdmi_msm_audio_arcs *arcs = &acr_lut[i];
  73. if (arcs->pixclock == pixclock)
  74. return arcs;
  75. }
  76. return NULL;
  77. }
  78. int hdmi_audio_update(struct hdmi *hdmi)
  79. {
  80. struct hdmi_audio *audio = &hdmi->audio;
  81. struct hdmi_audio_infoframe *info = &audio->infoframe;
  82. const struct hdmi_msm_audio_arcs *arcs = NULL;
  83. bool enabled = audio->enabled;
  84. uint32_t acr_pkt_ctrl, vbi_pkt_ctrl, aud_pkt_ctrl;
  85. uint32_t infofrm_ctrl, audio_config;
  86. DBG("audio: enabled=%d, channels=%d, channel_allocation=0x%x, "
  87. "level_shift_value=%d, downmix_inhibit=%d, rate=%d",
  88. audio->enabled, info->channels, info->channel_allocation,
  89. info->level_shift_value, info->downmix_inhibit, audio->rate);
  90. DBG("video: power_on=%d, pixclock=%lu", hdmi->power_on, hdmi->pixclock);
  91. if (enabled && !(hdmi->power_on && hdmi->pixclock)) {
  92. DBG("disabling audio: no video");
  93. enabled = false;
  94. }
  95. if (enabled) {
  96. arcs = get_arcs(hdmi->pixclock);
  97. if (!arcs) {
  98. DBG("disabling audio: unsupported pixclock: %lu",
  99. hdmi->pixclock);
  100. enabled = false;
  101. }
  102. }
  103. /* Read first before writing */
  104. acr_pkt_ctrl = hdmi_read(hdmi, REG_HDMI_ACR_PKT_CTRL);
  105. vbi_pkt_ctrl = hdmi_read(hdmi, REG_HDMI_VBI_PKT_CTRL);
  106. aud_pkt_ctrl = hdmi_read(hdmi, REG_HDMI_AUDIO_PKT_CTRL1);
  107. infofrm_ctrl = hdmi_read(hdmi, REG_HDMI_INFOFRAME_CTRL0);
  108. audio_config = hdmi_read(hdmi, REG_HDMI_AUDIO_CFG);
  109. /* Clear N/CTS selection bits */
  110. acr_pkt_ctrl &= ~HDMI_ACR_PKT_CTRL_SELECT__MASK;
  111. if (enabled) {
  112. uint32_t n, cts, multiplier;
  113. enum hdmi_acr_cts select;
  114. uint8_t buf[14];
  115. n = arcs->lut[audio->rate].n;
  116. cts = arcs->lut[audio->rate].cts;
  117. if ((MSM_HDMI_SAMPLE_RATE_192KHZ == audio->rate) ||
  118. (MSM_HDMI_SAMPLE_RATE_176_4KHZ == audio->rate)) {
  119. multiplier = 4;
  120. n >>= 2; /* divide N by 4 and use multiplier */
  121. } else if ((MSM_HDMI_SAMPLE_RATE_96KHZ == audio->rate) ||
  122. (MSM_HDMI_SAMPLE_RATE_88_2KHZ == audio->rate)) {
  123. multiplier = 2;
  124. n >>= 1; /* divide N by 2 and use multiplier */
  125. } else {
  126. multiplier = 1;
  127. }
  128. DBG("n=%u, cts=%u, multiplier=%u", n, cts, multiplier);
  129. acr_pkt_ctrl |= HDMI_ACR_PKT_CTRL_SOURCE;
  130. acr_pkt_ctrl |= HDMI_ACR_PKT_CTRL_AUDIO_PRIORITY;
  131. acr_pkt_ctrl |= HDMI_ACR_PKT_CTRL_N_MULTIPLIER(multiplier);
  132. if ((MSM_HDMI_SAMPLE_RATE_48KHZ == audio->rate) ||
  133. (MSM_HDMI_SAMPLE_RATE_96KHZ == audio->rate) ||
  134. (MSM_HDMI_SAMPLE_RATE_192KHZ == audio->rate))
  135. select = ACR_48;
  136. else if ((MSM_HDMI_SAMPLE_RATE_44_1KHZ == audio->rate) ||
  137. (MSM_HDMI_SAMPLE_RATE_88_2KHZ == audio->rate) ||
  138. (MSM_HDMI_SAMPLE_RATE_176_4KHZ == audio->rate))
  139. select = ACR_44;
  140. else /* default to 32k */
  141. select = ACR_32;
  142. acr_pkt_ctrl |= HDMI_ACR_PKT_CTRL_SELECT(select);
  143. hdmi_write(hdmi, REG_HDMI_ACR_0(select - 1),
  144. HDMI_ACR_0_CTS(cts));
  145. hdmi_write(hdmi, REG_HDMI_ACR_1(select - 1),
  146. HDMI_ACR_1_N(n));
  147. hdmi_write(hdmi, REG_HDMI_AUDIO_PKT_CTRL2,
  148. COND(info->channels != 2, HDMI_AUDIO_PKT_CTRL2_LAYOUT) |
  149. HDMI_AUDIO_PKT_CTRL2_OVERRIDE);
  150. acr_pkt_ctrl |= HDMI_ACR_PKT_CTRL_CONT;
  151. acr_pkt_ctrl |= HDMI_ACR_PKT_CTRL_SEND;
  152. /* configure infoframe: */
  153. hdmi_audio_infoframe_pack(info, buf, sizeof(buf));
  154. hdmi_write(hdmi, REG_HDMI_AUDIO_INFO0,
  155. (buf[3] << 0) || (buf[4] << 8) ||
  156. (buf[5] << 16) || (buf[6] << 24));
  157. hdmi_write(hdmi, REG_HDMI_AUDIO_INFO1,
  158. (buf[7] << 0) || (buf[8] << 8));
  159. hdmi_write(hdmi, REG_HDMI_GC, 0);
  160. vbi_pkt_ctrl |= HDMI_VBI_PKT_CTRL_GC_ENABLE;
  161. vbi_pkt_ctrl |= HDMI_VBI_PKT_CTRL_GC_EVERY_FRAME;
  162. aud_pkt_ctrl |= HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND;
  163. infofrm_ctrl |= HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SEND;
  164. infofrm_ctrl |= HDMI_INFOFRAME_CTRL0_AUDIO_INFO_CONT;
  165. infofrm_ctrl |= HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SOURCE;
  166. infofrm_ctrl |= HDMI_INFOFRAME_CTRL0_AUDIO_INFO_UPDATE;
  167. audio_config &= ~HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK;
  168. audio_config |= HDMI_AUDIO_CFG_FIFO_WATERMARK(4);
  169. audio_config |= HDMI_AUDIO_CFG_ENGINE_ENABLE;
  170. } else {
  171. acr_pkt_ctrl &= ~HDMI_ACR_PKT_CTRL_CONT;
  172. acr_pkt_ctrl &= ~HDMI_ACR_PKT_CTRL_SEND;
  173. vbi_pkt_ctrl &= ~HDMI_VBI_PKT_CTRL_GC_ENABLE;
  174. vbi_pkt_ctrl &= ~HDMI_VBI_PKT_CTRL_GC_EVERY_FRAME;
  175. aud_pkt_ctrl &= ~HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND;
  176. infofrm_ctrl &= ~HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SEND;
  177. infofrm_ctrl &= ~HDMI_INFOFRAME_CTRL0_AUDIO_INFO_CONT;
  178. infofrm_ctrl &= ~HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SOURCE;
  179. infofrm_ctrl &= ~HDMI_INFOFRAME_CTRL0_AUDIO_INFO_UPDATE;
  180. audio_config &= ~HDMI_AUDIO_CFG_ENGINE_ENABLE;
  181. }
  182. hdmi_write(hdmi, REG_HDMI_ACR_PKT_CTRL, acr_pkt_ctrl);
  183. hdmi_write(hdmi, REG_HDMI_VBI_PKT_CTRL, vbi_pkt_ctrl);
  184. hdmi_write(hdmi, REG_HDMI_AUDIO_PKT_CTRL1, aud_pkt_ctrl);
  185. hdmi_write(hdmi, REG_HDMI_INFOFRAME_CTRL0, infofrm_ctrl);
  186. hdmi_write(hdmi, REG_HDMI_AUD_INT,
  187. COND(enabled, HDMI_AUD_INT_AUD_FIFO_URUN_INT) |
  188. COND(enabled, HDMI_AUD_INT_AUD_SAM_DROP_INT));
  189. hdmi_write(hdmi, REG_HDMI_AUDIO_CFG, audio_config);
  190. DBG("audio %sabled", enabled ? "en" : "dis");
  191. return 0;
  192. }
  193. int hdmi_audio_info_setup(struct hdmi *hdmi, bool enabled,
  194. uint32_t num_of_channels, uint32_t channel_allocation,
  195. uint32_t level_shift, bool down_mix)
  196. {
  197. struct hdmi_audio *audio;
  198. if (!hdmi)
  199. return -ENXIO;
  200. audio = &hdmi->audio;
  201. if (num_of_channels >= ARRAY_SIZE(nchannels))
  202. return -EINVAL;
  203. audio->enabled = enabled;
  204. audio->infoframe.channels = nchannels[num_of_channels];
  205. audio->infoframe.channel_allocation = channel_allocation;
  206. audio->infoframe.level_shift_value = level_shift;
  207. audio->infoframe.downmix_inhibit = down_mix;
  208. return hdmi_audio_update(hdmi);
  209. }
  210. void hdmi_audio_set_sample_rate(struct hdmi *hdmi, int rate)
  211. {
  212. struct hdmi_audio *audio;
  213. if (!hdmi)
  214. return;
  215. audio = &hdmi->audio;
  216. if ((rate < 0) || (rate >= MSM_HDMI_SAMPLE_RATE_MAX))
  217. return;
  218. audio->rate = rate;
  219. hdmi_audio_update(hdmi);
  220. }