hdmi_i2c.c 6.5 KB

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  1. /*
  2. * Copyright (C) 2013 Red Hat
  3. * Author: Rob Clark <robdclark@gmail.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published by
  7. * the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program. If not, see <http://www.gnu.org/licenses/>.
  16. */
  17. #include "hdmi.h"
  18. struct hdmi_i2c_adapter {
  19. struct i2c_adapter base;
  20. struct hdmi *hdmi;
  21. bool sw_done;
  22. wait_queue_head_t ddc_event;
  23. };
  24. #define to_hdmi_i2c_adapter(x) container_of(x, struct hdmi_i2c_adapter, base)
  25. static void init_ddc(struct hdmi_i2c_adapter *hdmi_i2c)
  26. {
  27. struct hdmi *hdmi = hdmi_i2c->hdmi;
  28. hdmi_write(hdmi, REG_HDMI_DDC_CTRL,
  29. HDMI_DDC_CTRL_SW_STATUS_RESET);
  30. hdmi_write(hdmi, REG_HDMI_DDC_CTRL,
  31. HDMI_DDC_CTRL_SOFT_RESET);
  32. hdmi_write(hdmi, REG_HDMI_DDC_SPEED,
  33. HDMI_DDC_SPEED_THRESHOLD(2) |
  34. HDMI_DDC_SPEED_PRESCALE(10));
  35. hdmi_write(hdmi, REG_HDMI_DDC_SETUP,
  36. HDMI_DDC_SETUP_TIMEOUT(0xff));
  37. /* enable reference timer for 27us */
  38. hdmi_write(hdmi, REG_HDMI_DDC_REF,
  39. HDMI_DDC_REF_REFTIMER_ENABLE |
  40. HDMI_DDC_REF_REFTIMER(27));
  41. }
  42. static int ddc_clear_irq(struct hdmi_i2c_adapter *hdmi_i2c)
  43. {
  44. struct hdmi *hdmi = hdmi_i2c->hdmi;
  45. struct drm_device *dev = hdmi->dev;
  46. uint32_t retry = 0xffff;
  47. uint32_t ddc_int_ctrl;
  48. do {
  49. --retry;
  50. hdmi_write(hdmi, REG_HDMI_DDC_INT_CTRL,
  51. HDMI_DDC_INT_CTRL_SW_DONE_ACK |
  52. HDMI_DDC_INT_CTRL_SW_DONE_MASK);
  53. ddc_int_ctrl = hdmi_read(hdmi, REG_HDMI_DDC_INT_CTRL);
  54. } while ((ddc_int_ctrl & HDMI_DDC_INT_CTRL_SW_DONE_INT) && retry);
  55. if (!retry) {
  56. dev_err(dev->dev, "timeout waiting for DDC\n");
  57. return -ETIMEDOUT;
  58. }
  59. hdmi_i2c->sw_done = false;
  60. return 0;
  61. }
  62. #define MAX_TRANSACTIONS 4
  63. static bool sw_done(struct hdmi_i2c_adapter *hdmi_i2c)
  64. {
  65. struct hdmi *hdmi = hdmi_i2c->hdmi;
  66. if (!hdmi_i2c->sw_done) {
  67. uint32_t ddc_int_ctrl;
  68. ddc_int_ctrl = hdmi_read(hdmi, REG_HDMI_DDC_INT_CTRL);
  69. if ((ddc_int_ctrl & HDMI_DDC_INT_CTRL_SW_DONE_MASK) &&
  70. (ddc_int_ctrl & HDMI_DDC_INT_CTRL_SW_DONE_INT)) {
  71. hdmi_i2c->sw_done = true;
  72. hdmi_write(hdmi, REG_HDMI_DDC_INT_CTRL,
  73. HDMI_DDC_INT_CTRL_SW_DONE_ACK);
  74. }
  75. }
  76. return hdmi_i2c->sw_done;
  77. }
  78. static int hdmi_i2c_xfer(struct i2c_adapter *i2c,
  79. struct i2c_msg *msgs, int num)
  80. {
  81. struct hdmi_i2c_adapter *hdmi_i2c = to_hdmi_i2c_adapter(i2c);
  82. struct hdmi *hdmi = hdmi_i2c->hdmi;
  83. struct drm_device *dev = hdmi->dev;
  84. static const uint32_t nack[] = {
  85. HDMI_DDC_SW_STATUS_NACK0, HDMI_DDC_SW_STATUS_NACK1,
  86. HDMI_DDC_SW_STATUS_NACK2, HDMI_DDC_SW_STATUS_NACK3,
  87. };
  88. int indices[MAX_TRANSACTIONS];
  89. int ret, i, j, index = 0;
  90. uint32_t ddc_status, ddc_data, i2c_trans;
  91. num = min(num, MAX_TRANSACTIONS);
  92. WARN_ON(!(hdmi_read(hdmi, REG_HDMI_CTRL) & HDMI_CTRL_ENABLE));
  93. if (num == 0)
  94. return num;
  95. init_ddc(hdmi_i2c);
  96. ret = ddc_clear_irq(hdmi_i2c);
  97. if (ret)
  98. return ret;
  99. for (i = 0; i < num; i++) {
  100. struct i2c_msg *p = &msgs[i];
  101. uint32_t raw_addr = p->addr << 1;
  102. if (p->flags & I2C_M_RD)
  103. raw_addr |= 1;
  104. ddc_data = HDMI_DDC_DATA_DATA(raw_addr) |
  105. HDMI_DDC_DATA_DATA_RW(DDC_WRITE);
  106. if (i == 0) {
  107. ddc_data |= HDMI_DDC_DATA_INDEX(0) |
  108. HDMI_DDC_DATA_INDEX_WRITE;
  109. }
  110. hdmi_write(hdmi, REG_HDMI_DDC_DATA, ddc_data);
  111. index++;
  112. indices[i] = index;
  113. if (p->flags & I2C_M_RD) {
  114. index += p->len;
  115. } else {
  116. for (j = 0; j < p->len; j++) {
  117. ddc_data = HDMI_DDC_DATA_DATA(p->buf[j]) |
  118. HDMI_DDC_DATA_DATA_RW(DDC_WRITE);
  119. hdmi_write(hdmi, REG_HDMI_DDC_DATA, ddc_data);
  120. index++;
  121. }
  122. }
  123. i2c_trans = HDMI_I2C_TRANSACTION_REG_CNT(p->len) |
  124. HDMI_I2C_TRANSACTION_REG_RW(
  125. (p->flags & I2C_M_RD) ? DDC_READ : DDC_WRITE) |
  126. HDMI_I2C_TRANSACTION_REG_START;
  127. if (i == (num - 1))
  128. i2c_trans |= HDMI_I2C_TRANSACTION_REG_STOP;
  129. hdmi_write(hdmi, REG_HDMI_I2C_TRANSACTION(i), i2c_trans);
  130. }
  131. /* trigger the transfer: */
  132. hdmi_write(hdmi, REG_HDMI_DDC_CTRL,
  133. HDMI_DDC_CTRL_TRANSACTION_CNT(num - 1) |
  134. HDMI_DDC_CTRL_GO);
  135. ret = wait_event_timeout(hdmi_i2c->ddc_event, sw_done(hdmi_i2c), HZ/4);
  136. if (ret <= 0) {
  137. if (ret == 0)
  138. ret = -ETIMEDOUT;
  139. dev_warn(dev->dev, "DDC timeout: %d\n", ret);
  140. DBG("sw_status=%08x, hw_status=%08x, int_ctrl=%08x",
  141. hdmi_read(hdmi, REG_HDMI_DDC_SW_STATUS),
  142. hdmi_read(hdmi, REG_HDMI_DDC_HW_STATUS),
  143. hdmi_read(hdmi, REG_HDMI_DDC_INT_CTRL));
  144. return ret;
  145. }
  146. ddc_status = hdmi_read(hdmi, REG_HDMI_DDC_SW_STATUS);
  147. /* read back results of any read transactions: */
  148. for (i = 0; i < num; i++) {
  149. struct i2c_msg *p = &msgs[i];
  150. if (!(p->flags & I2C_M_RD))
  151. continue;
  152. /* check for NACK: */
  153. if (ddc_status & nack[i]) {
  154. DBG("ddc_status=%08x", ddc_status);
  155. break;
  156. }
  157. ddc_data = HDMI_DDC_DATA_DATA_RW(DDC_READ) |
  158. HDMI_DDC_DATA_INDEX(indices[i]) |
  159. HDMI_DDC_DATA_INDEX_WRITE;
  160. hdmi_write(hdmi, REG_HDMI_DDC_DATA, ddc_data);
  161. /* discard first byte: */
  162. hdmi_read(hdmi, REG_HDMI_DDC_DATA);
  163. for (j = 0; j < p->len; j++) {
  164. ddc_data = hdmi_read(hdmi, REG_HDMI_DDC_DATA);
  165. p->buf[j] = FIELD(ddc_data, HDMI_DDC_DATA_DATA);
  166. }
  167. }
  168. return i;
  169. }
  170. static u32 hdmi_i2c_func(struct i2c_adapter *adapter)
  171. {
  172. return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
  173. }
  174. static const struct i2c_algorithm hdmi_i2c_algorithm = {
  175. .master_xfer = hdmi_i2c_xfer,
  176. .functionality = hdmi_i2c_func,
  177. };
  178. void hdmi_i2c_irq(struct i2c_adapter *i2c)
  179. {
  180. struct hdmi_i2c_adapter *hdmi_i2c = to_hdmi_i2c_adapter(i2c);
  181. if (sw_done(hdmi_i2c))
  182. wake_up_all(&hdmi_i2c->ddc_event);
  183. }
  184. void hdmi_i2c_destroy(struct i2c_adapter *i2c)
  185. {
  186. struct hdmi_i2c_adapter *hdmi_i2c = to_hdmi_i2c_adapter(i2c);
  187. i2c_del_adapter(i2c);
  188. kfree(hdmi_i2c);
  189. }
  190. struct i2c_adapter *hdmi_i2c_init(struct hdmi *hdmi)
  191. {
  192. struct drm_device *dev = hdmi->dev;
  193. struct hdmi_i2c_adapter *hdmi_i2c;
  194. struct i2c_adapter *i2c = NULL;
  195. int ret;
  196. hdmi_i2c = kzalloc(sizeof(*hdmi_i2c), GFP_KERNEL);
  197. if (!hdmi_i2c) {
  198. ret = -ENOMEM;
  199. goto fail;
  200. }
  201. i2c = &hdmi_i2c->base;
  202. hdmi_i2c->hdmi = hdmi;
  203. init_waitqueue_head(&hdmi_i2c->ddc_event);
  204. i2c->owner = THIS_MODULE;
  205. i2c->class = I2C_CLASS_DDC;
  206. snprintf(i2c->name, sizeof(i2c->name), "msm hdmi i2c");
  207. i2c->dev.parent = &hdmi->pdev->dev;
  208. i2c->algo = &hdmi_i2c_algorithm;
  209. ret = i2c_add_adapter(i2c);
  210. if (ret) {
  211. dev_err(dev->dev, "failed to register hdmi i2c: %d\n", ret);
  212. goto fail;
  213. }
  214. return i2c;
  215. fail:
  216. if (i2c)
  217. hdmi_i2c_destroy(i2c);
  218. return ERR_PTR(ret);
  219. }