mdp4_kms.c 15 KB

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  1. /*
  2. * Copyright (C) 2013 Red Hat
  3. * Author: Rob Clark <robdclark@gmail.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published by
  7. * the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program. If not, see <http://www.gnu.org/licenses/>.
  16. */
  17. #include "msm_drv.h"
  18. #include "msm_mmu.h"
  19. #include "mdp4_kms.h"
  20. static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev);
  21. static int mdp4_hw_init(struct msm_kms *kms)
  22. {
  23. struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
  24. struct drm_device *dev = mdp4_kms->dev;
  25. uint32_t version, major, minor, dmap_cfg, vg_cfg;
  26. unsigned long clk;
  27. int ret = 0;
  28. pm_runtime_get_sync(dev->dev);
  29. mdp4_enable(mdp4_kms);
  30. version = mdp4_read(mdp4_kms, REG_MDP4_VERSION);
  31. mdp4_disable(mdp4_kms);
  32. major = FIELD(version, MDP4_VERSION_MAJOR);
  33. minor = FIELD(version, MDP4_VERSION_MINOR);
  34. DBG("found MDP4 version v%d.%d", major, minor);
  35. if (major != 4) {
  36. dev_err(dev->dev, "unexpected MDP version: v%d.%d\n",
  37. major, minor);
  38. ret = -ENXIO;
  39. goto out;
  40. }
  41. mdp4_kms->rev = minor;
  42. if (mdp4_kms->dsi_pll_vdda) {
  43. if ((mdp4_kms->rev == 2) || (mdp4_kms->rev == 4)) {
  44. ret = regulator_set_voltage(mdp4_kms->dsi_pll_vdda,
  45. 1200000, 1200000);
  46. if (ret) {
  47. dev_err(dev->dev,
  48. "failed to set dsi_pll_vdda voltage: %d\n", ret);
  49. goto out;
  50. }
  51. }
  52. }
  53. if (mdp4_kms->dsi_pll_vddio) {
  54. if (mdp4_kms->rev == 2) {
  55. ret = regulator_set_voltage(mdp4_kms->dsi_pll_vddio,
  56. 1800000, 1800000);
  57. if (ret) {
  58. dev_err(dev->dev,
  59. "failed to set dsi_pll_vddio voltage: %d\n", ret);
  60. goto out;
  61. }
  62. }
  63. }
  64. if (mdp4_kms->rev > 1) {
  65. mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff);
  66. mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f);
  67. }
  68. mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3);
  69. /* max read pending cmd config, 3 pending requests: */
  70. mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222);
  71. clk = clk_get_rate(mdp4_kms->clk);
  72. if ((mdp4_kms->rev >= 1) || (clk >= 90000000)) {
  73. dmap_cfg = 0x47; /* 16 bytes-burst x 8 req */
  74. vg_cfg = 0x47; /* 16 bytes-burs x 8 req */
  75. } else {
  76. dmap_cfg = 0x27; /* 8 bytes-burst x 8 req */
  77. vg_cfg = 0x43; /* 16 bytes-burst x 4 req */
  78. }
  79. DBG("fetch config: dmap=%02x, vg=%02x", dmap_cfg, vg_cfg);
  80. mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg);
  81. mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg);
  82. mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg);
  83. mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg);
  84. mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg);
  85. mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg);
  86. if (mdp4_kms->rev >= 2)
  87. mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD, 1);
  88. mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, 0);
  89. /* disable CSC matrix / YUV by default: */
  90. mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG1), 0);
  91. mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG2), 0);
  92. mdp4_write(mdp4_kms, REG_MDP4_DMA_P_OP_MODE, 0);
  93. mdp4_write(mdp4_kms, REG_MDP4_DMA_S_OP_MODE, 0);
  94. mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(1), 0);
  95. mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(2), 0);
  96. if (mdp4_kms->rev > 1)
  97. mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1);
  98. dev->mode_config.allow_fb_modifiers = true;
  99. out:
  100. pm_runtime_put_sync(dev->dev);
  101. return ret;
  102. }
  103. static void mdp4_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state)
  104. {
  105. struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
  106. int i, ncrtcs = state->dev->mode_config.num_crtc;
  107. mdp4_enable(mdp4_kms);
  108. /* see 119ecb7fd */
  109. for (i = 0; i < ncrtcs; i++) {
  110. struct drm_crtc *crtc = state->crtcs[i];
  111. if (!crtc)
  112. continue;
  113. drm_crtc_vblank_get(crtc);
  114. }
  115. }
  116. static void mdp4_complete_commit(struct msm_kms *kms, struct drm_atomic_state *state)
  117. {
  118. struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
  119. int i, ncrtcs = state->dev->mode_config.num_crtc;
  120. /* see 119ecb7fd */
  121. for (i = 0; i < ncrtcs; i++) {
  122. struct drm_crtc *crtc = state->crtcs[i];
  123. if (!crtc)
  124. continue;
  125. drm_crtc_vblank_put(crtc);
  126. }
  127. mdp4_disable(mdp4_kms);
  128. }
  129. static void mdp4_wait_for_crtc_commit_done(struct msm_kms *kms,
  130. struct drm_crtc *crtc)
  131. {
  132. mdp4_crtc_wait_for_commit_done(crtc);
  133. }
  134. static long mdp4_round_pixclk(struct msm_kms *kms, unsigned long rate,
  135. struct drm_encoder *encoder)
  136. {
  137. /* if we had >1 encoder, we'd need something more clever: */
  138. return mdp4_dtv_round_pixclk(encoder, rate);
  139. }
  140. static void mdp4_preclose(struct msm_kms *kms, struct drm_file *file)
  141. {
  142. struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
  143. struct msm_drm_private *priv = mdp4_kms->dev->dev_private;
  144. unsigned i;
  145. for (i = 0; i < priv->num_crtcs; i++)
  146. mdp4_crtc_cancel_pending_flip(priv->crtcs[i], file);
  147. }
  148. static void mdp4_destroy(struct msm_kms *kms)
  149. {
  150. struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
  151. if (mdp4_kms->blank_cursor_iova)
  152. msm_gem_put_iova(mdp4_kms->blank_cursor_bo, mdp4_kms->id);
  153. if (mdp4_kms->blank_cursor_bo)
  154. drm_gem_object_unreference_unlocked(mdp4_kms->blank_cursor_bo);
  155. kfree(mdp4_kms);
  156. }
  157. static const struct mdp_kms_funcs kms_funcs = {
  158. .base = {
  159. .hw_init = mdp4_hw_init,
  160. .irq_preinstall = mdp4_irq_preinstall,
  161. .irq_postinstall = mdp4_irq_postinstall,
  162. .irq_uninstall = mdp4_irq_uninstall,
  163. .irq = mdp4_irq,
  164. .enable_vblank = mdp4_enable_vblank,
  165. .disable_vblank = mdp4_disable_vblank,
  166. .prepare_commit = mdp4_prepare_commit,
  167. .complete_commit = mdp4_complete_commit,
  168. .wait_for_crtc_commit_done = mdp4_wait_for_crtc_commit_done,
  169. .get_format = mdp_get_format,
  170. .round_pixclk = mdp4_round_pixclk,
  171. .preclose = mdp4_preclose,
  172. .destroy = mdp4_destroy,
  173. },
  174. .set_irqmask = mdp4_set_irqmask,
  175. };
  176. int mdp4_disable(struct mdp4_kms *mdp4_kms)
  177. {
  178. DBG("");
  179. clk_disable_unprepare(mdp4_kms->clk);
  180. if (mdp4_kms->pclk)
  181. clk_disable_unprepare(mdp4_kms->pclk);
  182. clk_disable_unprepare(mdp4_kms->lut_clk);
  183. if (mdp4_kms->axi_clk)
  184. clk_disable_unprepare(mdp4_kms->axi_clk);
  185. return 0;
  186. }
  187. int mdp4_enable(struct mdp4_kms *mdp4_kms)
  188. {
  189. DBG("");
  190. clk_prepare_enable(mdp4_kms->clk);
  191. if (mdp4_kms->pclk)
  192. clk_prepare_enable(mdp4_kms->pclk);
  193. clk_prepare_enable(mdp4_kms->lut_clk);
  194. if (mdp4_kms->axi_clk)
  195. clk_prepare_enable(mdp4_kms->axi_clk);
  196. return 0;
  197. }
  198. #ifdef CONFIG_OF
  199. static struct drm_panel *detect_panel(struct drm_device *dev)
  200. {
  201. struct device_node *endpoint, *panel_node;
  202. struct device_node *np = dev->dev->of_node;
  203. struct drm_panel *panel = NULL;
  204. endpoint = of_graph_get_next_endpoint(np, NULL);
  205. if (!endpoint) {
  206. dev_err(dev->dev, "no valid endpoint\n");
  207. return ERR_PTR(-ENODEV);
  208. }
  209. panel_node = of_graph_get_remote_port_parent(endpoint);
  210. if (!panel_node) {
  211. dev_err(dev->dev, "no valid panel node\n");
  212. of_node_put(endpoint);
  213. return ERR_PTR(-ENODEV);
  214. }
  215. of_node_put(endpoint);
  216. panel = of_drm_find_panel(panel_node);
  217. if (!panel) {
  218. of_node_put(panel_node);
  219. return ERR_PTR(-EPROBE_DEFER);
  220. }
  221. return panel;
  222. }
  223. #else
  224. static struct drm_panel *detect_panel(struct drm_device *dev)
  225. {
  226. // ??? maybe use a module param to specify which panel is attached?
  227. }
  228. #endif
  229. static int modeset_init(struct mdp4_kms *mdp4_kms)
  230. {
  231. struct drm_device *dev = mdp4_kms->dev;
  232. struct msm_drm_private *priv = dev->dev_private;
  233. struct drm_plane *plane;
  234. struct drm_crtc *crtc;
  235. struct drm_encoder *encoder;
  236. struct drm_connector *connector;
  237. struct drm_panel *panel;
  238. int ret;
  239. /* construct non-private planes: */
  240. plane = mdp4_plane_init(dev, VG1, false);
  241. if (IS_ERR(plane)) {
  242. dev_err(dev->dev, "failed to construct plane for VG1\n");
  243. ret = PTR_ERR(plane);
  244. goto fail;
  245. }
  246. priv->planes[priv->num_planes++] = plane;
  247. plane = mdp4_plane_init(dev, VG2, false);
  248. if (IS_ERR(plane)) {
  249. dev_err(dev->dev, "failed to construct plane for VG2\n");
  250. ret = PTR_ERR(plane);
  251. goto fail;
  252. }
  253. priv->planes[priv->num_planes++] = plane;
  254. /*
  255. * Setup the LCDC/LVDS path: RGB2 -> DMA_P -> LCDC -> LVDS:
  256. */
  257. panel = detect_panel(dev);
  258. if (IS_ERR(panel)) {
  259. ret = PTR_ERR(panel);
  260. dev_err(dev->dev, "failed to detect LVDS panel: %d\n", ret);
  261. goto fail;
  262. }
  263. plane = mdp4_plane_init(dev, RGB2, true);
  264. if (IS_ERR(plane)) {
  265. dev_err(dev->dev, "failed to construct plane for RGB2\n");
  266. ret = PTR_ERR(plane);
  267. goto fail;
  268. }
  269. crtc = mdp4_crtc_init(dev, plane, priv->num_crtcs, 0, DMA_P);
  270. if (IS_ERR(crtc)) {
  271. dev_err(dev->dev, "failed to construct crtc for DMA_P\n");
  272. ret = PTR_ERR(crtc);
  273. goto fail;
  274. }
  275. encoder = mdp4_lcdc_encoder_init(dev, panel);
  276. if (IS_ERR(encoder)) {
  277. dev_err(dev->dev, "failed to construct LCDC encoder\n");
  278. ret = PTR_ERR(encoder);
  279. goto fail;
  280. }
  281. /* LCDC can be hooked to DMA_P: */
  282. encoder->possible_crtcs = 1 << priv->num_crtcs;
  283. priv->crtcs[priv->num_crtcs++] = crtc;
  284. priv->encoders[priv->num_encoders++] = encoder;
  285. connector = mdp4_lvds_connector_init(dev, panel, encoder);
  286. if (IS_ERR(connector)) {
  287. ret = PTR_ERR(connector);
  288. dev_err(dev->dev, "failed to initialize LVDS connector: %d\n", ret);
  289. goto fail;
  290. }
  291. priv->connectors[priv->num_connectors++] = connector;
  292. /*
  293. * Setup DTV/HDMI path: RGB1 -> DMA_E -> DTV -> HDMI:
  294. */
  295. plane = mdp4_plane_init(dev, RGB1, true);
  296. if (IS_ERR(plane)) {
  297. dev_err(dev->dev, "failed to construct plane for RGB1\n");
  298. ret = PTR_ERR(plane);
  299. goto fail;
  300. }
  301. crtc = mdp4_crtc_init(dev, plane, priv->num_crtcs, 1, DMA_E);
  302. if (IS_ERR(crtc)) {
  303. dev_err(dev->dev, "failed to construct crtc for DMA_E\n");
  304. ret = PTR_ERR(crtc);
  305. goto fail;
  306. }
  307. encoder = mdp4_dtv_encoder_init(dev);
  308. if (IS_ERR(encoder)) {
  309. dev_err(dev->dev, "failed to construct DTV encoder\n");
  310. ret = PTR_ERR(encoder);
  311. goto fail;
  312. }
  313. /* DTV can be hooked to DMA_E: */
  314. encoder->possible_crtcs = 1 << priv->num_crtcs;
  315. priv->crtcs[priv->num_crtcs++] = crtc;
  316. priv->encoders[priv->num_encoders++] = encoder;
  317. if (priv->hdmi) {
  318. /* Construct bridge/connector for HDMI: */
  319. ret = hdmi_modeset_init(priv->hdmi, dev, encoder);
  320. if (ret) {
  321. dev_err(dev->dev, "failed to initialize HDMI: %d\n", ret);
  322. goto fail;
  323. }
  324. }
  325. return 0;
  326. fail:
  327. return ret;
  328. }
  329. static const char *iommu_ports[] = {
  330. "mdp_port0_cb0", "mdp_port1_cb0",
  331. };
  332. struct msm_kms *mdp4_kms_init(struct drm_device *dev)
  333. {
  334. struct platform_device *pdev = dev->platformdev;
  335. struct mdp4_platform_config *config = mdp4_get_config(pdev);
  336. struct mdp4_kms *mdp4_kms;
  337. struct msm_kms *kms = NULL;
  338. struct msm_mmu *mmu;
  339. int ret;
  340. mdp4_kms = kzalloc(sizeof(*mdp4_kms), GFP_KERNEL);
  341. if (!mdp4_kms) {
  342. dev_err(dev->dev, "failed to allocate kms\n");
  343. ret = -ENOMEM;
  344. goto fail;
  345. }
  346. mdp_kms_init(&mdp4_kms->base, &kms_funcs);
  347. kms = &mdp4_kms->base.base;
  348. mdp4_kms->dev = dev;
  349. mdp4_kms->mmio = msm_ioremap(pdev, NULL, "MDP4");
  350. if (IS_ERR(mdp4_kms->mmio)) {
  351. ret = PTR_ERR(mdp4_kms->mmio);
  352. goto fail;
  353. }
  354. mdp4_kms->dsi_pll_vdda =
  355. devm_regulator_get_optional(&pdev->dev, "dsi_pll_vdda");
  356. if (IS_ERR(mdp4_kms->dsi_pll_vdda))
  357. mdp4_kms->dsi_pll_vdda = NULL;
  358. mdp4_kms->dsi_pll_vddio =
  359. devm_regulator_get_optional(&pdev->dev, "dsi_pll_vddio");
  360. if (IS_ERR(mdp4_kms->dsi_pll_vddio))
  361. mdp4_kms->dsi_pll_vddio = NULL;
  362. /* NOTE: driver for this regulator still missing upstream.. use
  363. * _get_exclusive() and ignore the error if it does not exist
  364. * (and hope that the bootloader left it on for us)
  365. */
  366. mdp4_kms->vdd = devm_regulator_get_exclusive(&pdev->dev, "vdd");
  367. if (IS_ERR(mdp4_kms->vdd))
  368. mdp4_kms->vdd = NULL;
  369. if (mdp4_kms->vdd) {
  370. ret = regulator_enable(mdp4_kms->vdd);
  371. if (ret) {
  372. dev_err(dev->dev, "failed to enable regulator vdd: %d\n", ret);
  373. goto fail;
  374. }
  375. }
  376. mdp4_kms->clk = devm_clk_get(&pdev->dev, "core_clk");
  377. if (IS_ERR(mdp4_kms->clk)) {
  378. dev_err(dev->dev, "failed to get core_clk\n");
  379. ret = PTR_ERR(mdp4_kms->clk);
  380. goto fail;
  381. }
  382. mdp4_kms->pclk = devm_clk_get(&pdev->dev, "iface_clk");
  383. if (IS_ERR(mdp4_kms->pclk))
  384. mdp4_kms->pclk = NULL;
  385. // XXX if (rev >= MDP_REV_42) { ???
  386. mdp4_kms->lut_clk = devm_clk_get(&pdev->dev, "lut_clk");
  387. if (IS_ERR(mdp4_kms->lut_clk)) {
  388. dev_err(dev->dev, "failed to get lut_clk\n");
  389. ret = PTR_ERR(mdp4_kms->lut_clk);
  390. goto fail;
  391. }
  392. mdp4_kms->axi_clk = devm_clk_get(&pdev->dev, "mdp_axi_clk");
  393. if (IS_ERR(mdp4_kms->axi_clk)) {
  394. dev_err(dev->dev, "failed to get axi_clk\n");
  395. ret = PTR_ERR(mdp4_kms->axi_clk);
  396. goto fail;
  397. }
  398. clk_set_rate(mdp4_kms->clk, config->max_clk);
  399. clk_set_rate(mdp4_kms->lut_clk, config->max_clk);
  400. /* make sure things are off before attaching iommu (bootloader could
  401. * have left things on, in which case we'll start getting faults if
  402. * we don't disable):
  403. */
  404. mdp4_enable(mdp4_kms);
  405. mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0);
  406. mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0);
  407. mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0);
  408. mdp4_disable(mdp4_kms);
  409. mdelay(16);
  410. if (config->iommu) {
  411. mmu = msm_iommu_new(&pdev->dev, config->iommu);
  412. if (IS_ERR(mmu)) {
  413. ret = PTR_ERR(mmu);
  414. goto fail;
  415. }
  416. ret = mmu->funcs->attach(mmu, iommu_ports,
  417. ARRAY_SIZE(iommu_ports));
  418. if (ret)
  419. goto fail;
  420. } else {
  421. dev_info(dev->dev, "no iommu, fallback to phys "
  422. "contig buffers for scanout\n");
  423. mmu = NULL;
  424. }
  425. mdp4_kms->id = msm_register_mmu(dev, mmu);
  426. if (mdp4_kms->id < 0) {
  427. ret = mdp4_kms->id;
  428. dev_err(dev->dev, "failed to register mdp4 iommu: %d\n", ret);
  429. goto fail;
  430. }
  431. ret = modeset_init(mdp4_kms);
  432. if (ret) {
  433. dev_err(dev->dev, "modeset_init failed: %d\n", ret);
  434. goto fail;
  435. }
  436. mutex_lock(&dev->struct_mutex);
  437. mdp4_kms->blank_cursor_bo = msm_gem_new(dev, SZ_16K, MSM_BO_WC);
  438. mutex_unlock(&dev->struct_mutex);
  439. if (IS_ERR(mdp4_kms->blank_cursor_bo)) {
  440. ret = PTR_ERR(mdp4_kms->blank_cursor_bo);
  441. dev_err(dev->dev, "could not allocate blank-cursor bo: %d\n", ret);
  442. mdp4_kms->blank_cursor_bo = NULL;
  443. goto fail;
  444. }
  445. ret = msm_gem_get_iova(mdp4_kms->blank_cursor_bo, mdp4_kms->id,
  446. &mdp4_kms->blank_cursor_iova);
  447. if (ret) {
  448. dev_err(dev->dev, "could not pin blank-cursor bo: %d\n", ret);
  449. goto fail;
  450. }
  451. dev->mode_config.min_width = 0;
  452. dev->mode_config.min_height = 0;
  453. dev->mode_config.max_width = 2048;
  454. dev->mode_config.max_height = 2048;
  455. return kms;
  456. fail:
  457. if (kms)
  458. mdp4_destroy(kms);
  459. return ERR_PTR(ret);
  460. }
  461. static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev)
  462. {
  463. static struct mdp4_platform_config config = {};
  464. #ifdef CONFIG_OF
  465. /* TODO */
  466. config.max_clk = 266667000;
  467. config.iommu = iommu_domain_alloc(&platform_bus_type);
  468. #else
  469. if (cpu_is_apq8064())
  470. config.max_clk = 266667000;
  471. else
  472. config.max_clk = 200000000;
  473. config.iommu = msm_get_iommu_domain(DISPLAY_READ_DOMAIN);
  474. #endif
  475. return &config;
  476. }