omap_dmm_priv.h 4.8 KB

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  1. /*
  2. *
  3. * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
  4. * Author: Rob Clark <rob@ti.com>
  5. * Andy Gross <andy.gross@ti.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation version 2.
  10. *
  11. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12. * kind, whether express or implied; without even the implied warranty
  13. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. */
  16. #ifndef OMAP_DMM_PRIV_H
  17. #define OMAP_DMM_PRIV_H
  18. #define DMM_REVISION 0x000
  19. #define DMM_HWINFO 0x004
  20. #define DMM_LISA_HWINFO 0x008
  21. #define DMM_DMM_SYSCONFIG 0x010
  22. #define DMM_LISA_LOCK 0x01C
  23. #define DMM_LISA_MAP__0 0x040
  24. #define DMM_LISA_MAP__1 0x044
  25. #define DMM_TILER_HWINFO 0x208
  26. #define DMM_TILER_OR__0 0x220
  27. #define DMM_TILER_OR__1 0x224
  28. #define DMM_PAT_HWINFO 0x408
  29. #define DMM_PAT_GEOMETRY 0x40C
  30. #define DMM_PAT_CONFIG 0x410
  31. #define DMM_PAT_VIEW__0 0x420
  32. #define DMM_PAT_VIEW__1 0x424
  33. #define DMM_PAT_VIEW_MAP__0 0x440
  34. #define DMM_PAT_VIEW_MAP_BASE 0x460
  35. #define DMM_PAT_IRQ_EOI 0x478
  36. #define DMM_PAT_IRQSTATUS_RAW 0x480
  37. #define DMM_PAT_IRQSTATUS 0x490
  38. #define DMM_PAT_IRQENABLE_SET 0x4A0
  39. #define DMM_PAT_IRQENABLE_CLR 0x4B0
  40. #define DMM_PAT_STATUS__0 0x4C0
  41. #define DMM_PAT_STATUS__1 0x4C4
  42. #define DMM_PAT_STATUS__2 0x4C8
  43. #define DMM_PAT_STATUS__3 0x4CC
  44. #define DMM_PAT_DESCR__0 0x500
  45. #define DMM_PAT_DESCR__1 0x510
  46. #define DMM_PAT_DESCR__2 0x520
  47. #define DMM_PAT_DESCR__3 0x530
  48. #define DMM_PEG_HWINFO 0x608
  49. #define DMM_PEG_PRIO 0x620
  50. #define DMM_PEG_PRIO_PAT 0x640
  51. #define DMM_IRQSTAT_DST (1<<0)
  52. #define DMM_IRQSTAT_LST (1<<1)
  53. #define DMM_IRQSTAT_ERR_INV_DSC (1<<2)
  54. #define DMM_IRQSTAT_ERR_INV_DATA (1<<3)
  55. #define DMM_IRQSTAT_ERR_UPD_AREA (1<<4)
  56. #define DMM_IRQSTAT_ERR_UPD_CTRL (1<<5)
  57. #define DMM_IRQSTAT_ERR_UPD_DATA (1<<6)
  58. #define DMM_IRQSTAT_ERR_LUT_MISS (1<<7)
  59. #define DMM_IRQSTAT_ERR_MASK (DMM_IRQ_STAT_ERR_INV_DSC | \
  60. DMM_IRQ_STAT_ERR_INV_DATA | \
  61. DMM_IRQ_STAT_ERR_UPD_AREA | \
  62. DMM_IRQ_STAT_ERR_UPD_CTRL | \
  63. DMM_IRQ_STAT_ERR_UPD_DATA | \
  64. DMM_IRQ_STAT_ERR_LUT_MISS)
  65. #define DMM_PATSTATUS_READY (1<<0)
  66. #define DMM_PATSTATUS_VALID (1<<1)
  67. #define DMM_PATSTATUS_RUN (1<<2)
  68. #define DMM_PATSTATUS_DONE (1<<3)
  69. #define DMM_PATSTATUS_LINKED (1<<4)
  70. #define DMM_PATSTATUS_BYPASSED (1<<7)
  71. #define DMM_PATSTATUS_ERR_INV_DESCR (1<<10)
  72. #define DMM_PATSTATUS_ERR_INV_DATA (1<<11)
  73. #define DMM_PATSTATUS_ERR_UPD_AREA (1<<12)
  74. #define DMM_PATSTATUS_ERR_UPD_CTRL (1<<13)
  75. #define DMM_PATSTATUS_ERR_UPD_DATA (1<<14)
  76. #define DMM_PATSTATUS_ERR_ACCESS (1<<15)
  77. /* note: don't treat DMM_PATSTATUS_ERR_ACCESS as an error */
  78. #define DMM_PATSTATUS_ERR (DMM_PATSTATUS_ERR_INV_DESCR | \
  79. DMM_PATSTATUS_ERR_INV_DATA | \
  80. DMM_PATSTATUS_ERR_UPD_AREA | \
  81. DMM_PATSTATUS_ERR_UPD_CTRL | \
  82. DMM_PATSTATUS_ERR_UPD_DATA)
  83. enum {
  84. PAT_STATUS,
  85. PAT_DESCR
  86. };
  87. struct pat_ctrl {
  88. u32 start:4;
  89. u32 dir:4;
  90. u32 lut_id:8;
  91. u32 sync:12;
  92. u32 ini:4;
  93. };
  94. struct pat {
  95. uint32_t next_pa;
  96. struct pat_area area;
  97. struct pat_ctrl ctrl;
  98. uint32_t data_pa;
  99. };
  100. #define DMM_FIXED_RETRY_COUNT 1000
  101. /* create refill buffer big enough to refill all slots, plus 3 descriptors..
  102. * 3 descriptors is probably the worst-case for # of 2d-slices in a 1d area,
  103. * but I guess you don't hit that worst case at the same time as full area
  104. * refill
  105. */
  106. #define DESCR_SIZE 128
  107. #define REFILL_BUFFER_SIZE ((4 * 128 * 256) + (3 * DESCR_SIZE))
  108. /* For OMAP5, a fixed offset is added to all Y coordinates for 1D buffers.
  109. * This is used in programming to address the upper portion of the LUT
  110. */
  111. #define OMAP5_LUT_OFFSET 128
  112. struct dmm;
  113. struct dmm_txn {
  114. void *engine_handle;
  115. struct tcm *tcm;
  116. uint8_t *current_va;
  117. dma_addr_t current_pa;
  118. struct pat *last_pat;
  119. };
  120. struct refill_engine {
  121. int id;
  122. struct dmm *dmm;
  123. struct tcm *tcm;
  124. uint8_t *refill_va;
  125. dma_addr_t refill_pa;
  126. /* only one trans per engine for now */
  127. struct dmm_txn txn;
  128. bool async;
  129. struct completion compl;
  130. struct list_head idle_node;
  131. };
  132. struct dmm_platform_data {
  133. uint32_t cpu_cache_flags;
  134. };
  135. struct dmm {
  136. struct device *dev;
  137. void __iomem *base;
  138. int irq;
  139. struct page *dummy_page;
  140. dma_addr_t dummy_pa;
  141. void *refill_va;
  142. dma_addr_t refill_pa;
  143. /* refill engines */
  144. wait_queue_head_t engine_queue;
  145. struct list_head idle_head;
  146. struct refill_engine *engines;
  147. int num_engines;
  148. atomic_t engine_counter;
  149. /* container information */
  150. int container_width;
  151. int container_height;
  152. int lut_width;
  153. int lut_height;
  154. int num_lut;
  155. /* array of LUT - TCM containers */
  156. struct tcm **tcm;
  157. /* allocation list and lock */
  158. struct list_head alloc_head;
  159. const struct dmm_platform_data *plat_data;
  160. };
  161. #endif